JP2002093934A - Ceramic multilayer wiring board and semiconductor device - Google Patents
Ceramic multilayer wiring board and semiconductor deviceInfo
- Publication number
- JP2002093934A JP2002093934A JP2000279871A JP2000279871A JP2002093934A JP 2002093934 A JP2002093934 A JP 2002093934A JP 2000279871 A JP2000279871 A JP 2000279871A JP 2000279871 A JP2000279871 A JP 2000279871A JP 2002093934 A JP2002093934 A JP 2002093934A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- ceramic multilayer
- metal pad
- conductive resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、セラミック多層配
線基板およびセラミック多層配線基板に半導体素子を搭
載した半導体装置に関するものである。The present invention relates to a ceramic multilayer wiring board and a semiconductor device having a semiconductor element mounted on the ceramic multilayer wiring board.
【０００２】[0002]
【従来の技術】従来、半導体素子をセラミック多層配線
基板に搭載するにあたって、半導体素子をセラミック多
層配線基板に接着固定し、半導体素子の電極パッドとセ
ラミック多層配線基板の金属パッドとをボンディングワ
イヤによって電気的に接続する方法が採用されている。
このワイヤボンディング法は、半導体素子の電極パッド
とセラミック多層配線基板の金属パッドとをボンディン
グワイヤによって確実、強固に接続できるが、半導体装
置をより小さくすることができないという問題があっ
た。2. Description of the Related Art Conventionally, when a semiconductor element is mounted on a ceramic multilayer wiring board, the semiconductor element is bonded and fixed to the ceramic multilayer wiring board, and an electrode pad of the semiconductor element and a metal pad of the ceramic multilayer wiring board are electrically connected by bonding wires. The method of making a connection is adopted.
According to this wire bonding method, the electrode pads of the semiconductor element and the metal pads of the ceramic multilayer wiring board can be reliably and firmly connected by bonding wires, but there is a problem that the semiconductor device cannot be made smaller.
【０００３】このため、ワイヤボンディング法に代わっ
て、半導体装置をより小さくすることができるフリップ
チップ法と呼ばれる接続方法が試みられている。このフ
リップチップ法は、半導体素子の電極パッドに予め被着
形成された導体バンプとセラミック多層配線基板の金属
パッドとを対向させ、導電性樹脂を介して導体バンプと
金属パッドとを接続する方法である。For this reason, instead of the wire bonding method, a connection method called a flip chip method which can make a semiconductor device smaller has been attempted. This flip-chip method is a method in which a conductive bump previously formed on an electrode pad of a semiconductor element and a metal pad of a ceramic multilayer wiring board are opposed to each other, and the conductive bump and the metal pad are connected via a conductive resin. is there.
【０００４】図１の（Ａ）、（Ｂ）は、フリップチップ
法により半導体素子をセラミック多層配線基板に搭載し
た半導体装置の断面図および平面図である。１は半導体
素子、２は半導体素子１の下面に形成された電極パッ
ド、３は電極パッド２に被着形成されたＡｕより成る導
体バンプ、４はセラミック多層配線基板、５はセラミッ
ク多層配線基板４に予め形成された金属パッド、６は導
電性樹脂、７は半導体素子１とセラミック多層配線基板
４の間隙に注入された封止樹脂である。FIGS. 1A and 1B are a cross-sectional view and a plan view of a semiconductor device in which a semiconductor element is mounted on a ceramic multilayer wiring board by a flip-chip method. 1 is a semiconductor element, 2 is an electrode pad formed on the lower surface of the semiconductor element 1, 3 is a conductor bump made of Au adhered to the electrode pad 2, 4 is a ceramic multilayer wiring board, 5 is a ceramic multilayer wiring board 4. Is a conductive resin, 6 is a sealing resin injected into a gap between the semiconductor element 1 and the ceramic multilayer wiring board 4.
【０００５】このうち、セラミック多層配線基板４の形
成にあたっては、セラミックのグリーンシート表面に高
融点金属からなる導体ペーストをスクリーン印刷法によ
り印刷塗布し、これを約１５００℃の温度で焼成する厚
膜加工法が用いられている。In forming the ceramic multi-layer wiring board 4, a conductor paste made of a high melting point metal is applied by printing on a surface of a ceramic green sheet by a screen printing method, and is fired at a temperature of about 1500 ° C. Processing methods are used.
【０００６】近年、半導体素子１の高密度化、複数の半
導体素子１を１つのセラミック多層配線基板４に搭載す
る半導体装置のモジュール化、半導体装置の小型薄型化
が進み、半導体装置を構成するセラミック多層配線基板
４にも半導体素子１と同様の高密度化が求められてい
る。このため、従来の厚膜加工法では金属パッド５の微
細化が困難であった。In recent years, the density of the semiconductor element 1 has been increased, the modularization of a semiconductor device in which a plurality of semiconductor elements 1 are mounted on one ceramic multilayer wiring board 4, and the size and thickness of the semiconductor device have been reduced. The multilayer wiring board 4 is also required to have the same high density as the semiconductor element 1. For this reason, it has been difficult to miniaturize the metal pad 5 by the conventional thick film processing method.
【０００７】上記問題を解決するために２つの手法が提
案されている。１つは、セラミック基板の主面を研磨加
工した後、スパッタリング法、フォトリソグラフィ法、
エッチング法等の薄膜形成法により金属パッドを形成す
るセラミック配線基板の製造方法である（従来例１：特
許第２６３１１１８号公報参照）。Two approaches have been proposed to solve the above problem. First, after polishing the main surface of the ceramic substrate, a sputtering method, a photolithography method,
This is a method of manufacturing a ceramic wiring board in which metal pads are formed by a thin film forming method such as an etching method (conventional example 1: see Japanese Patent No. 2631118).
【０００８】もう一つは、セラミック基板の表面を算術
平均粗さＲａが０．５μｍ以下となるように研磨した
後、感光性導体ペーストをパターン加工し、焼成するこ
とによって微細な配線導体層を形成する配線回路基板の
製造方法である（従来例２：特開２０００−１１４６９
１号公報参照）。The other is to polish a fine wiring conductor layer by polishing the surface of the ceramic substrate so that the arithmetic average roughness Ra is 0.5 μm or less, and then patterning and firing the photosensitive conductor paste. This is a method for manufacturing a printed circuit board to be formed (conventional example 2: JP-A-2000-11469).
No. 1).
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、フリッ
プチップ法によって半導体素子１をセラミック多層配線
基板４に搭載する半導体装置をさらに小型化するため
に、半導体素子１およびセラミック多層配線基板４の隣
接する電極パッド２または金属パッド５の間隔をより小
さくした場合、導電性樹脂６が金属パッド５間のセラミ
ック多層配線基板４の主面に流れ出し、隣接する金属パ
ッド５がショートするという問題があった。However, in order to further reduce the size of the semiconductor device in which the semiconductor element 1 is mounted on the ceramic multilayer wiring board 4 by the flip-chip method, adjacent electrodes of the semiconductor element 1 and the ceramic multilayer wiring board 4 are required. If the spacing between the pads 2 or the metal pads 5 is made smaller, the conductive resin 6 flows out to the main surface of the ceramic multilayer wiring board 4 between the metal pads 5, and there is a problem that the adjacent metal pads 5 are short-circuited.
【００１０】またこの問題を解消するために、セラミッ
ク多層配線基板４の金属パッド５から導電性樹脂６が流
れ出さないように、セラミック多層配線基板４の主面に
おいて、金属パッド５の上面だけが露出するように金属
パッド５間に樹脂より成るダムコート層を設ける構成も
考えられる。しかしながら、ダムコート層を形成する
際、金属パッド５上面にダムコート層の樹脂が付着し易
く、その場合導体バンプ３と金属パッド５との接続不良
を引き起こしたり、ダムコート層の樹脂を硬化させる
際、ダムコート材の硬化収縮によってセラミック多層配
線基板４に反りが発生したりする問題があった。さら
に、ダムコート層の形成工程が増えるため、製造コスト
も高くなるという問題もあった。In order to solve this problem, only the upper surface of the metal pad 5 is formed on the main surface of the ceramic multilayer wiring board 4 so that the conductive resin 6 does not flow out from the metal pad 5 of the ceramic multilayer wiring board 4. A configuration in which a dam coat layer made of resin is provided between the metal pads 5 so as to be exposed is also conceivable. However, when the dam coat layer is formed, the resin of the dam coat layer easily adheres to the upper surface of the metal pad 5, and in this case, poor connection between the conductor bump 3 and the metal pad 5 is caused, or when the resin of the dam coat layer is cured, the dam coat layer is hardly damaged. There is a problem that the ceramic multilayer wiring board 4 is warped due to the shrinkage of the material upon curing. Further, there is a problem in that the number of steps for forming the dam coat layer is increased, so that the manufacturing cost is also increased.
【００１１】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、フリップチップ法によっ
て半導体素子を搭載するセラミック多層配線基板におい
て、導電性樹脂が金属パッドの上面全体に広がり、半導
体素子の電極パッドに被着形成された導体バンプとセラ
ミック多層配線基板の金属パッドとが導電性樹脂を介し
て強固に接着され、かつ導電性樹脂がセラミック多層配
線基板の主面に流れ出すことを抑制し、隣接する金属パ
ッドがショートすることを防止できるセラミック多層配
線基板を提供することにある。また、上記のセラミック
多層配線基板を用いて構成される、より小型で信頼性の
高い半導体装置を提供することにある。Accordingly, the present invention has been completed in view of the above circumstances, and an object of the present invention is to provide a ceramic multilayer wiring board on which a semiconductor element is mounted by a flip chip method, in which a conductive resin spreads over the entire upper surface of a metal pad. The conductive bumps adhered to the electrode pads of the semiconductor element and the metal pads of the ceramic multilayer wiring board are firmly bonded via the conductive resin, and the conductive resin flows to the main surface of the ceramic multilayer wiring board. It is an object of the present invention to provide a ceramic multilayer wiring board capable of suppressing the occurrence of short circuit between adjacent metal pads. It is another object of the present invention to provide a smaller and more reliable semiconductor device that is configured using the above-described ceramic multilayer wiring board.
【００１２】[0012]
【課題を解決するための手段】本発明のセラミック多層
配線基板は、半導体素子を搭載する側の主面に導電性樹
脂に覆われた金属パッドが形成され、前記金属パッドお
よび前記導電性樹脂が前記半導体素子の下面の電極パッ
ドに導体バンプを介して接続されるセラミック多層配線
基板であって、前記主面の算術平均粗さＲa1が０．０１
〜０．１μｍであり、かつ前記金属パッドの上面の算術
平均粗さＲa2が０．１〜０．５μｍであることを特徴と
する。In the ceramic multilayer wiring board of the present invention, a metal pad covered with a conductive resin is formed on a main surface on a side on which a semiconductor element is mounted, and the metal pad and the conductive resin are formed. A ceramic multilayer wiring board connected to electrode pads on the lower surface of said semiconductor element via conductive bumps, wherein said main surface has an arithmetic average roughness Ra1 of 0.01.
0.1 to 0.5 μm, and the arithmetic average roughness Ra2 of the upper surface of the metal pad is 0.1 to 0.5 μm.
【００１３】本発明のセラミック多層配線基板によれ
ば、セラミック多層配線基板の主面の算術平均粗さＲa1
を０．０１〜０．１μｍとしたことにより、導電性樹脂
が金属パッドからセラミック表面に流れ出しても、セラ
ミック多層配線基板の主面が平滑に研磨されているた
め、導電性樹脂の表面張力によって流れ出しが止まり、
隣接する金属パッドが、流れ出した導電性樹脂を介して
ショートすることを防ぐことができる。また、金属パッ
ドの上面の算術平均粗さＲa2を０．１〜０．５μｍとし
たことにより、導電性樹脂が金属パッド上面全体に広が
り易くなり、半導体素子の導体バンプとセラミック多層
配線基板の金属パッドとが、強固、確実に、低抵抗な状
態で接続される。According to the ceramic multilayer wiring board of the present invention, the arithmetic mean roughness Ra1 of the main surface of the ceramic multilayer wiring board is obtained.
Is set to 0.01 to 0.1 μm, even if the conductive resin flows out of the metal pad to the ceramic surface, the main surface of the ceramic multilayer wiring board is polished smoothly. The flow stops,
It is possible to prevent the adjacent metal pad from being short-circuited via the conductive resin that has flowed out. Further, by setting the arithmetic average roughness Ra2 of the upper surface of the metal pad to 0.1 to 0.5 μm, the conductive resin can easily spread over the entire upper surface of the metal pad, and the conductive bump of the semiconductor element and the metal of the ceramic multilayer wiring board can be easily spread. The pads are connected firmly, reliably, and with low resistance.
【００１４】また、本発明の半導体装置は、上記本発明
のセラミック多層配線基板の前記金属パッドおよび前記
導電性樹脂に前記半導体素子の下面の前記電極パッドが
前記導体バンプを介して接続されていることを特徴とす
るものである。In the semiconductor device of the present invention, the electrode pad on the lower surface of the semiconductor element is connected to the metal pad and the conductive resin of the ceramic multilayer wiring board of the present invention via the conductive bump. It is characterized by the following.
【００１５】本発明の半導体装置によれば、上記のよう
な特徴を持つセラミック多層配線基板を用いることによ
り、小型で信頼性の高いものを提供することができる。According to the semiconductor device of the present invention, by using the ceramic multilayer wiring board having the above-described features, it is possible to provide a small and highly reliable one.
【００１６】[0016]
【発明の実施の形態】本発明のセラミック多層配線基板
およびこれを用いた半導体装置の基本構造は、従来と同
様であり、図１に基づいて説明する。セラミック多層配
線基板４は例えば、酸化アルミニウム（Ａｌ2Ｏ3）質焼
結体、窒化アルミニウム（ＡｌＮ）質焼結体、炭化珪素
（ＳｉＣ）質焼結体、ガラスセラミックス焼結体、窒化
珪素（Ｓｉ3Ｎ4）質焼結体のうち少なくとも１種より成
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic structure of a ceramic multilayer wiring board and a semiconductor device using the same according to the present invention are the same as those of the prior art, and will be described with reference to FIG. The ceramic multilayer wiring board 4 is made of, for example, an aluminum oxide (Al 2 O 3 ) sintered body, an aluminum nitride (AlN) based sintered body, a silicon carbide (SiC) based sintered body, a glass ceramic sintered body, a silicon nitride ( It is made of at least one of Si 3 N 4 ) sintered bodies.
【００１７】本発明において、セラミック多層配線基板
４の少なくとも１つの主面は、表面研磨装置によって、
算術平均粗さＲa1が０．０１〜０．１μｍになるように
研磨される。０．０１μｍ未満になるように研磨される
と、表面の平滑性の上では好ましいが、研磨工程での研
磨圧および研磨熱によって、応力が発生し、セラミック
多層配線基板４に反りが発生しやすい。この反りによっ
てフリップチップ法によって半導体素子１を接続するこ
とが困難になりやすい。また、セラミック表面が平滑に
なると薄膜配線層よりなる金属パッド５との接触面積が
小さくなり、いわゆるアンカー効果が小さくなって、セ
ラミック多層配線基板４と金属パッド５との密着強度が
弱くなってしまう。一方、０．１μｍを超えると、導電
性樹脂６がセラミック多層配線基板４の表面で濡れ易く
なり、表面張力による流れ防止作用が十分に働かなくな
ってしまう。In the present invention, at least one principal surface of the ceramic multilayer wiring board 4 is formed by a surface polishing device.
Polishing is performed so that the arithmetic average roughness Ra1 becomes 0.01 to 0.1 μm. Polishing to a thickness of less than 0.01 μm is preferable in terms of surface smoothness, but stress is generated by the polishing pressure and polishing heat in the polishing step, and the ceramic multilayer wiring board 4 is likely to be warped. . The warpage tends to make it difficult to connect the semiconductor element 1 by the flip chip method. Further, when the ceramic surface becomes smooth, the contact area with the metal pad 5 formed of the thin film wiring layer becomes small, so-called anchor effect becomes small, and the adhesion strength between the ceramic multilayer wiring substrate 4 and the metal pad 5 becomes weak. . On the other hand, when the thickness exceeds 0.1 μm, the conductive resin 6 is easily wetted on the surface of the ceramic multilayer wiring board 4, and the effect of preventing flow due to surface tension does not work sufficiently.
【００１８】金属パッド５は、蒸着法、スパッタリング
法、ＣＶＤ法、メッキ法等の薄膜形成法により成膜さ
れ、フォトリソグラフィ法、エッチング法、リフトオフ
法等によってパターン加工される。金属パッド５は、基
本的に下層側より密着金属層、拡散防止層、主導体層の
３層からなり、密着金属層は、Ｔｉ、Ｃｒ、Ｔａ、Ｎ
ｂ、Ｎｉ−Ｃｒ合金、Ｔｉ−Ｗ合金またはＴａ2Ｎ等の
うち少なくとも１種より形成される。密着金属層の厚さ
は０．０１〜０．２μｍ程度が良い。０．０１μｍ未満
では、強固に密着することが困難となる傾向にあり、
０．２μｍを超えると、成膜時の内部応力によって剥離
が生じ易くなる。The metal pad 5 is formed by a thin film forming method such as a vapor deposition method, a sputtering method, a CVD method, and a plating method, and is patterned by a photolithography method, an etching method, a lift-off method, or the like. The metal pad 5 is basically composed of three layers from the lower side: an adhesion metal layer, a diffusion prevention layer, and a main conductor layer. The adhesion metal layer is made of Ti, Cr, Ta, N
b, Ni-Cr alloy, is formed from at least one of such Ti-W alloy or Ta 2 N. The thickness of the adhesion metal layer is preferably about 0.01 to 0.2 μm. If it is less than 0.01 μm, it tends to be difficult to firmly adhere,
If the thickness exceeds 0.2 μm, separation easily occurs due to internal stress during film formation.
【００１９】拡散防止層はＰｔ、Ｐｄ、Ｒｈ、Ｒｕ、Ｎ
ｉ、Ｎｉ−Ｃｒ合金またはＴｉ−Ｗ合金等のうち少なく
とも１種からなる。拡散防止層の厚さは０．０５〜３μ
ｍ程度が良く、０．０５μｍ未満ではピンホール等の欠
陥のために拡散防止層としての機能を果たしにくい傾向
にあり、３μｍを超えると成膜時の内部応力により剥離
が生じ易くなる。The diffusion preventing layer is made of Pt, Pd, Rh, Ru, N
i, Ni-Cr alloy, Ti-W alloy or the like. The thickness of the diffusion prevention layer is 0.05 to 3μ.
When the thickness is less than 0.05 μm, it tends to be difficult to function as a diffusion preventing layer due to defects such as pinholes. When the thickness exceeds 3 μm, peeling tends to occur due to internal stress during film formation.
【００２０】主導体層は、Ｃｕ、Ｎｉ、ＡｕまたはＡｇ
等のうち少なくとも１種より形成される。主導体層にＣ
ｕを用いた場合は、酸化されないようにＮｉメッキおよ
びＡｕメッキによる表面仕上げを行う。主導体層の厚さ
は０．１〜５μｍ程度が良い。０．１μｍ未満では、電
気抵抗が大きくなる傾向にあり、５μｍを超えると成膜
時の内部応力により剥離を生じ易くなり、また主導体層
の多くは貴金属で高価であることから、薄く形成される
ことがコストの点で好ましい。The main conductor layer is made of Cu, Ni, Au or Ag.
And the like. C for main conductor layer
When u is used, the surface is finished by Ni plating and Au plating so as not to be oxidized. The thickness of the main conductor layer is preferably about 0.1 to 5 μm. If the thickness is less than 0.1 μm, the electrical resistance tends to increase. If the thickness is more than 5 μm, separation tends to occur due to internal stress during film formation, and most of the main conductor layers are formed of thin precious metals because they are expensive. Is preferable in terms of cost.
【００２１】金属パッド５の上面の算術平均粗さＲa2は
０．１〜０．５μｍとなるように加工される。スパッタ
リング法、蒸着法、ＣＶＤ法等の薄膜形成法によって形
成された金属パッド５の上面の算術平均粗さＲa2は０．
０５μｍ程度であり、この状態で金属パッド５とすれ
ば、導電性樹脂６の金属パッド５表面での表面張力が大
きすぎて広がり難くなる。そこで、金属パッド５の上面
の算術平均粗さＲa2が０．１〜０．５μｍとなるよう
に、例えば、薄膜形成法によって形成された金属パッド
５の上面にメッキ法などによって粒径の大きな金属膜を
被着させる。また、薄膜形成法によって形成された金属
パッド５の上面をドライエッチング法、ディップエッチ
ング法、スプレーエッチング法、ブラスト法等によって
粗面化してもよい。The upper surface of the metal pad 5 is processed to have an arithmetic average roughness Ra2 of 0.1 to 0.5 μm. The arithmetic average roughness Ra2 of the upper surface of the metal pad 5 formed by a thin film forming method such as a sputtering method, a vapor deposition method, and a CVD method is 0.
If the metal pad 5 is formed in this state, the surface tension of the conductive resin 6 on the surface of the metal pad 5 is too large to spread easily. Therefore, for example, the upper surface of the metal pad 5 formed by the thin film forming method is plated on the upper surface of the metal pad 5 by a plating method or the like so that the arithmetic average roughness Ra2 of the upper surface of the metal pad 5 is 0.1 to 0.5 μm. Deposit the membrane. Further, the upper surface of the metal pad 5 formed by the thin film forming method may be roughened by a dry etching method, a dip etching method, a spray etching method, a blast method or the like.
【００２２】このように、金属パッド５の上面の算術平
均粗さＲa2が０．１μｍ未満の場合、導電性樹脂６が表
面張力によって広がりにくい傾向にある。一方、０．５
μｍを超えると微細な凹凸のために導電性樹脂６が広が
りにくい傾向がある。As described above, when the arithmetic average roughness Ra2 of the upper surface of the metal pad 5 is less than 0.1 μm, the conductive resin 6 tends to be difficult to spread due to surface tension. On the other hand, 0.5
If it exceeds μm, the conductive resin 6 tends to be difficult to spread due to fine irregularities.
【００２３】次に、半導体素子１をセラミック多層配線
基板４に搭載する方法について説明する。まず、半導体
素子１の電極パッド２にワイヤボンディング装置によっ
て、Ａｕ，Ａｌ等から成る導体バンプ３を形成する。導
体バンプ３は電極パッド２と同じ程度の大きさの底面を
もった略円錐形である。導体バンプ3とセラミック多層
配線基板４の金属パッド５とを接続する導電性樹脂６
は、金属パッド５表面にディスペンス法、印刷法、転写
法等により塗布する。また、セラミック多層配線基板４
の導体バンプ３表面にディスペンス法、転写法等によっ
て塗布しても構わない。導電性樹脂６は、エポキシ樹脂
等の樹脂成分に、Ａｇ、Ｐｄ等の導電性粒子と有機溶剤
とを含有させたものを用いる。Next, a method for mounting the semiconductor element 1 on the ceramic multilayer wiring board 4 will be described. First, a conductor bump 3 made of Au, Al, or the like is formed on an electrode pad 2 of a semiconductor element 1 by a wire bonding apparatus. The conductive bump 3 is substantially conical with a bottom surface approximately the same size as the electrode pad 2. A conductive resin 6 for connecting the conductive bumps 3 and the metal pads 5 of the ceramic multilayer wiring board 4
Is applied to the surface of the metal pad 5 by a dispense method, a printing method, a transfer method, or the like. The ceramic multilayer wiring board 4
May be applied to the surface of the conductive bump 3 by a dispensing method, a transfer method, or the like. As the conductive resin 6, a resin component such as an epoxy resin containing conductive particles such as Ag and Pd and an organic solvent is used.
【００２４】半導体素子１とセラミック多層配線基板４
との接続は、半導体素子１とセラミック多層配線基板４
とを導体バンプ３と金属パッド５とが接続するように位
置合わせし、半導体素子１の導体バンプ３が形成されて
いない面より所定の圧力によって半導体素子１を加圧す
る。このとき、導体バンプ３の先端が潰れ、導電性樹脂
６を介して導体バンプ３と金属パッド５とが接続され
る。この後、封止樹脂７を半導体素子１とセラミック多
層配線基板４との間隙にディスペンス法等によって注入
し、加熱することで半導体装置が完成する。Semiconductor element 1 and ceramic multilayer wiring board 4
Connection between the semiconductor element 1 and the ceramic multilayer wiring board 4
Are aligned so that the conductor bumps 3 and the metal pads 5 are connected, and the semiconductor element 1 is pressurized by a predetermined pressure from the surface of the semiconductor element 1 where the conductor bumps 3 are not formed. At this time, the tip of the conductor bump 3 is crushed, and the conductor bump 3 and the metal pad 5 are connected via the conductive resin 6. Thereafter, the sealing resin 7 is injected into the gap between the semiconductor element 1 and the ceramic multilayer wiring board 4 by a dispensing method or the like, and the semiconductor device is completed by heating.
【００２５】かくして、本発明は、導電性樹脂６が金属
パッド５からセラミック表面に流れ出しても、セラミッ
ク多層配線基板４の主面が平滑に研磨されているため、
導電性樹脂６の表面張力によって流れ出しが止まり、隣
接する金属パッド５が、流れ出した導電性樹脂６を介し
てショートすることを防ぐことができる。また、導電性
樹脂６が金属パッド５上面全体に広がり易くなり、導体
バンプ３と金属パッド５とが、強固、確実に、低抵抗な
状態で接続される。Thus, according to the present invention, even if the conductive resin 6 flows out of the metal pad 5 to the ceramic surface, the main surface of the ceramic multilayer wiring board 4 is polished smoothly.
The flowing out is stopped by the surface tension of the conductive resin 6, and the short circuit of the adjacent metal pad 5 via the flowing out conductive resin 6 can be prevented. In addition, the conductive resin 6 easily spreads over the entire upper surface of the metal pad 5, and the conductive bump 3 and the metal pad 5 are connected firmly, reliably, and with low resistance.
【００２６】[0026]
【実施例】本発明の実施例を以下に説明する。Embodiments of the present invention will be described below.
【００２７】（実施例）図１のセラミック多層配線基板
４を以下の工程［１］〜［５］により作製した。(Example) The ceramic multilayer wiring board 4 of FIG. 1 was manufactured by the following steps [1] to [5].
【００２８】［１］セラミックスのグリーンシートにそ
の上下間を導通させる貫通導体通用の貫通孔を形成し、
このグリーンシートの貫通孔や配線パターン部にタング
ステン導体ペーストを印刷塗布した。このように構成し
たグリーンシートを配線パターンが電気的に接続される
ように積層し、約１５００℃の温度で焼成し、ベース基
板を得た。[1] A through hole is formed in a ceramic green sheet for passing a through conductor for conducting between the top and bottom of the green sheet.
A tungsten conductor paste was printed and applied to the through holes and the wiring pattern portions of the green sheet. The green sheets thus configured were stacked so that the wiring patterns were electrically connected, and fired at a temperature of about 1500 ° C. to obtain a base substrate.
【００２９】［２］このベース基板の表面をアルミナの
砥粒を用いて研磨し、算術平均粗さＲa1を種々の値とし
た５種のサンプル（表１）を作製した。[2] The surface of the base substrate was polished using alumina abrasive grains to produce five types of samples (Table 1) having various values of arithmetic average roughness Ra1.
【００３０】［３］ベース基板の研磨面に、スパッタリ
ング法によって、厚さ０．１μｍのＴｉ層（密着金属
層）、厚さ２μｍのＴｉ−Ｗ合金層（拡散防止層）、厚
さ４μｍのＣｕ層（主導体層）を順次成膜し、フォトリ
ソグラフィ法およびエッチング法によりパターン加工し
て金属パッド５を作製した。金属パッド５の大きさは直
径４０μｍの円形で、隣接する電極パッド５との間隔は
３０μｍとした。[3] On the polished surface of the base substrate, a 0.1 μm-thick Ti layer (adhesion metal layer), a 2 μm-thick Ti—W alloy layer (diffusion prevention layer), and a 4 μm-thick A Cu layer (main conductor layer) was sequentially formed and patterned by photolithography and etching to produce a metal pad 5. The size of the metal pad 5 was a circle having a diameter of 40 μm, and the interval between the adjacent electrode pads 5 was 30 μm.
【００３１】［４］約８５０℃の熱処理後、ドライエッ
チング法およびディップエッチング法によって、Ｃｕ層
表面の算術平均粗さが０．０９μｍ程度になるようにし
た。[4] After the heat treatment at about 850 ° C., the arithmetic average roughness of the Cu layer surface was adjusted to about 0.09 μm by dry etching and dip etching.
【００３２】［５］Ｃｕ層表面が酸化しないように、無
電解メッキによって、厚さ２μｍのＮｉ層、厚さ０．２
μｍのＡｕ層を順次被着させた。Ａｕ層表面、即ち金属
パッド５の上面の算術平均粗さＲa2は０．１２μｍであ
った。[5] In order to prevent the Cu layer surface from being oxidized, a Ni layer having a thickness of 2 μm and a thickness of 0.2
A μm Au layer was sequentially deposited. The arithmetic average roughness Ra2 of the Au layer surface, that is, the upper surface of the metal pad 5 was 0.12 μm.
【００３３】上記実施例にて作製したセラミック多層配
線基板４（表１のサンプル番号１〜５）について、Ａｇ
−Ｐｄ合金の粒子を含む導電性樹脂６を金属パッド５に
塗布し、導電性樹脂６の流れ出しを評価した。For the ceramic multilayer wiring board 4 (sample numbers 1 to 5 in Table 1) manufactured in the above embodiment, Ag
A conductive resin 6 containing particles of a -Pd alloy was applied to the metal pad 5, and the outflow of the conductive resin 6 was evaluated.
【００３４】５種類のサンプルのセラミック多層配線基
板４の表面の算術平均粗さＲa1と、上記評価結果をまと
めたものを表１に示す。Table 1 summarizes the arithmetic average roughness Ra1 of the surface of the ceramic multilayer wiring board 4 of the five types of samples and the above evaluation results.
【００３５】[0035]
【表１】 [Table 1]
【００３６】この結果から、セラミック多層配線基板４
の算術平均粗さＲa1は０．０１〜０．１μｍの範囲にお
いて、導電性樹脂６の流れ出しを止め、隣接する金属パ
ッド５が導電性樹脂６を介してショートしないことがわ
かった。From these results, it is found that the ceramic multilayer wiring board 4
When the arithmetic average roughness Ra1 is in the range of 0.01 to 0.1 μm, it was found that the flow of the conductive resin 6 was stopped and the adjacent metal pad 5 did not short-circuit via the conductive resin 6.
【００３７】なお、本発明は上記実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲内において
種々の変更を行なうことは何等差し支えない。It should be noted that the present invention is not limited to the above embodiment, and that various changes may be made without departing from the spirit of the present invention.
【００３８】[0038]
【発明の効果】本発明は、半導体素子を搭載する側の主
面に導電性樹脂に覆われた金属パッドが形成され、金属
パッドおよび導電性樹脂が半導体素子の下面の電極パッ
ドに導体バンプを介して接続されており、主面の算術平
均粗さＲa1が０．０１〜０．１μｍであり、かつ金属パ
ッドの上面の算術平均粗さＲa2が０．１〜０．５μｍで
あることにより、導電性樹脂が金属パッドからセラミッ
ク表面に流れ出しても、セラミック多層配線基板の主面
が平滑に研磨されているため、導電性樹脂の表面張力に
よって流れ出しが止まり、隣接する金属パッドが、流れ
出した導電性樹脂を介してショートすることを防ぐこと
ができる。また、導電性樹脂が金属パッド上面全体に広
がり易くなり、半導体素子の導体バンプとセラミック多
層配線基板の金属パッドとが強固、確実に、低抵抗な状
態で接続される。According to the present invention, a metal pad covered with a conductive resin is formed on a main surface on a side on which a semiconductor element is mounted, and the metal pad and the conductive resin form a conductive bump on an electrode pad on a lower surface of the semiconductor element. The arithmetic average roughness Ra1 of the main surface is 0.01 to 0.1 μm, and the arithmetic average roughness Ra2 of the upper surface of the metal pad is 0.1 to 0.5 μm. Even if the conductive resin flows from the metal pad to the ceramic surface, the main surface of the ceramic multilayer wiring board is polished smoothly, so that the flow stops due to the surface tension of the conductive resin, and the adjacent metal pad flows out of the conductive pad. It is possible to prevent a short circuit via the conductive resin. In addition, the conductive resin easily spreads over the entire upper surface of the metal pad, and the conductive bump of the semiconductor element and the metal pad of the ceramic multilayer wiring board are connected firmly, reliably, and in a low resistance state.
【００３９】また本発明の半導体装置は、上記のような
セラミック多層配線基板を用いて構成されるので、上記
と同様の作用効果を有するとともに、小型で信頼性の高
いものとなる。Further, since the semiconductor device of the present invention is constituted by using the above-mentioned ceramic multilayer wiring board, it has the same function and effect as described above, and is compact and highly reliable.
【図１】（Ａ）はフリップチップ法によって半導体素子
を接続したセラミック多層配線基板の断面図、（Ｂ）は
セラミック多層配線基板の平面図である。1A is a cross-sectional view of a ceramic multilayer wiring board to which semiconductor elements are connected by a flip chip method, and FIG. 1B is a plan view of the ceramic multilayer wiring board.
１：半導体素子 ２：電極パッド ３：導体バンプ ４：セラミック多層配線基板 ５：金属パッド ６：導電性樹脂 ７：封止樹脂 1: semiconductor element 2: electrode pad 3: conductive bump 4: ceramic multilayer wiring board 5: metal pad 6: conductive resin 7: sealing resin
Claims (2)
脂に覆われた金属パッドが形成され、前記金属パッドお
よび前記導電性樹脂が前記半導体素子の下面の電極パッ
ドに導体バンプを介して接続されるセラミック多層配線
基板であって、前記主面の算術平均粗さＲa1が０．０１
〜０．１μｍであり、かつ前記金属パッドの上面の算術
平均粗さＲa2が０．１〜０．５μｍであることを特徴と
するセラミック多層配線基板。A metal pad covered with a conductive resin is formed on a main surface on a side on which a semiconductor element is mounted, and the metal pad and the conductive resin are connected to an electrode pad on a lower surface of the semiconductor element via a conductive bump. Wherein the arithmetic mean roughness Ra1 of the main surface is 0.01.
A multi-layer ceramic wiring board, wherein the arithmetic average roughness Ra2 of the upper surface of the metal pad is 0.1 to 0.5 μm.
前記金属パッドおよび前記導電性樹脂に前記半導体素子
の下面の前記電極パッドが前記導体バンプを介して接続
されていることを特徴とする半導体装置。2. The semiconductor according to claim 1, wherein the electrode pads on the lower surface of the semiconductor element are connected to the metal pads and the conductive resin of the ceramic multilayer wiring board via the conductor bumps. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000279871A JP2002093934A (en) | 2000-09-14 | 2000-09-14 | Ceramic multilayer wiring board and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000279871A JP2002093934A (en) | 2000-09-14 | 2000-09-14 | Ceramic multilayer wiring board and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002093934A true JP2002093934A (en) | 2002-03-29 |
Family
ID=18764811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000279871A Pending JP2002093934A (en) | 2000-09-14 | 2000-09-14 | Ceramic multilayer wiring board and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002093934A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014143305A (en) * | 2013-01-24 | 2014-08-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device mounting structure and semiconductor device manufacturing method |
| US10707388B2 (en) | 2017-09-27 | 2020-07-07 | Nichia Corporation | Semiconductor device, and method for manufacturing semiconductor device |
-
2000
- 2000-09-14 JP JP2000279871A patent/JP2002093934A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014143305A (en) * | 2013-01-24 | 2014-08-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device mounting structure and semiconductor device manufacturing method |
| US10707388B2 (en) | 2017-09-27 | 2020-07-07 | Nichia Corporation | Semiconductor device, and method for manufacturing semiconductor device |
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