JP2002091392A - Liquid crystal driving method and drive controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of obtaining a satisfactory display state in which there is no afterimage (persistent image) with respect to video signals of all sorts of types. SOLUTION: In a liquid crystal display device 0102 displaying input video information 0101 from a video signal generating device on a liquid crystal panel 0112, the display device is provided with a comparator circuit 0203 judging the presence or absence of difference by comparing past input video information with present video information, a first driving circuit 0210 outputting an alternating current signal having a first cycle in order to prevent the application of DC voltage to the liquid crystal panel, a second driving circuit 0213 which is different from the first driving circuit and which outputs a second alternating current signal and a selecting circuit 0215 which selects either the alternating current signal having the first cycle or the second alternating current signal having the second cycle which are to be outputted respectively from the first driving circuit and the second driving circuit according to the compared result of the comparator circuit and outputs the selected signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using a liquid crystal display device, and more particularly to a liquid crystal display device for preventing a steady DC voltage from being applied and obtaining a good display without image sticking (afterimage). Things.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device for displaying input video information from a video signal generator, a method of removing a DC voltage from being applied to a liquid crystal panel and preventing image sticking of the liquid crystal panel, that is, display of an afterimage, includes For example, as disclosed in JP-A-09-27934, an input video signal is gamma-corrected by a gamma correction circuit according to the display characteristics of a liquid crystal panel, and then supplied to a bipolar video signal generation circuit. I was The bipolar video signal generation circuit generates a first video signal of a positive polarity and a second video signal of a negative polarity with predetermined amplitude, and supplies the first and second video signals to a gate circuit. In the gate circuit, the first and second video signals are switched at regular intervals by the inversion control signal, and the selected first or second video signal is supplied to the limiter circuit. In the limiter circuit, the amplitude of the selected first and second video signals is limited, and the first or second video signal whose amplitude has been limited by the limiter circuit is supplied to the liquid crystal panel via the buffer circuit.

FIG. 22 shows an example of a configuration of a video signal processing circuit disclosed in Japanese Patent Application Laid-Open No. 09-27934 which enables prevention of burn-in of a liquid crystal panel. In the figure, 2201 is an input video signal, 2202 is a clamp circuit, 2203 is a gamma correction circuit, 2204 is a bipolar video signal generator, 2205 is a gate circuit, 2206 is a polarity inversion control signal, 2207 is a limiter circuit, Reference numeral 2208 denotes a buffer circuit unit. Normally, one video processing circuit is required for each primary color signal, so that a total of three circuits are required.

[0004] The primary color signal is pedestal clamped at a predetermined potential by a clamp circuit 2202. Next, each primary color signal whose pedestal potential is adjusted to a predetermined potential is input to the gamma correction circuit 2203. Then, the gamma-corrected video signal is output to a bipolar video signal generation circuit 2204, where a positive polarity video signal and a negative polarity video signal are created.
Note that the bipolar video signal generation circuit 2204 includes a gain adjustment circuit that simultaneously adjusts the amplitude of each primary color signal, a brightness adjustment circuit that changes the relative voltage of the positive and negative pedestal levels of each primary color signal, and a variation between circuits and liquid crystal. In order to adjust the white balance of the panel, for example, an adjustment circuit for individually adjusting the gains of the R and B signals and the brightness for the G signal of the primary color signal is incorporated. The positive and negative video signals are supplied to the gate circuit 2205, and the gate circuit 2205
In this embodiment, the polarity inversion control signal 2206 alternately takes out a positive or negative video signal for each field or at a cycle that is an integral multiple of the horizontal cycle. An output video signal from the gate circuit 2205 is subjected to limiter control by a limiter circuit 2207, and the output video signal subjected to the limiter control is output with a low impedance via a buffer circuit 2208 so as to sufficiently drive a load circuit.

[0005] By applying a limiter at the final output section based on the average voltage of the AC-inverted video signal, the center voltage of the video signal can be reduced to one of the power supply voltage without depending on the power supply voltage of the video signal processing circuit section. The reduction of the contrast of the liquid crystal panel by applying a limiter to the positive and negative video signals symmetrically around the average voltage of the video signal without being restricted by the / 2 potential and without limiting various gain and brightness adjustment ranges. An ideal limiter operation without any burn-in (afterimage) can be performed.

[0006]

However, in the prior art, when the video signal at a constant period interval (for example, frame period) is close, the average voltage is almost equal, and the portion exceeding the limit value is sliced to correct the voltage. Although the input video signal can be reproduced almost faithfully even if the negative video signal is symmetrical, there is a problem that the input video signal cannot be reproduced when the gradation is extremely different (for example, white data and black data). .

Further, it is necessary to find an average voltage for positive and negative video signals in a pixel unit at a constant period interval (for example, a frame period).

An object of the present invention is to provide a liquid crystal display device,
In particular, to provide a liquid crystal display device for obtaining a good display state with no afterimage (burn-in) by preventing a steady DC voltage from being applied to a liquid crystal panel in an environment where different video data is input for each frame. It is in.

Another object of the present invention is to provide a liquid crystal display device which does not generate an afterimage without using expensive components.

Another object of the present invention is to provide a liquid crystal display device capable of obtaining a good display without generating an afterimage even when paused during reproduction of moving image data supplied from an external device such as a VTR. It is to provide a liquid crystal display device.

[0011]

That is, the present invention detects a state of video information input from a video signal source such as a television broadcast, a video playback, and a personal computer in a liquid crystal display device and detects the status of the video information at an arbitrary interval. Find the comparison result,
When the comparison result is obtained, which is determined that a steady DC voltage is applied to the liquid crystal panel, the steady DC voltage is dispersed, and the alternating current is applied to prevent the afterimage (burn-in) of the liquid crystal panel from occurring. The drive signal control is performed.

As the input video information to be compared, for example,
The number of lines in each frame can be considered as an example. That is, when the pause function is operated while moving image data supplied from a VTR or the like is displayed, it is known that the length of video information repeats length for each frame. When the number of lines is different, the display data of a specific line differs between adjacent frames, and matches every two frames. On the other hand, if the alternating current of the liquid crystal is set to the dot inversion frame AC drive, a steady DC voltage is applied to the liquid crystal panel. Drive control is performed.

That is, in a liquid crystal display device for displaying input video information from a video signal generator on a liquid crystal panel, a comparison circuit for comparing past input video information with current input video information to determine whether there is a difference, A first driving circuit for outputting an alternating signal of a first cycle to prevent application of a DC voltage to the liquid crystal panel; and a second driving circuit for outputting a second alternating signal different from the first driving circuit. And an AC signal of the first cycle and an AC signal of the second cycle output from the first drive circuit and the second drive circuit, respectively, according to the comparison result of the comparison circuit. And a selection circuit for selecting and outputting one of the conversion signals.

[0014]

An embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, 0101 is a personal computer (hereinafter referred to as P
C), an input video signal from a television broadcast (hereinafter, referred to as TV), a video tape recorder (hereinafter, referred to as VTR), 0102 is a liquid crystal display device for displaying the input video signal 0101, 0103 Is a video processing circuit that takes in the input video signal 0101 and performs video format conversion, image quality adjustment such as contrast and brightness, analog-digital conversion, color number conversion, display size conversion, and the like. Digital video signal subjected to processing, 0105 is a liquid crystal module having a digital video signal as input, 0106 is provided in the liquid crystal module 0105,
Driver control circuit for generating display timing, 0107
Is provided in the driver control circuit 0106, and the liquid crystal panel
An AC control circuit section for performing AC conversion, 0108 is an AC drive signal output from the AC control circuit section 0107, 0109 is a liquid crystal driver control signal excluding the AC drive signal 0108, 0
110 is a data driver, 0111 is a gate driver, and 0112 is a liquid crystal panel.

Hereinafter, the overall operation of the first embodiment according to the present invention will be described with reference to FIG.

First, an image processing circuit unit 0103 in a liquid crystal display device 0102 receives an input image signal 0101 from a PC, TV, VTR, or the like. The video processing circuit unit 0103 performs various kinds of processing on the input video signal 0101 that has been fetched. As an example of processing contents, first, an analog input video signal is converted into a digital video signal, an interlaced video signal is converted into a non-interlaced video signal, and a liquid crystal panel is converted.
For example, enlargement processing according to the display size, gradation correction for improving the contrast ratio, and color number conversion processing for multi-gradation display can be considered. The digital image signal 0104 subjected to image processing is input to a driver control circuit 0106 inside the liquid crystal module 0105, and the data driver 01
10 and a timing required for the gate driver 0111, and generates and outputs a control signal. The inside of the driver control circuit unit 0106 is composed of an AC conversion control circuit unit 0107 necessary for AC conversion of the liquid crystal panel 0112 and other control units. Display data and timing signal 0109 are output to data driver 0110, and gate driver 0111 is output.
, A control signal including an AC drive signal 0108 output from the AC control circuit unit 0107 is output. Here, the AC drive signal 0108 detects the state of the digital video signal 0104, and applies a steady DC voltage to the liquid crystal panel 0112.
A drive signal that does not cause an afterimage (burn-in) is output.

FIG. 2 shows a configuration for detecting the state of the digital video signal 0104 and controlling the operation of the AC drive signal 0108. In other words, the AC conversion control circuit unit 0107 constantly detects the number of lines in one input frame, and performs AC driving so that a steady DC voltage is not applied to the liquid crystal panel 0112 according to the comparison result between adjacent frames. Signal 0108 is controlled.

In FIG. 2, reference numeral 0201 denotes a digital video signal 0.
A vertical synchronization signal included in 101, 0202 is also a horizontal synchronization signal, 0203 is a frame line number comparison control unit for detecting the number of lines of a vertical synchronization signal between adjacent frames, and determining the match / mismatch thereof, 0204 is a frame line number Detection control unit
0203 is a frame line number detection control unit, 0205 is a frame line number detection control unit, 0204 is a frame line number detection result output from 0204, 0206 is a frame line number detection result, 0205 is a latch circuit unit that holds 0205, and 0207 is a latch circuit unit.
The number of frame lines one frame before, which is the output of 0206,
Is a comparison circuit unit of the frame line number detection result 0205 and the frame line number 0207 one frame before, and 0209 is a comparison result by the comparison circuit unit 0208.

Reference numeral 0210 denotes an AC drive signal generation unit for generating an AC drive signal 0108; 0211 is a drive circuit A unit provided in the AC drive signal generation unit 0210 for generating a first timing signal of the drive signal 0108; 0212 is an output of the drive circuit A which is the output, 0213 is a drive circuit B section for generating another timing signal, 0214 is an output of the drive circuit B which is the output,
[0215] Reference numeral 2215 denotes a selector circuit unit (selection circuit) for selecting either the output 0212 of the drive circuit A or the output 0214 of the drive circuit B according to the comparison result 0209.

A frame line number detection control unit (line number detection circuit) 0204 uses a horizontal synchronization signal 0202 as a clock,
The number of clocks between adjacent vertical synchronization signals 0201 is counted. The count result 0205 of the horizontal synchronization signal 0202 in one frame period is output to the comparison circuit unit 0208, and is also delayed by one frame and held in the latch circuit 0206. Therefore,
The frame line number comparison circuit unit 0208 compares the frame line number detection result 0205 for the current frame with the output data 0207 of the latch circuit unit 0206 which is the number of frame lines one frame before the current frame. As a result of the comparison, if it is determined that the number of frame lines of the current frame and the frame one frame before are the same, the output AC drive signal 0211 from the drive circuit A 0211 is determined to be inconsistent. The selector circuit unit 0215 selects the output AC drive signal 0214 from the, and outputs it to the liquid crystal panel 0112 as an AC drive signal 0108. In the present embodiment, in the comparison result of the number of frame lines, if they match, there is no steady application of the DC voltage to the liquid crystal panel 0112, and the output 0212 of the drive circuit A 0211 which is a normal AC drive signal is selected. However, in the case of a mismatch, there is a possibility that a steady DC voltage is applied. Therefore, the output 0214 of the drive circuit B 0213 which is an AC drive signal for dispersing the DC voltage is selected.

Next, an embodiment of the AC driving circuit A 0211 and the AC driving circuit B 0213 will be described together with the cause of applying a DC voltage to the liquid crystal panel. FIG. 3 is a schematic diagram of the voltage applied to the liquid crystal panel by the input video signal and the AC drive signal. In FIG. 3, for ease of explanation, the digital video signal 0104 is regarded as focusing on a specific pixel for each frame.

When the digital video signal 0104 for each frame (here, frame 1 to frame 4) is the same (high gradation data (white) in FIG. 3), the positive and negative polarities of this digital video signal 0104 are inverted for each frame. AC drive signal 010
When 8 is superimposed, a voltage is applied to the liquid crystal panel in which the absolute value is equal and the positive and negative polarities are inverted for each frame, so that the voltages cancel each other out and no steady DC voltage is applied. Therefore, good display without an afterimage (burn-in) is performed.

FIG. 4 is a schematic diagram of the voltage applied to the liquid crystal panel by the input video signal and the AC drive signal. In this case, the input digital video signal is different for each frame, and is the same for every two frames (frames 1, 3 → high gradation data (white) / frame 2,
4 → low gradation data (black)). In particular, such digital video signals are such that video data supplied from a VTR or the like repeats length in each frame. More specifically, during a pause operation, the digital video signal 0104 has positive and negative polarities in each frame. When the AC drive signal 0108 is superimposed, the effective value on the positive polarity side is larger at a certain level than the effective value on the negative polarity side, so that a steady DC voltage is applied. ).

FIG. 5 shows an example of a liquid crystal display system in which an afterimage (burn-in) occurs due to the generation of a digital video signal as shown in FIG. In FIG. 5, reference numeral 0501 denotes a VTR which is one of video signal sources, reference numeral 0502 denotes video signal information including a synchronization signal output from the VTR 0501, and reference numeral 0503 denotes a VTR 0501.
A liquid crystal interface control unit that performs multi-scan processing control or the like to display video signal information 0502 on a liquid crystal panel. Numeral 0504 indicates liquid crystal module video signal information output from the liquid crystal interface control unit.

In FIG. 5, the VTR 0501 has slightly different video signal information depending on the model. For example, VT
Once R 0501 is temporarily stopped, the output video signal information 0502 may be blurred in the vertical direction. When this blur occurs at one line interval for each frame, if the contrast ratio of video data between adjacent lines is large (for example, a boundary between white and black in the horizontal direction), attention is paid to a specific pixel at the boundary. , High gradation (white) and low gradation (black) are repeated for each frame. This information is input to the liquid crystal interface control unit 0503. The liquid crystal interface control unit 0503 performs processes such as analog / digital conversion (hereinafter, referred to as A / D conversion) and multi-scan. When a frame memory is not used in this process, one unit is output for each frame from the VTR 0501. The video information having the blur generated at the line interval is output as the liquid crystal module video signal information 0504 in the blurred state, and supplied to the liquid crystal module 0105. That is,
A digital video signal 0104 as shown in FIG. 4 is given to the liquid crystal module 0105.

FIG. 6 is a diagram for explaining the operation of an example of the drive circuit A 0211 in the AC drive signal generator 0210. This driving method is a “dot inversion + frame alternating current (two frame completion) driving method” in which the voltage polarity is inverted between adjacent pixels in both the horizontal and vertical directions, and all of them are inverted between adjacent frames. In this driving method, when video signal information is input by a liquid crystal display system as shown in FIG.
As shown in FIG. 4, a steady DC voltage is applied, causing an afterimage (burn-in) of the liquid crystal panel 0112.

FIG. 7 is a diagram illustrating the operation of an example of the drive circuit B 0213 inside the AC drive signal generation unit 0210. In this method, the polarity is inverted every two lines in the vertical direction,
In the horizontal direction, the polarity of each dot is inverted. Further, in order to shift one line in the vertical direction for each frame, the "two-line dot inversion + two-frame alternating current (four-frame completed) driving method" has the same polarity every four frames.

FIG. 8 shows a state of a voltage applied to the liquid crystal panel 0112 when video signal information is input by the liquid crystal display system as shown in FIG. 5 in the present driving method.

According to this driving method, the polarity of the AC driving signal is inverted every two frames with respect to the input digital video signal 0104. Cancellation does not occur, and no steady DC voltage is applied. Therefore, afterimages (burn-in)
A good display without the error is performed. Here, in the liquid crystal display system as shown in FIG. 5, when there is a blur in the vertical direction and the digital video signal 0104 as shown in FIG. 4 is input, the driving method B shown in FIG. For example, the liquid crystal panel 0112 can realize good display without an afterimage (burn-in). That is, the AC conversion control circuit 0107 shown in FIG. 2 detects coincidence or non-coincidence of the number of frame lines due to the blur of the vertical synchronization signal as shown in the timing chart of FIG. The information is determined to be in the state shown in FIG.
In the “dot inversion + frame alternating current (two frame completion) driving method” shown in FIG. On the other hand, if they do not match, it is determined that the input video information is in the state shown in FIG. 4, and the “two-line dot inversion + two-frame alternating current (four-frame completed) driving method” shown in FIG. , It is possible to always obtain a good display state with no afterimage (burn-in).

Next, a description will be given of the operation of the liquid crystal display system shown in FIG. 5 of the first embodiment when a frame memory is mounted as the configuration of the liquid crystal interface control unit 0503. FIG. 9 shows an example of a liquid crystal display system equipped with a liquid crystal interface control unit using a frame memory.

In FIG. 9, a VTR 0501, video signal information 0502 as its output, and a liquid crystal module 0105 are the same as those in FIG. Reference numeral 0901 denotes a liquid crystal interface control unit that uses a frame memory to perform multi-scan processing control and the like for displaying video signal information 0502 from a VTR 0501 on a liquid crystal panel. Reference numeral 0902 denotes a liquid crystal module video signal output from the liquid crystal interface control unit. The information is shown below.

In FIG. 9, when the video signal information 0502 output from the VTR 0501 is blurred due to a pause state or the like, the liquid crystal interface control unit
The video signal information 0502 in a blurred state is input to 0901. However, the LCD interface control unit 0901 is equipped with a frame memory,
Since 0502 is temporarily stored in the frame memory for one screen, the input and output of the liquid crystal interface control unit 0901 are controlled in a completely asynchronous state. In this case, the output vertical synchronization signal of the liquid crystal module video signal information 0902 is in a stable state without blur as shown in the timing chart of FIG. That is, the frame frequency detection result in the AC control circuit 0107 is always in a stable state, and as the AC drive signal 0108, the “dot inversion + frame AC (two frame complete) drive system” output from the drive circuit A 0211 is used.
Is selected. Therefore, if the video signal given to the liquid crystal panel is the output from the VTR 0501 as it is, a steady DC voltage is applied as shown in FIG.
An afterimage (burn-in) occurs. However, once a video signal for one screen is stored using a frame memory,
In a liquid crystal display system that controls input and output asynchronously, the DC voltage applied to the liquid crystal panel is dispersed and the afterimage (burn-in) occurs.
Does not occur.

FIG. 10 shows the principle of DC voltage distribution in a liquid crystal display system using a frame memory. In FIG. 10, two frames (frame memories A and B) are provided as frame memories, and while a video signal from the VTR 0501 is being written to one of the memories, a video signal is read from the other memory, and a liquid crystal is read. Output to module 0105. Generally, the frame memory gives priority to the reading operation to the liquid crystal module 0105 in order to perform stable display.
Therefore, as shown in FIG. 10, the input video data from the VTR 0501 is switched between the memories A and B to be written in accordance with the readout timing.
Divided into two memories. In addition, the display data for one screen that is divided and stored is shifted in storage position of each frame due to a difference in input / output frame frequency.

FIG. 11 shows a liquid crystal panel by a liquid crystal display system using the frame memory shown in FIGS. 9 and 10.
The state of the voltage applied to 2 is shown. As shown in FIG. 11, since the frame frequency detection result is always in a stable state for the AC drive signal 0108, the “dot inversion + frame AC (two frame completion) drive method” output from the drive circuit A0211 is selected. However, as shown in FIG. 10, the digital video signal 0104 to which the AC drive signal 0108 is applied is different in each frame when focusing on the pixel at the specific position (that is, the adjacent video in which the afterimage (burn-in) occurs). The state is different between frames, and the same data does not occur every two frames), and the image is dispersed without the application of a steady DC voltage, so that afterimages (burn-in) do not occur.

In the above embodiment, the method of avoiding the afterimage (burn-in) when one frame of blur occurs every frame in the pause state of the VTR 0501 has been described. However, the actual blur does not always occur every frame, but may occur every two frames, three frames, and every N frames.

FIG. 12 shows the state of the voltage applied to the liquid crystal panel 0112 when blur occurs every two frames. FIG.
As shown in (2), even when the blur occurs every two frames, the DC voltage is canceled every two frames, and the steady application of the DC voltage does not occur. In the case of this example, FIG.
In this example, the liquid crystal panel application signals of the second frame and the third frame are reversed every four frames, as opposed to the example in which one line blur occurs.

FIG. 13 shows a liquid crystal panel to which the “dot inversion + frame alternating current (two frame complete) driving method” is applied when blur occurs every two frames shown in FIG.
The state of the voltage applied to 2 is shown. In FIG. 13, the voltage applied to the liquid crystal panel is canceled at the completion of two frames, and no steady DC voltage is applied. That is,
In the case where blur occurs every two frames, FIG.
In either of the two-line dot inversion + two-frame AC (complete four-frame) driving method shown in FIG. 13 or the "dot inversion + frame AC (two-frame completion) driving method" as shown in FIG. Also, it is possible to avoid the steady application of the direct-current voltage, and it is possible to realize a good display without an afterimage (burn-in). Normally, it is desirable for the liquid crystal to use the AC drive in which the polarity of each frame is inverted, and the continuous polarity of the same polarity causes flicker and the like.
The "dot inversion + frame AC (two frame completion) drive system" is adopted.

Therefore, in the case of this example, in any of the AC driving methods, afterimages (burn-in) can be avoided, but in consideration of other effects on display performance, “dot inversion + frame AC (2 Driving in the "frame complete) driving method" is desirable. In order to realize this control, FIG.
This can be realized by not only comparing the number of lines between two adjacent frames but also performing a comparison determination on distant frames in the in-frame line number comparison control unit 0203 shown in FIG.

FIG. 14 is a schematic configuration diagram of an AC control circuit for realizing the present control. In FIG. 14, reference numeral 1401 denotes a vertical synchronization signal. 0201: a frame line number comparison control unit for detecting the number of frame lines between arbitrary frames and judging coincidence or non-coincidence; 1402, a frame line number detection control unit 1401; The detection control unit 1403 is a frame line number detection result output from the frame line number detection control unit 1402, 1404 is a frame line number detection period setting value that determines the detection period of the frame line number, 1405 is a frame line number detection period setting value A line number detection cycle control unit that obtains a frame line number detection cycle corresponding to 1404, 1406 is a frame line number capture signal for each frame line number detection cycle, output from the line number detection cycle control unit 1405,
Reference numeral 1407 denotes latch circuit units 1 and 14 which capture and hold the frame line number detection result 1403 at each frame line number detection period.
08 is a detection result of the number of frame lines held by the latch circuit section 1 1407, 1409 is a detection result of the held frame line number 1408 is delayed by the frame line number detection period and held, and the latch circuit sections 2 and 1410 are latch circuit sections. 2 140
Reference numeral 1411 denotes a comparison circuit unit for comparing the two frame line number detection results 1408 and 1410, and reference numeral 1412 denotes a comparison result by the comparison circuit unit 1411. Other functions are the same as those shown in FIG.

First, the frame cycle of the frame line number detection results 1403 and 1408 to be taken into the latch circuit section 1 1407 and the latch circuit section 2 1409 is set according to the line number detection cycle setting value 1404. The line number detection cycle control unit 1405 outputs a detection line number capture signal 1406 every frame period according to the line number detection cycle setting value 1404. Accordingly, the latch circuit section 1 1407 captures the number of frame lines 1403 at a cycle of the line number detection cycle setting value 1404, and the latch circuit section 2 1409 similarly captures the frame line number 1408 at a cycle of the line number detection cycle setting value 1404. . That is, two frame line number detection results 140
Between 8 and 1410, the frame line number detection cycle setting value 1404
The interval is in accordance with The comparison circuit unit 1409 compares the number of frame lines at this cycle interval.

[0042]

[Table 1]

FIG. 14 shows an example of an algorithm by the AC conversion control circuit of FIG. In Table 1, the blurring generation cycle of the input video signal is shown for each frame and every two frames. First, in the case of blurring for each frame, when the frame line number detection cycle setting value is “1”,
In any adjacent frames, the number of frame lines for the input video data does not match (AtoB or B
toA). Therefore, at this point, it can be determined that the blurring of the input video signal occurs for each frame (each frame). Next, in the case of blurring every two frames, first, when the frame line number detection cycle setting value is “1”, when the number of frame lines for the input video data matches between adjacent frames (AtoA or Bto
B) and when they do not match (AtoB or BtoA)
There are both cases. As described above, when the coincidence and the non-coincidence are mixed, it is determined that the blurring period is even longer, and the value of the line number detection period setting value 1404 is added by +1. That is,
The line number detection cycle setting value becomes “2”, and comparison is performed every other frame. In this case, any comparison results in a mismatch (AtoB or BtoA), and at this point, it can be determined that the blur of the input video signal occurs every two frames. Thereby, it is possible to perform the optimal AC driving in accordance with the blurring period of the input video signal. In Table 1, 1 and 2 are set as the blurring occurrence cycle of the video signal.
Although only two frames have been described, according to this method, for any N frames, the cycle is detected by sequentially adding and setting the line number detection cycle set value, and the cycle is detected, and optimal AC drive is performed. It is possible to do.

Further, the blur is not limited to one line, but may be a case where a blur of N lines occurs or a case where a random blur always occurs. The blur of N lines is only the time difference between the number of lines of each of the two frames to be compared, and if attention is paid to the pixel at a specific position, the state is the same as that of the above-described embodiment. It is.

On the other hand, the DC voltage applied to the liquid crystal panel is dispersed even for random blurring, as in the case of the system using the frame memory shown in FIG. No DC voltage is applied, and no afterimage (burn-in) occurs.

FIG. 15 is a block diagram showing a second embodiment of the liquid crystal display system using the liquid crystal drive control method according to the present invention. In the present embodiment, the input video signal is assumed to be the interlaced signal such as the VTR and TV broadcast shown in the first embodiment. Driver control circuit
The liquid crystal module having the same as the liquid crystal module described in the first embodiment. In order to display an interlaced video signal on the liquid crystal panel 0112, non-interlacing processing is required inside the video processing circuit unit 0103.

In FIG. 15, reference numeral 1501 denotes an A / D conversion processing circuit for converting an input analog video signal into a digital video signal, and reference numeral 1502 denotes a PLL circuit for generating a sampling clock in the A / D conversion processing circuit 1501. , 1503 is a sampling clock, 1504 is a digitized interlaced video signal, 1505 is a two-line scanning processing circuit that converts an interlaced video signal into a non-interlaced video signal, and 1506 is a line memory that generates a video signal delayed by one line Reference numeral 1507 denotes write / read data for the line memory 1506, 1508 denotes a non-interlaced video signal output from the two-line scanning processing circuit 1505, and 1509 performs enlargement / reduction processing of the video signal in accordance with the display area of the liquid crystal panel 0112. Multi-scan processing circuit section, 1510 is the frame memory required for multi-scan processing 1511 respectively indicate the write / read data to the frame memory 1510.

First, an input video signal 0101 is in an interlaced format, and a format in which one frame has 525 lines (hereinafter referred to as a 525I format) will be described as an example.

As the input video signal 0101, even fields and odd fields are input alternately. Each field data is separated into even-line data and odd-line data. A / D conversion processing circuit section 1501
Using the sampling clock 1503 from the PLL circuit section 1502, the signal is converted into a digital video signal 1504 and input to the two-line scanning processing circuit 1505. 2-line scanning processing circuit 15
In 05, non-interlaced video signals are written to the line memory 1506 by write / read data 1507.
08 is output to the next-stage multi-scan processing circuit 1509.
Multi-scan processing circuit 1509 with frame memory 1510
A digital video signal 0104 enlarged or reduced by the write / read data 1511 is output. Here, the non-interlaced video signal 1508 output from the two-line scanning processing circuit 1505 will be described in detail.

FIG. 16 shows an interlaced video signal 150.
4 and 2 line scanning processing circuit 1505 and line memory 1
4 shows a timing diagram of a non-interlaced video signal 1508 converted by 506. FIG. 16 shows, as an example, the processing of the input video signal 1504 of the odd field.

The input video signal 1504 for each line is written into the line memory 1506 simultaneously with the input. In the even-numbered line which is a pause period of the input video signal 1504, the video signal written in the previous line is read from the line memory 1506. Since writing and reading may be performed alternately for one line, the installed capacity of the line memory may be one line. The output video signal 1508 can be in a non-interlaced format by alternately outputting the input video signal 1504 and the read data 1507 from the line memory. The same processing can be applied to even fields.

FIG. 17 shows an example of non-interlaced display by the two-line scanning processing circuit shown in FIGS. In FIG. 17, in order to simplify the explanation, one screen is composed of five lines, and lines 1 to 3 are low gradation data (black data) and lines 4 and 5 are high gradation data (white data). Show.

The original video signal (the figure on the left side of FIG. 17) is
When the video signal is input to the video processing circuit 0103 shown in FIG. 15 in an interlaced format (the center diagram in FIG. 17), the two-line scanning processing circuit 1
At 505, the video signal is converted into a non-interlaced video signal (the right diagram in FIG. 17). Focusing on the fourth line of each video signal of the even-numbered frame and the odd-numbered frame after the conversion, high gradation data (white data) and low gradation data (black data) are repeated for each frame. This is the same state as the input video signal shown in FIG.
When the control is performed in the "frame alternating current (two-frame completed) drive", a steady DC voltage is applied, and an afterimage (burn-in) occurs. In the example of FIG. I do.

However, when the AC conversion control circuit 0107 according to the present invention shown in FIG. 15 is mounted, when a video signal 0104 as shown in FIG. 17 is input, the number of lines in one frame is two in an even field, and When three lines are measured in the odd field and the number of lines is determined to be different, the AC drive method is switched to “2-line dot inversion + 2-frame AC (complete 4 frames) drive”. That is, FIG.
And the same state as the voltage applied to the liquid crystal panel by the input video signal and the AC drive signal shown in (1), no steady DC voltage is applied, and good display without image sticking (burn-in) is possible.

In other words, similarly, since the total number of lines is odd for 525I format video signals such as TV and VTR, either one of the even field and the odd field is detected by one more line, and "2 line dot inversion + 2 frames" The drive is switched to "AC (complete 4 frames) drive", and good display without afterimages (burn-in) is possible.

FIG. 18 shows an example of a liquid crystal display system equipped with a three-dimensional IP conversion function used when converting a generally known interlaced TV video signal into a non-interlaced format. In FIG. 18, reference numeral 1801 denotes a three-dimensional IP conversion processing circuit for converting an interlaced video signal into a non-interlaced video signal using video data between lines in even and odd fields and between lines in the same field; 1802 is a microcomputer for controlling various parameters such as the amount of motion detection of the video for the three-dimensional IP conversion processing circuit 1801, and 1803 is a microcomputer for connecting the three-dimensional IP conversion processing circuit 1801 and the microcomputer 1802. Bus, 1804 is input even and odd fields
A field memory 1805 for storing an interlaced video signal indicates an even and odd field interlaced video signal read and written between the three-dimensional IP conversion processing circuit 1801 and the field memory 1804, respectively.

FIG. 19 shows a basic operation diagram of the three-dimensional IP conversion processing circuit. 18 and 19, the control is the same for both odd-numbered frames and even-numbered frames. For example, in the processing of odd-numbered frames, an old odd-field video signal, an even-field video signal, and a new odd-field video are stored in a field memory 1804 for three fields. Each signal is stored. Each is a field that is adjacent in the order of description. In the video signal for the three fields, the odd lines of the display image are compared between the new and old odd fields,
If it is determined that they match, the video signal of the corresponding odd line of the new odd field is output as a video signal to be displayed (line 1 and line 5). If it is determined that they do not match, the video signals of the upper and lower lines in the even-numbered field are calculated and output as the video signals of the corresponding odd-numbered lines (line 2 of the even-numbered field and line 3 of the display video from line 4).
Generate a). As for the even-numbered lines of the display image, the video signal of the corresponding even-numbered line of the even-numbered field is output as the display image. Similar control is performed for even-numbered frames. Here, the determination of the match / mismatch depends on the motion detection amount set by the microcomputer 1802. In the non-interlace display video signal of the odd and even frames, the lines determined to be coincident have the same data. Therefore, even when the AC drive method is “dot inversion + frame AC (two frame complete) drive”, Since the state is as shown in FIG. 3, no afterimage (burn-in) occurs (line 1, line 2, line 5). If it is determined that they do not match, the video signal is different between frames, but in the case of a moving image, the video signal is different for each field, so that the display video is also different for each frame, and the DC voltage shown in FIG. In the case of coincidence, the AC drive method is “dot inversion + frame AC drive (complete two frames)”.
No afterimage (burn-in) occurs (line 3, line 4). However, for a video signal that moves regularly as in the case of the VTR pause in the first embodiment, the odd frame display video and the even frame display video shown in FIG. 19 are alternately provided to the liquid crystal panel. Therefore, depending on the set value of the motion detection amount, the gradation difference between the original video signal and the video signal generated by the calculation between the upper and lower lines becomes large, and the state shown in FIG. 4 occurs, and the afterimage (burn-in) occurs. (Line 3, line 4).

Therefore, when a three-dimensional IP conversion processing circuit is mounted, a normal video signal (regardless of interlaced format, non-interlaced format, still image, and moving image) can be used as shown in FIG. Although the afterimage (burn-in) does not occur in (2 frame completion) drive, the afterimage (burn-in) occurs for a video signal that moves regularly as in the case of the VTR pause in the first embodiment. It is necessary to switch to "2-line dot inversion + 2-frame AC (complete 4 frames) drive" shown in FIG.

[0059]

[Table 2]

FIG. 15 shows the estimated member costs of the two-line scanning processing circuit shown in FIG. 15 and the three-dimensional IP conversion circuit shown in FIG. In the three-dimensional IP conversion circuit system, an interlaced video signal that moves irregularly is converted into a signal shown in FIG.
"Dot inversion + frame exchange (two frames completed)
Although there is an advantage that a good display without an afterimage (burn-in) can be performed by using "drive", the cost of members is about three times that of the two-line scanning circuit system.

FIG. 20 is a block diagram showing a third embodiment of the liquid crystal display system using the liquid crystal drive control method according to the present invention. In the present embodiment, the method of switching between the two driving methods (the driving circuit A 0211 and the driving circuit B 0213) shown in FIG. 2 is further expanded.

In FIG. 20, reference numeral 2001 denotes a control B signal enable control unit for controlling whether the control signal B 2022 composed of VSYNC is enabled or disabled, and 2002 denotes a control output from the control B signal enable control unit 2001. A B enable signal, 2003 is a selector circuit for selecting the control signal A or control signal B output from the frame line number detection control section 0203, and 2004 is a drive circuit A 0211 or drive circuit B output from the selector circuit 2003. Are respectively shown.

The control B signal enable control unit 2001 determines the selection of the control signal B consisting of the input vertical synchronization signal (VSYNC) 0201 according to the state of the input vertical synchronization signal (VSYNC) 0201 and the input horizontal synchronization signal (HSYNC) 0202. The state of the control B enable signal 2002 is determined. That is, the input vertical synchronization signal (VSYNC) normally
If the input horizontal synchronizing signal (HSYNC) 0202 is input, the control signal A 0209 is selected; otherwise, the control signal B 0201 is selected.

FIG. 21 shows an operation timing chart of the control B enable signal 2002. In FIG. 21, the input horizontal synchronizing signal (HSYNC) 0202 is counted by a counter starting from the pulse of the input vertical synchronizing signal (VSYNC) 0201, and the counter value when the input vertical synchronizing signal (VSYNC) 0201 falls is checked. If the counter value is within the specified range, it is determined that a normal synchronization signal has been input, the control signal A 0209 is selected, and the AC drive switching control by the frame line number detection control described in the first embodiment is performed. I do. If it is out of the specified range, no normal synchronization signal is input, and the control signal B0201 composed of the input vertical synchronization signal (VSYNC) 0201 functions as a selection signal for either the driving circuit A0211 or the driving circuit B0213. .

[0065]

[Table 3]

An example of the specified range is shown in FIG. In Table 3, the resolution is shown for XGA or SXGA, and the number of lines is about 800 lines and about 1100 lines, respectively. Therefore, as an enable condition of the control signal B0201, it is assumed that the value is out of a range that sufficiently satisfies these conditions.
It is made effective when it deviates from 00 line to 2000 line.

Therefore, in the pattern 1 in FIG.
Input vertical synchronizing signal (VSYNC) Count value n at the time of falling of 0201 falls within this specified range, it is determined that a normal synchronizing signal is input, and control signal A 0209 is selected to select the first embodiment. The AC drive switching control is performed by the frame line comparison control shown in FIG. Pattern 2 is a case where the input vertical synchronization signal (VSYNC) 0201 is always at the “L” level. In this case, the counter is always cleared. Further, since there is no falling edge of the input vertical synchronization signal (VSYNC) 0201 for checking the counter value, the check result is always the initial value of zero (here, the initial value of the check value of the counter is defined as zero). . Therefore, the condition is out of the condition range of Table 3, and the control B enable signal 2002 selects the control signal B consisting of the input vertical synchronization signal (VSYNC) 0201. Since this signal is at the “L” level, the driving circuit A 0211 is selected.

Similarly, in the pattern 3, the counter is not cleared and enters a free-run state. Further, since there is no falling edge of the input vertical synchronization signal (VSYNC) 0201 for checking the counter value, the check result is always the initial value of zero. . Accordingly, the control B enable signal 2002 is out of the condition range of Table 3, and the control V enable signal 2002 is the input vertical synchronization signal (VSYNC).
Is selected. Since this signal is at the “H” level, the driving circuit B 0213 is selected.

As described above, according to the present embodiment, the functions of the input vertical synchronizing signal (VSYNC) 0201 and the input horizontal synchronizing signal (HSYNC) 0202 are shared, and
It is possible to have different types of AC switching control.

As an example of a liquid crystal display system to which this embodiment is applied, a video processing circuit 0103 and a liquid crystal module of the liquid crystal display system 0102 shown in FIGS. 1, 15 and 18 are shown.
As the interface specification of the digital video signal between 0105, versatile LVDS can be adopted. In this case, the input vertical synchronization signal (VSYNC) 02
When 01 and the input horizontal synchronization signal (HSYNC) 0202 operate as a normal synchronization signal, the AC drive is automatic control on the liquid crystal module side by frame line number comparison control.

The driver control circuit 0106 in the liquid crystal module 0105 is connected to the input vertical synchronization signal (VSYNC) 02
01 and the input horizontal synchronizing signal (HSYNC) 0202 can be controlled only by the display valid period signal without using the input vertical synchronizing signal (VSYNC) 0201 and the input horizontal synchronizing signal (HSYNC) 0202. A signal can be used, and the AC drive can be arbitrarily controlled from the display system side.

As described above, according to the present invention, afterimages (burn-in) can be obtained for video signals of any form without processing input video data and without installing expensive functions such as three-dimensional IP conversion. ), It is possible to realize a good display. Further, an AC drive switching control means for realizing a good display without an afterimage (burn-in) is provided.
The liquid crystal module side can be controlled by itself or the control of the whole system can be added.In that case, the interface between the video processing circuit unit and the liquid crystal module can be made versatile. .

[0073]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, the format of the input video signal is an interlace format, a non-interlaced format,
Regardless of the still image, it is possible to obtain a good display state with no afterimage (burn-in) without losing reproducibility by processing the video signal itself for any form of input video signal. can get.

Further, when converting an interlaced video signal into a non-interlaced video signal, a circuit requiring expensive components such as a three-dimensional IP conversion function is not required, and even and odd fields are not required. For a simple circuit in which the line is read twice within, a good display state with no afterimage (burn-in) can be obtained, and the effect that the cost can be greatly reduced can be obtained.

Further, as the switching means of the AC drive system according to the present invention, in addition to the control of the liquid crystal module alone, the combined use of the control by the system on the video processing apparatus side is used.
Since it can be realized only with a versatile interface such as DS, an effect is obtained that it can be applied to a wide range of products in accordance with the required specifications of each product.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a liquid crystal display system using the technology of the present invention.

FIG. 2 is a configuration diagram of an AC conversion control circuit unit in the configuration diagram shown in the first embodiment according to the present invention;

FIG. 3 is a schematic diagram of a voltage applied to a liquid crystal panel in “dot inversion + frame alternating current (complete two frames)” when video signals are the same for the first embodiment according to the present invention.

FIG. 4 is a schematic diagram of a voltage applied to a liquid crystal panel in “dot inversion + frame alternating current (complete two frames)” when a video signal differs for each frame for the first embodiment according to the present invention.

FIG. 5 is a schematic configuration diagram showing an example of a system configuration using a VTR for the first embodiment according to the present invention.

FIG. 6 is an explanatory diagram of the operation of “dot inversion + frame exchange (two frames completed)” for the first embodiment according to the present invention.

FIG. 7 is an explanatory diagram of an operation of “two-line dot inversion + two-frame alternating current (complete four frames)” for the first embodiment according to the present invention.

FIG. 8 shows a case where the video signal for the first embodiment according to the present invention is different for each frame, "2 line dot inversion + 2".
FIG. 8 is a schematic diagram of a liquid crystal panel applied voltage in a frame alternating current (4 frames completed).

FIG. 9 is a schematic configuration diagram of an example of a system configuration using a VTR according to the first embodiment of the present invention when input and output are asynchronous using a frame memory for an interface control unit.

FIG. 10 is a diagram illustrating a DC voltage dispersion operation principle in a liquid crystal display system using a frame memory according to the first embodiment of the present invention.

FIG. 11 is a schematic diagram of a liquid crystal panel applied voltage in “dot inversion + frame alternating current (complete two frames)” when video signals are randomly different for the first embodiment according to the present invention.

FIG. 12 is a diagram showing a case where a video signal is blurred every two frames with respect to the first embodiment according to the present invention.
It is a schematic diagram of the liquid crystal panel applied voltage in "two frame alternating current (four frame completion)".

FIG. 13 is a schematic diagram of the voltage applied to the liquid crystal panel in “dot inversion + frame alternating current (two frame completion)” when the video signal is blurred every two frames for the first embodiment according to the present invention.

FIG. 14 is a configuration diagram of an AC conversion control circuit unit in consideration of a blur period of a video signal in the configuration diagram according to the first embodiment of the present invention.

FIG. 15 is a configuration diagram showing a second embodiment of a liquid crystal display system using the technology of the present invention.

FIG. 16 is a timing diagram of a line memory controlled by a two-line scanning processing circuit according to a second embodiment of the present invention.

FIG. 17 shows an example of non-interlaced display by a two-line scanning processing circuit according to the second embodiment of the present invention.

FIG. 18 is a configuration example of a liquid crystal display system equipped with a general three-dimensional IP conversion function for the second embodiment according to the present invention.

FIG. 19 is a basic operation diagram of a general three-dimensional IP conversion function for the second embodiment according to the present invention.

FIG. 20 is a configuration diagram showing a third embodiment of the liquid crystal display system using the technology of the present invention.

FIG. 21 is an operation timing chart of a control B enable signal for the third embodiment according to the present invention.

And FIG. 22 is a configuration example of a video signal processing circuit capable of preventing an afterimage (burn-in) according to a conventional technique.

[Explanation of symbols]

0101: input video signal 0102: liquid crystal display device 0103: video processing circuit 0104: digital video signal 0105: liquid crystal module 0106: driver control circuit 0107: AC control circuit unit 0108: AC drive signal 0109: liquid crystal driver control signal 0110 Data driver 0111: Gate driver 0112: LCD panel 0201: Vertical synchronization signal 02
02: Horizontal synchronization signal 0203: Frame line number comparison control unit
0204: Frame line number detection control unit 0205: Frame line number detection result 0206: Latch circuit unit 0207: Number of frame lines one frame before 0208: Comparison circuit unit 0209: Comparison result 0210: AC drive signal generation unit 0211: Drive circuit A
Unit 0212: Drive circuit A output 0213 ... Drive circuit B unit 0214 ... Drive circuit B output 0215 ... Selector circuit unit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 102 H04N 5/66 102B (72) Inventor Tsutomu Furuhashi 1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory (72) Inventor Waka Kawabe 1099 Ozenji Temple, Aso-ku, Kawasaki, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara-shi, Chiba Co., Ltd. F term in Hitachi Display Group (reference) 2H093 NA16 NA32 NA33 NA34 NA43 NA45 NA53 NC21 NC29 NC34 NC49 NC52 NC65 ND12 ND35 5C006 AA01 AA11 AC26 AC29 AC30 AF42 AF44 AF46 AF51 AF53 AF61 BB11 BF02 BF04 BF24 BF15 BF14 BF15 BF14 BF14 BA04 BB04 BB09 BB13 BB15 BB16 5C080 AA10 BB05 DD18 DD29 EE29 JJ 02 JJ04 JJ05

Claims (9)

[Claims] 1. A liquid crystal display device for displaying input video information from a video signal generator on a liquid crystal panel, comprising: a comparison circuit for comparing past input video information with current input video information to determine whether there is a difference; A first driving circuit that outputs an alternating signal of a first cycle to prevent application of a DC voltage to the liquid crystal panel; and a second driving circuit that outputs a second alternating signal different from the first driving circuit. And an AC signal of the first cycle and an AC signal of the second cycle that are respectively output from the first drive circuit and the second drive circuit according to the comparison result of the comparison circuit. A liquid crystal drive control device comprising a selection circuit for selecting and outputting any one of an activation signal and an activation signal. 2. A liquid crystal display device according to claim 1, wherein said liquid crystal display device further detects a vertical line number of each frame when displayed on said liquid crystal panel from said input video information. A comparison circuit for comparing the number of lines detected by the line number detection circuit between frames at arbitrary intervals, and the selection circuit includes a frame to be compared by the comparison of the comparison circuit. A liquid crystal drive control device wherein the output of the first drive circuit is selected when the number of lines matches between them, and the output of the second drive circuit is selected when the numbers do not match. 3. The liquid crystal display device according to claim 2, wherein the comparison circuit has a holding circuit for holding the number of lines one frame before detected by the line number detection circuit. A liquid crystal display device comprising: comparing the number of lines held in a holding circuit with a current number of lines of the input video information signal detected by the line number detection circuit. 4. The liquid crystal display device according to claim 1, wherein the first drive circuit sets the polarity of the voltage of each pixel of the liquid crystal panel to a positive polarity for each frame and a negative polarity as the alternating signal of the first cycle. A liquid crystal display device that outputs a signal for inverting the voltage polarity between adjacent pixels in both the horizontal and vertical directions. 5. The liquid crystal display device according to claim 1, wherein the second drive circuit inverts the voltage polarity of each pixel of the liquid crystal panel at a cycle of two frames as the alternating signal of the second cycle. Repeat the operation completed in 4 frames,
The liquid crystal display device further outputs a signal in which the voltage polarity is inverted between adjacent pixels in the horizontal direction and the voltage polarity is inverted every two pixels in the vertical direction. 6. The liquid crystal display device according to claim 2, wherein the comparison circuit includes an input terminal for inputting a signal indicating a frame interval of the input video information to be compared, and a signal input from the input terminal. A first holding circuit and a second holding circuit for holding the number of lines detected by the line number detecting circuit in each frame constituting the frame interval according to the designated frame interval; A liquid crystal display device comprising: comparing the number of lines held in the first holding circuit with the number of lines held in the second holding circuit. 7. A liquid crystal display device according to claim 1, wherein the input video information from said video signal generation device is in a non-interlace format. 8. The liquid crystal display device according to claim 1, wherein the input video information from said video signal generating device is in an interlace format. 9. A liquid crystal display device for displaying input video information from a video signal generator on a liquid crystal panel, wherein the number of vertical lines of each frame when displayed on the liquid crystal panel is detected from the input video information. A line number detection circuit, and a holding circuit for holding the number of lines one frame before detected by the line number detection circuit, wherein the number of lines held in the holding circuit and the number of lines detected by the line number detection circuit are A comparison circuit for comparing the current number of lines of the input video information video signal with the current number of lines; and in order to prevent the application of a DC voltage to the liquid crystal panel, the voltage polarity of each pixel of the liquid crystal panel repeats positive polarity and negative polarity for each frame. A first driving circuit for outputting an AC signal of a first cycle for inverting the voltage polarity between adjacent pixels in both the horizontal and vertical directions; The polarity of the voltage of each pixel of the pixel is inverted every two frames, and the operation completed in four frames is repeated.
A voltage polarity is inverted between adjacent pixels in the horizontal direction, and a voltage polarity is inverted every two pixels in the vertical direction.
And a second drive circuit that outputs an alternating signal having a period of, when the number of lines matches between the frames compared by the comparison of the comparison circuit, the output of the first drive circuit is
A liquid crystal drive control device comprising a selection circuit for selecting an output of the second drive circuit when the two do not match.