JP2002084180A - High-speed arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed arithmetic circuit, capable of accelerating a circuit operation when various types of calculations are carried out, as compared to prior art. SOLUTION: The high-speed arithmetic circuit comprises two MOS-transistor logic circuits 101 and 102 for obtaining two equal logic results. The logic circuit 101 inputs a first signal group of two inputs to its gate terminal and inputs a second signal group to a source terminal. The logic circuit 102 inputs a first signal group to its gate terminal and inputs a second signal group to its source terminal. The outputs of the logic circuits 101 and 102 are constituted so as to carry out wired OR operation by a wired-OR circuit 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed LSI, and more particularly to a high-speed operation circuit such as a logic circuit composed of a MOS transistor circuit operating at a low voltage.

[0002]

2. Description of the Related Art Conventionally, a high-speed LSI has been realized, and in particular, a high-speed OR circuit composed of MOS transistor circuits operating at a low voltage, a high-speed AND circuit, a high-speed exclusive OR circuit, a high-speed exclusive AND circuit, and a high-speed High-speed arithmetic circuits having a high-speed arithmetic function for performing various numerical and logical operations at high speed, such as a sum circuit, a high-speed product circuit, a high-speed exclusive-sum circuit, and a high-speed exclusive product circuit, are widely used. .

A pass transistor logic in a high-speed operation circuit having such a high-speed operation function is described below.
"Low power consumption, high speed L"
SI technology ", pp. 126-127.

As an example of the above high-speed operation circuit, a DPL (Double Pascal) shown in FIG.
s Transistor Logic) will be described below as an example.

FIG. 12 shows an example of the configuration of a circuit that receives two signals, an input signal (A) and an input signal (B), and outputs a logical inversion of the logical product (A · B). In FIG. 12, reference numerals 1201 and 1203 denote PchMOS transistors,
Reference numerals 1202 and 1204 denote NchMOS transistors.

The PchMOS transistor 1201 has a source connected to the power supply VDD and a gate connected to the input signal (B). NchMOS transistor 1
In the source 202, an input signal (a logically inverted value of NA: A) is connected to the source, and an input signal (B) is connected to the gate.

The PchMOS transistor 1203 has a source connected to the power supply VDD and a gate connected to the input signal (A). NchMOS transistor 1
Reference numeral 204 denotes a source to which an input signal (NB: logically inverted value of B) is connected, and a gate to which an input signal (A) is connected.

[0008] MOS transistors 1201 to 1204
Are connected in common, and the input signal (A)
And the input signal (B). Next, logical product (A · B) using the DPL circuit shown in FIG.
The operation of the logical inversion circuit of FIG. At this time, it is assumed that the input signal (A) and the input signal (B) do not arrive at the same time. Here, the input signal (A) is at level (1) (at this time, the input signal (NA) is at level (0))
Now, a case where the input signal (B) transitions from level (0) to (1) (this is hereinafter referred to as (R)) will be described. At this time, the input signal (NB) transitions from level (1) to (0) (this is hereinafter referred to as (F)). In this case, the transistors that change the output according to the change in the input signal (B) are the NchMOS transistor 1202 and the NchMO transistor.
It becomes an S transistor 1204.

First, an NchMOS transistor 1202
For the input signal (B) to the gate, the level (0)
From (1) to the input signal (N
A) is at level (0), and the gate potential is at level (0) in the initial stage of the change. Therefore, no channel is formed below the gate oxide film, and the device is in a non-conductive state.

After that, the NchMOS transistor 120
In 2, when the gate potential reaches the threshold potential, a channel is formed under the gate oxide film, and current starts to flow between the source and the drain. In other words, NchMO
The output level (0) of the S transistor 1202 appears at the drain terminal when the gate potential becomes the threshold potential.

On the other hand, NchMOS transistor 1204
As for the input signal (A) is input to the gate at this time, the potential of the input signal (A) is at level (1),
The source receives an input signal (NB) and its potential changes from level (1) to (0). Since the gate terminal is at level (1) and the source terminal is at level (1), the drain terminal is at level (1). , A value reduced by the threshold potential due to the base bias effect.

When the time further elapses and the source potential of the NchMOS transistor 1204 drops by the threshold potential from the power supply, the drain potential of the NchMOS transistor 1204 becomes the input signal (N
It follows the potential change of B), and the potential starts to decrease. That is, in the NchMOS transistor 1204, the potential of the output signal starts to change after the input signal (B) changes by the threshold potential.

Further, since the same problem occurs in another conventional example, another circuit will be described. Here, an inversion circuit of a conventional exclusive OR circuit using a pass transistor will be described as an example.

FIG. 13 is a block diagram of an inverting circuit of an exclusive OR circuit which is another example of the configuration of the conventional high-speed operation circuit. In FIG. 13, reference numerals 1301 and 1303 denote NchMOs.
S transistors 1302 and 1304 are PchMOS transistors.

Nch and PchMOS transistor 1
Each of 301 and 1302 has a common source terminal and a common drain terminal. An input signal (B) is input to the source terminal, and the drain terminal is connected to the output. Also, N
An input signal (A) is input to a gate terminal of the chMOS transistor 1301, and an input signal (NA) is input to a gate terminal of the PchMOS transistor 1302.

On the other hand, the Nch and Pch MOS transistors 1303 and 1304 have a common source terminal and a common drain terminal, and have an input signal (N
B) is input, and the drain terminal is connected to the output. An input signal (NA) is input to a gate terminal of the NchMOS transistor 1303, and an input signal (A) is input to a gate terminal of the PchMOS transistor 1304.

Here, when the input signal (A) is in the state (R),
The case where the input signal (B) is at level (1) will be described.
At this time, the Nch and PchMOS transistors 13
For 01 and 1302, the source and drain terminals are turned on and the source potential is transmitted to the drain.

As an operation example, an NchMOS transistor 1301 will be described. NchMOS transistor 1
In 301, the input signal (A) is input to the gate terminal, and the potential of the gate terminal changes from level (0) to (1). At this time, when the potential difference between the gate and the source becomes equal to or higher than the threshold voltage Vtn of the NchMOS transistor 1301, a channel is formed under the gate oxide film, the source and the drain are brought into conduction, and the drain terminal is connected to the source terminal from the source terminal. The current starts to flow,
The potential of the drain terminal starts to rise.

Similarly, the PchMOS transistor 130
In the case of 2, the current starts to flow between the source and the drain when the potential between the gate and the source reaches the threshold potential.

[0020]

However, in the above-described conventional high-speed operation circuit such as a high-speed logic circuit,
In the case where a change in an input signal is transmitted to an output by operating the arithmetic function, when the operation of the arithmetic function starts, a channel is first formed under a gate oxide film of a transistor constituting the circuit, and then, a Since the circuit becomes conductive and the change of the input signal is transmitted to the output, there is a delay time from the input change to the output change, and this delay time is calculated. This is a major problem in increasing the operation speed.

In the high-speed LSI constituted by the above-mentioned high-speed arithmetic circuit, the delay time is further reduced in the future, and the ratio (ratio) of Vt to the power supply voltage is further increased. , Which is an even bigger problem in increasing the speed of the arithmetic operation.

The present invention solves the above-mentioned conventional problems, and can reduce the time from the start of operation of an arbitrary arithmetic function to the formation of a channel under a gate oxide film of a transistor. Provided is a high-speed arithmetic circuit that can increase the speed of a circuit operation at the time of arithmetic operation as compared with the related art.

[0023]

In order to solve the above-mentioned problems, a high-speed arithmetic circuit according to the present invention comprises a Pch and an Nch M
A pair of two signals having a logically complementary relationship with each other is defined as an output signal, and two signals having a logically complementary relationship with each other are set as a first and a second input signal. CMOS logic circuit
A third MOS transistor group including a plurality of MOS transistors, wherein the first input signal is supplied to each source of the MOS transistors, and the second input signal is supplied to each gate; A second input signal is supplied to each source of the MOS transistors, a first input signal is supplied to each gate, and an output logic is the same as that of the third MOS transistor group. And a means for logically wired-ORing each output signal of the third MOS transistor group and the fourth MOS transistor group.

As described above, of the two input signals, the signal arriving late is the PchMOS transistor and the Nch
When the signal is input to each source terminal of the MOS transistor, the signal that has arrived late is input to the source terminal because the source and the drain are in a conductive state by another signal that has arrived earlier at that time. Thereafter, transmission and output to the drain terminal can be performed with almost no delay.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-speed arithmetic circuit according to a first aspect of the present invention is composed of P-channel and N-channel MOS transistors. A CMOS logic circuit that outputs a pair of two signals that are logically complementary to each other as an output signal as first and second input signals, and includes a plurality of MOS transistors. One input signal is supplied, and a third MOS transistor group to which the second input signal is supplied to each gate, and a plurality of MOS transistors.
A fourth MOS transistor group, the second input signal being supplied to each source of the OS transistor, the first input signal being supplied to each gate, and an output logic being the same as the third MOS transistor group; , A high-speed logic circuit comprising means for logically wired-ORing each output signal of the third MOS transistor group and the fourth MOS transistor group.

According to a second aspect of the present invention, there is provided a high-speed operation circuit, comprising: a third MOS transistor group and a fourth MOS transistor group; PchM to be input
The OS transistor and the NchMOS transistor are paired and each source and each drain are short-circuited.

[0027] The high-speed operation circuit according to claim 3 is a Pch
And two N-channel MOS transistors, and two sets of signals (A) and (NA) or (B) and (NB), which are logically complementary to each other, are set as a first set.
And a two-input AND circuit having a first MOS logic circuit and a second MOS logic circuit as second input signals, wherein the first MOS logic circuit is supplied with power at a source and has a gate connected to a gate. An input signal (B) is supplied and a drain is connected to a third node, a PchMOS transistor, and a source and a drain are commonly connected to each other to form a pair of a PchMOS transistor and an NchMOS.
And a pair of the PchMOS transistor and the NchMOS transistor,
An input signal (NA) is supplied to each source, each drain is connected to the third node, and an input signal (NB) is supplied to a gate on the side of the PchMOS transistor.
The input signal (B) is supplied to the gate on the OS transistor side, and the second MOS logic circuit is configured such that the power is supplied to the source, the input signal (A) is supplied to the gate, and the drain is connected to the drain. PchMOS connected to node 4
A P-channel MOS transistor and an N-channel MOS transistor, each of which has a source and a drain connected to each other in common.
In the chMOS transistor and the NchMOS transistor, an input signal (NB) is supplied to each source,
Each drain is connected to the fourth node, and the PchMO
The input signal (NA) is supplied to the gate on the S transistor side, and the input signal (A) is supplied to the gate on the NchMOS transistor side, and the third node and the fourth node are short-circuited. A two-input AND circuit for obtaining a logical output from this short-circuit point is constructed.

The high-speed operation circuit according to claim 4 is a Pch
And two N-channel MOS transistors, and two sets of signals (A) and (NA) or (B) and (NB), which are logically complementary to each other, are set as a first set.
And a two-input OR circuit having a first MOS logic circuit and a second MOS logic circuit as second input signals, wherein the first MOS logic circuit has a source connected to ground, and a gate connected to the gate. An NchMOS transistor supplied with an input signal (B) and having a drain connected to a third node, and a pair of PchMOS transistor and NchMOS having a source and a drain commonly connected, respectively.
And a pair of the PchMOS transistor and the NchMOS transistor,
An input signal (NA) is supplied to each source, each drain is connected to the third node, and an input signal (B) is supplied to a gate on the side of the PchMOS transistor.
An input signal (NB) is supplied to the gate on the S transistor side, and the second MOS logic circuit has a source connected to the ground, an input signal (A) supplied to the gate, and a drain connected to the second MOS logic circuit. NchMOS connected to node 4
A P-channel MOS transistor and an N-channel MOS transistor, each of which has a source and a drain connected to each other in common.
In the chMOS transistor and the NchMOS transistor, an input signal (NB) is supplied to each source,
Each drain is connected to the fourth node, and the PchMO
The input signal (A) is supplied to the gate on the S transistor side and the input signal (NA) is supplied to the gate on the NchMOS transistor side, and the third node and the fourth node are short-circuited. A two-input OR circuit for obtaining a logical output from the short-circuit point is formed.

The high-speed operation circuit according to claim 5 is a Pch
And two N-channel MOS transistors, and two sets of signals (A) and (NA) or (B) and (NB), which are logically complementary to each other, are set as a first set.
And a two-input exclusive-OR circuit having a first MOS logic circuit and a second MOS logic circuit as a second input signal, wherein the first MOS logic circuit has a source and a drain connected in common. A pair of PchMO
Two sets of S transistors and NchMOS transistors are provided. In the one pair of PchMOS transistors and NchMOS transistors, an input signal (B) is supplied to each source, each drain is connected to a third node, and the PchMOS transistor side The input signal (NA) is supplied to the gate, the input signal (A) is supplied to the gate on the NchMOS transistor side, and the other pair of PchMOS transistor and NchMOS
In the transistor, an input signal (NB) is supplied to each source, each drain is connected to the third node,
An input signal (A) is applied to the gate on the PchMOS transistor side.
And the input signal (NA) is supplied to the gate on the NchMOS transistor side, and the second MOS logic circuit comprises a pair of a PchMOS transistor and an NchMOS transistor each having a source and a drain commonly connected. , And one pair of the PchMOS transistor and the NchMOS
In the transistor, the input signal (A) is supplied to each source, each drain is connected to the fourth node, and Pch
The input signal (NB) is supplied to the gate on the MOS transistor side, and the input signal (B) is supplied to the gate on the NchMOS transistor side.
In the S transistor and the NchMOS transistor, an input signal (NA) is supplied to each source, each drain is connected to the fourth node, and an input signal (B) is supplied to a gate on the PchMOS transistor side.
A two-input exclusive OR circuit configured to supply an input signal (NB) to the gate on the MOS transistor side, short-circuiting the third node and the fourth node, and obtaining a logical output from the short-circuit point Is configured.

According to the above configuration, when a signal arriving late among the two input signals is input to each source terminal of the PchMOS transistor and the NchMOS transistor, the source signal is supplied by another signal arriving earlier at that time. Since the connection between the and the drain is in a conductive state, a signal that arrives late is transmitted to the drain terminal with almost no delay after being input to the source terminal.

Hereinafter, a high-speed arithmetic circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a logic circuit which is a configuration example of a high-speed operation circuit according to Embodiment 1 of the present invention. In FIG. 1, reference numerals 101 and 102 denote MOS transistor logic circuits which operate on input signals and output the same operation result, respectively, and 103 denotes MOS transistor logic circuits 101 and 10 respectively.
2 is a wired-OR circuit for logically wired-ORing each drain output of the second circuit.

In the MOS transistor logic circuit 101,
There are three types of connection ports. The connection port 1011 has input data (X) or a logically inverted value (NX) of the input data (X).
At least one of them is input. Connection port 101
2, at least one of input data (Y) or a logically inverted value (NY) of the input data (Y) is input. In addition, a calculation result based on the data input from the connection ports 1011 and 1012 is output to the connection port 1013.

In the MOS transistor logic circuit 102, input data (Y) or (N
Y), input data (X) or (N
X) is input, and the connection port 1023 is
An operation result based on the data input from 1,1022 is output.

The MOS transistor logic circuit 10
1 and 102 are the same, and the connection port 101
The results output from 3, 1023 are also the same. In the wired OR circuit 103, the operation results output from the connection ports 1013 and 1023 are short-circuited by wiring, and output data Z is output.

FIG. 2 is a circuit block diagram showing a specific configuration example of the MOS transistor logic circuit 101 of FIG. Here, the connection ports 1011, 1012, and 1013 have the same reference numerals as the connection ports shown in FIG. 1. In FIG. 2, 201 is
PchMO with common source and drain
This is a MOS circuit composed of a pair of an S transistor and an NchMOS transistor. Each source is connected to the connection port 1011, each gate is connected to the connection port 1012, and each drain is connected to the connection port 1013. This MOS
The circuit 201 has at least one set inside the MOS transistor logic circuit 101.

On the other hand, 202 is an NchMOS transistor or a PchMOS transistor. The source is grounded if it is an NchMOS transistor.
If it is an OS transistor, it is connected to a power supply. The gate is connected to the connection port 1012, and the drain is connected to the connection port 1013. At least 0 or more NchMOS transistors or PchMOS transistors 202 exist inside the MOS transistor logic circuit 101.

As described above, in the MOS transistor logic circuit 101, the input data (X) and (NX) input from the connection port 1011 are input to the source terminal of the MOS circuit 201 by the input data input from the connection port 1012. (Y) and (NY) are input to the gate terminal of the MOS circuit 201.

On the other hand, the MOS transistor logic circuit 102
Has the same configuration as 101, and the input data (Y) and (NY) input from the connection port 1021
Are input to the source terminal of the MOS circuit, and input data (X) and (NX) input from the connection port 1022 are input to the gate terminal of the MOS circuit.

With this configuration, of the two input data (X) and (Y), the signal arriving late is input to the source terminal, and the signal arriving early is input to the gate terminal. Therefore, when the gate is opened, since the source-drain of the MOS circuit is set to the conductive state by the signal arriving first, the signal input to the source terminal arriving late arrives without any delay with almost no delay. Is transmitted to For this reason, it is possible to transmit a change in input to the drain at high speed. (Embodiment 2) The function of a high-speed arithmetic circuit composed of an AND circuit configured as described above is described as a second embodiment.
This will be described below.

FIG. 3 shows the input signal (A) and the input signal (B).
Is input to determine the logical inversion value (= Z) of the logical product (A · B). The equation generated using this Carnot map is shown below.

Equation (1) shows a logical expression generated using the input signal (A) as a selection signal.

[0042]

(Equation 1) Here, (•) represents a logical product and (+) represents a logical sum. (NA) is a logically inverted value of (A), and (A),
(NA) is input as a selector selection signal.

Equation (2) shows a logical expression generated using the input signal (B) as a selection signal.

[0044]

(Equation 2) Here, (NB) is a logically inverted value of (B),
(B) and (NB) are input as selector selection signals.

FIG. 4 is a block diagram showing a circuit configuration obtained by expanding the above equations (1) and (2) into logic. In FIG. 4, reference numeral 410 denotes a logic circuit corresponding to a logical expression generated by using the input signal (B) shown in Expression (2) as a selection signal. Reference numeral 411 denotes a logic circuit corresponding to a logical expression generated by using the input signal (A) shown in Expression (1) as a selection signal. Since the outputs of the logic circuits 410 and 411 have the same logic, the outputs are connected (wired OR). This has the same configuration as the circuits shown in FIGS.

Next, the operation of the logic circuit shown in FIG. 4 will be described below. FIG. 4 is a circuit block diagram showing a circuit configuration that receives an input signal (A) and an input signal (B) and outputs a logically inverted value of a logical product (A · B). In FIG. 4, reference numerals 401, 403, 404, and 406 denote PchMOs.
It is an S transistor. 402 and 405 are NchMOS
It is a transistor.

The power supply VDD is connected to the source of the PchMOS transistor 401, and the input signal (B) is connected to the gate.
Is connected. The input signal (NA) (= logically inverted value of A) is connected to the source of the NchMOS transistor 402, and the input signal (B) is connected to the gate.
The input signal (NA) (= logically inverted value of A) is connected to the source of the PchMOS transistor 403, and the input signal (NB) is connected to the gate. The MOS transistors 402 and 403 have a transistor configuration in which a source and a drain are commonly used.

The source of the PchMOS transistor 404 is connected to the power supply VDD, and the gate is connected to the input signal (A). NchMOS transistor 4
The input signal (NB) (= the logically inverted value of B) is connected to the source 05, and the input signal (A) is connected to the gate. The input signal (NB) (= logically inverted value of B) is connected to the source of the PchMOS transistor 406, and the input signal (NA) is connected to the gate. The MOS transistors 405 and 406 have a transistor configuration in which a source and a drain are commonly used.

The drains of all the MOS transistors are connected in common, and constitute a circuit for outputting the inverted value of the logical product of the input signal (A) and the input signal (B).

The circuit configuration described above is obtained by adding two PchMOS transistors to the conventional AND circuit shown in FIG. 12, and as shown in FIG.
This is a portion in which a PchMOS transistor 403 having a common source and drain is added to the NchMOS transistor 402, and a portion in which a PchMOS transistor 406 having a common source and drain is added to the NchMOS transistor 405.

Next, the operation of the logic circuit for outputting the inverted value of the logical product (A · B) shown in FIG. 4 will be described below. Here, normally, the input signal (A) and its inverted signal (NA) and the input signal (B) and its inverted signal (NB) arrive at the same time, but the input signal groups (A) and (NA) and the input signal Assume that groups (B) and (NB) do not arrive at the same time.

The logical expression corresponding to the circuit configuration shown in FIG.
The logical expressions shown in Expressions (3) to (10) are obtained. Here, regarding the input signals (A) and (B), Expressions (3) to (10)
Is input, and the operation result at that time is output as a logical product (A · B). (NA),
(NB) is a logically inverted value of (A) and (B).

[0053]

(Equation 3) Here, (R) shown in Expressions (3) to (10),
(F) shows a change state of the input signals (A) and (B),
State (R) is a change from level (0) to (1), and state (F) is a change from level (1) to (0). Further, (U) and (D) show the change state of the output, where state (U) is a change from level (0) to (1) and state (D) is a change from level (1) to (0). is there.

Here, regarding the pattern in which the output changes,
First, how the logic circuit of FIG. 4 operates in the case of Expression (5) will be described. In the state indicated by the expression (5), the input signal (A) arrives first and is fixed to the level (1) (at this time, (NA) is the level (0)). In this state, the input signal (B) transitions from level (0) to (1) (state (R)). At this time, (NB) is from level (1) to (0).
(State (F)). Then, the output changes from level (1) to (0) (state (F)).
It is.

At this time, each MOS transistor 401,
Source terminals 4011, 4021, 4031, 4041, 405 of 402, 403, 404, 405, 406
1, 4061, each gate terminal 4012, 4022, 40
32, 4042, 4052, 4062, drain terminals 4013, 4023, 4033, 4043, 4053,
The state of the change of each potential at 4063 is shown using each waveform of FIG.

In FIG. 5, a waveform 501 is a PchMO
This is a change in the potential of each terminal of the transistor when the S transistor 401 changes as in the above equation (5). For simplicity, it is assumed that the threshold voltage Vtp of the PchMOS transistor and the threshold voltage Vtp of the NchMOS transistor have the same potential.

At this time, the gate terminal 4012 changes from level (0) to (1). When the potential difference between the gate and the source falls below the threshold voltage Vtp of the PchMOS transistor, the gate oxide film The channel formed below disappears, the resistance between the source and the drain becomes high, and the source potential is not transmitted to the drain. Time 230 is this time.

Therefore, at a time before time 230, the potential of source terminal 4011 is
013. A waveform 502 is a change in the potential of each terminal when the NchMOS transistor 402 changes according to the equation (5).

The source terminal 4021 is at level (0), and the gate terminal 4022 transitions from level (0) to (1) starting at time 210. At this time, NchMOS
Since the transistor 402 is Nch, when the potential difference Vgs between the gate and the source becomes larger than Vtn, a channel is formed below the gate oxide film, and a current flows from the source to the drain. Before the channel is formed (time 2
Since the potential of the drain terminal 4023 was at the level (1) during the period (between 10 and 220), after the channel was formed (after time 220), current flows from the drain to the source, and the potential of the drain terminal 4023 decreases.

Therefore, the time when the drain potential starts to fall is time 220 when the potential of the gate terminal 4022 becomes Vtn. A waveform 503 is a change in the potential of each terminal when the PchMOS transistor 403 changes according to the equation (5).

The source terminal 4031 is fixed at level (0). The potential of the gate terminal 4032 is at time 21
The transition from level (1) to (0) starts at 0. Therefore, since the potential of the drain terminal 4033 is at the level (1) at the time 410, the potential difference between the gate potential and the drain potential is 0, no channel is formed under the gate oxide film, and the drain terminal 4033 is turned off. is there.

At time 220, gate terminal 4032
Becomes Vdd-Vtp, the difference between the gate potential and the drain potential becomes Vtp, a channel is formed under the gate oxide film, and a current starts flowing between the drain and the source. Accordingly, the potential of the drain terminal 4033 starts to decrease from the time 220 as a starting point, and finally stabilizes at the potential Vtp due to the base bias effect.

Therefore, the time when the potential of the drain terminal 4033 starts to fall is time 220. Waveform 504
Shows the movement of the potential of each terminal when the PchMOS transistor 404 changes according to the equation (5).

The source terminal 4041 is at the level (0), and the gate terminal 4042 is fixed at the level (1). At this time, the PchMOS transistor 404
channel, the potential difference Vgs between the gate and the source is 0
And smaller than Vtp, so that the source and the drain are in a non-conductive state.

Therefore, the drain terminal 4043 is
The state is iZ. Waveform 505 is NchMOS
This is a change in the potential of each terminal when the transistor 405 changes according to Expression (5).

The source terminal 4051 transitions from level (1) to (0). The potential of the gate terminal 4052 is fixed at level (1). Therefore, source terminal 4
When the potential of the transistor 051 is at the level (1), the potential difference Vgs between the gate and the source is 0, so that the source-drain of the NchMOS transistor 405 is not conducting, and the potential of the source terminal 4051 decreases. Vgs is V
When the voltage exceeds tn, a channel is formed below the gate oxide film, and the potential of the drain terminal 4053 starts to decrease.

Therefore, the time when the potential starts to drop is
It is time 220. A waveform 506 is a change in the potential of each terminal when the PchMOS transistor 406 changes according to the equation (5).

Source terminal 4061 transitions from level (1) to (0) starting at time 210. Gate terminal 40
The potential of 62 is fixed at the level (0). Since the potential of the drain terminal 4063 is at the level (1) at the time 210, the potential difference between the gate potential and the drain potential is Vdd, a channel is formed below the gate oxide film, and the channel is conductive.

Accordingly, the time when the potential of the drain terminal 4063 starts to change is time 210, and the potential of the drain terminal 4063 starts to decrease from the time 210, and stabilizes at the potential Vtp due to the base bias effect.

As described above, looking at the operation of the six MOS transistors 401 to 406, the input signals (A),
The time when the change of (B) starts to be transmitted to the output is PchMO
S-transistor 406 begins to change fastest at time 210.

Therefore, when the output values of these transistors are wired-ORed, the output value can be changed at a high speed with respect to the change of the input. Next, the operation of equation (6) will be described.

The input signal (A) is fixed at level (1), and the input signal (B) changes from level (1) to (0). At this time, similarly considered, the transistor in which the potential of the drain terminal changes fastest is NchMO
S transistor 405 and PchMOS transistor 40
It becomes 6.

This is because the potential of the gate terminal of the NchMOS transistor is at level (1), the potential of the source terminal is the input signal (NB), and changes from level (0) to (1). This is because the gate-source potential of the NchMOS transistor 405 is equal to or higher than the threshold potential, and the N-channel MOS transistor 405 is in a common state from the first point in time when the input signal (B) changes from level (1) to (0).

That is, the change in the potential of the input signal (B) is transmitted to the drain terminal with almost no delay, and the signal is propagated at a high speed. Next, the operation of equation (9) will be described.

The input signal (A) changes from level (0) to (1). On the other hand, the input signal (B) is fixed at the level (1). Here, when the input signal changes, the transistor whose drain terminal changes first is the PchMOS transistor 403.

This is because the potential of the gate terminal of the PchMOS transistor is at level (0) and the potential of the input signal (NA) to the source terminal changes from level (1) to (0). The potential difference between the gate and the source of the transistor 403 is higher than the threshold potential, and the input signal (A) changes from level (0) to (1) (the input signal (NA) changes from level (1) to (0)). This is because the conductive state has been established from the first time.

That is, a change in the potential of the input signal (A) is transmitted to the drain terminal with almost no delay, and the signal is propagated at a high speed. Next, the operation of Expression (10) will be described.

The input signal (A) changes from level (1) to (0). On the other hand, the input signal (B) is fixed at the level (1). Here, when the input signal changes, the transistor whose drain terminal changes first is the NchMOS transistor 402.

The reason is that the NchMOS transistor 40
In the case of No. 2, the potential of the gate terminal is at level (1), the potential of the source terminal is (NA), and changes from level (0) to (1). The potential difference is equal to or higher than the threshold potential, and the input signal (A) changes from level (1) to (0) (the input signal (NA) changes from level (0) to (1)) from the first time This is because it is in a conductive state.

That is, a change in the potential of the input signal (A) is transmitted to the drain terminal with almost no delay, and the signal propagates at high speed. As described above, the equation (5) corresponding to the case where the output potential changes according to the input potential,
Regarding (6), (9), and (10), it can be confirmed that a change in the input signal propagates to the output at high speed.

As described above, as in the logic circuit shown in FIG. 1, transistors for transmitting a signal input to a source to an output are configured complementarily, and all types of input signals are transferred from a source to a drain. By being configured to be able to transmit, it is possible to transmit a change in input to the output at high speed.

Therefore, when the present invention is used, the miniaturization of the process and the lowering of the voltage are advanced, and the threshold voltage V
Even when t becomes relatively large with respect to the power supply voltage, the speed of transmitting the input signal to the output can be increased, and a high-speed CMOS logic can be formed. (Embodiment 3) A two-input exclusive OR circuit configured as Embodiment 3 of the present invention will be described.

FIG. 6 is a Carnot map of an inverted value of an exclusive OR operation using two input signals (A) and (B). The logical expression generated using this Carnot map is shown below.

Equation (11) shows a logical equation generated using the input signal (A) as a selection signal.

[0085]

(Equation 4) Here, (•) represents a logical product and (+) represents a logical sum. (NA) is a logically inverted value of (A), and (A),
(NA) is input as a selector selection signal.

Formula (12) shows a logical formula generated by using the input signal (B) as a selection signal.

[0087]

(Equation 5) Here, (NB) is a logically inverted value of (B),
(B) and (NB) are input as selector selection signals.

FIG. 7 is a block diagram showing an example of a logic circuit obtained by expanding the above equations (11) and (12) into logic. In FIG. 7, reference numeral 710 denotes a logic circuit corresponding to a case where the input signals (A) and (NA) shown in Expression (11) are created as selection signals. Reference numeral 711 denotes a logic circuit corresponding to a case where the input signals (B) and (NB) shown in Expression (12) are created as selection signals.

Next, the logic circuit shown in FIG. 7 will be described. FIG. 7 shows a logic circuit which receives an input signal (A) and an input signal (B) and outputs a logically inverted value of an exclusive OR (A ＾ B). 7, 701, 703, 70
5,707 are NchMOS transistors, 702,70
Reference numerals 4,706,708 denote PchMOS transistors.

The input signal (B) is connected to the source of the NchMOS transistor 701, and the input signal (A) is connected to the gate. PchMOS transistor 7
02, the input signal (B) is connected to the source, and the input signal (NA) is connected to the gate. The MOS transistors 701 and 702 have a transistor configuration in which a source and a drain are commonly used.

The input signal (NB) is connected to the source of the NchMOS transistor 703, and the input signal (NA) is connected to the gate. The input signal (NB) is connected to the source of the PchMOS transistor 704, and the input signal (A) is connected to the gate. The MOS transistors 703 and 704 have a transistor configuration in which a source and a drain are commonly used.

The input signal (A) is connected to the source of the NchMOS transistor 705, and the input signal (B) is connected to the gate. PchMOS transistor 7
The input signal (A) is connected to the source of 06, and the input signal (NB) is connected to the gate. The MOS transistors 705 and 706 have a transistor configuration in which a source and a drain are commonly used.

The input signal (NA) is connected to the source of the NchMOS transistor 707, and the input signal (NB) is connected to the gate. The input signal (NA) is connected to the source of the PchMOS transistor 708, and the input signal (B) is connected to the gate. The MOS transistors 707 and 708 have a transistor configuration in which a source and a drain are commonly used.

The drain terminals of all the MOS transistors are connected in common (wired OR), and output the inverted value of the exclusive OR (A ＾ B) of the input signals (A) and (B).

Next, equations (13) to (20) show changes in output when the input signals (A) and (B) change.

[0096]

(Equation 6) Among them, the operation corresponding to the logical expression shown in Expression (19) will be described below with reference to FIG.

A waveform 801 indicates a change in the potential of each terminal of the NchMOS transistor 701 when the NchMOS transistor 701 changes as in the above equation (19). Also for simplicity,
Threshold voltage Vtp of PchMOS transistor
And the threshold voltage Vt of the NchMOS transistor
p is assumed to be the same potential.

At this time, the level of the gate terminal 7012 changes from level (0) to (1). When the potential difference between the gate and the source becomes equal to or higher than the threshold voltage Vtn of the NchMOS transistor, the NchMOS transistor 701 operates under the gate oxide film. Then, a channel is formed between the source and the drain, and a conduction state is established between the source and the drain. However, the drain potential, which is the output potential,
Due to the substrate bias effect, the potential does not rise from the potential of Vdd-Vtp.

Therefore, at a time before time 220, the potential of source terminal 7011 is
013. A waveform 802 is a change in the potential of each terminal of the PchMOS transistor 702. At this time, the potential of the source terminal 7021 is at level (1). The gate terminal 7022 changes from level (1) to (0), and when the potential difference between the gate and the source becomes equal to or more than the threshold voltage Vtp of the PchMOS transistor, a channel is formed under the gate oxide film, A conduction state is established between the source and the drain, and the source potential starts to be transmitted to the drain. Time 220 is this time.

Therefore, at a time before time 220, the potential of source terminal 7021 is
023. A waveform 803 is a change in potential of each terminal of the NchMOS transistor 703. At this time, level (0) is input to the source terminal 7031. The gate terminal 7032 changes from level (1) to (0), and the NchMOS transistor 703 has a gate-source potential difference of NchMOS.
When the voltage becomes equal to or lower than the threshold voltage Vtn of the transistor, the channel disappears under the gate oxide film, the source and the drain become non-conductive, and the source terminal and the drain terminal are insulated. This time is time 230.

Therefore, at a time before time 230, the potential of source terminal 7031 is
033. A waveform 804 is a change in the potential of each terminal of the PchMOS transistor 704. At this time, level (0) is input to the source terminal 7041. The gate terminal 7042 changes from level (0) to (1), and the PchMOS transistor 704 has a gate-source potential difference of PchMO.
When the voltage drops below the threshold voltage Vtp of the S transistor, the channel disappears below the gate oxide film and the source-
The drain is in a non-conductive state, and the source terminal and the drain terminal are insulated. This time is time 230.

Therefore, at a time before time 230, the potential of source terminal 7041 is
043. A waveform 805 is a change in potential of each terminal of the NchMOS transistor 705. At this time, level (1) is input to the gate terminal 7052. The source terminal 7051 changes from level (0) to (1), and the NchMOS transistor 705 has a gate-source potential difference of NchMO.
Since the threshold voltage is higher than the threshold voltage Vtn of the S transistor, a channel is generated under the gate oxide film.
There is conduction between the source and the drain. Therefore, a change in the potential of the source terminal is transmitted to the drain terminal with almost no delay.

Therefore, at a time before time 210, the potential of drain terminal 7053 starts to change.
A waveform 806 is a change in potential of each terminal of the PchMOS transistor 706. At this time, the level (0) is input to the gate terminal 7062. The source terminal 7061 is at level (0) to (1)
Changes to At time 210, PchMOS transistor 706 has a gate-source potential difference of PchM
Since the threshold voltage is lower than the threshold voltage Vtp of the OS transistor, no channel is generated below the gate oxide film, and the source and the drain are in a non-conductive state. Time 22
At 0, the potential between the gate and the source becomes Vtp or more, a channel is formed, and a current starts flowing between the source and the drain.

Therefore, at a time before time 220, the potential of drain terminal 7063 starts to change.
A waveform 807 is a change in potential of each terminal of the NchMOS transistor 707. At this time, the level (0) is input to the gate terminal 7072. The source terminal 7071 is connected from the level (1) to the level (0).
, The NchMOS transistor 707 does not have a channel formed under the gate oxide film, and becomes non-conductive between the source and the drain.

Therefore, a change in the potential of the source terminal is not transmitted to the drain terminal. Waveform 808 is a PchMOS
This is a change in potential of each terminal of the transistor 708. At this time, level (1) is input to the gate terminal 7082. The source terminal 7081
The level changes from (1) to (0), the PchMOS transistor 708 does not have a channel formed under the gate oxide film, and is turned off between the source and the drain.

Therefore, a change in the potential of the source terminal is not transmitted to the drain terminal. These have been described in the case of equation (19). However, even under other conditions, when a signal that is always determined earlier is applied to the gates of the PchMOS transistor and the NchMOS transistor, and a slower signal is applied to the source terminal, the potential remains unchanged. Is transmitted to the drain terminal, and the change in the input is transmitted to the drain terminal with almost no delay.

Therefore, when the potential of the drain terminal in the waveforms 801 to 808 is wired-OR, the time at which the potential of the drain terminal starts to change is 210, and a high-speed exclusive OR that can propagate the change of the input signal to the output at high speed. Can be formed.

In the above, the case of equation (19) has been described. In other cases where the input signal changes and the output changes, the change in the input can be transmitted to the output at a high speed. It is possible to provide an exclusive OR circuit. (Embodiment 4) Next, as Embodiment 4 of the present invention,
Logical sum (A + B) of two inputs with inputs (A) and (B)
The following shows that high-speed logic can be formed for the inversion circuit of FIG.

FIG. 9 is a Carnot map for obtaining an inverted value of a logical sum (A + B) using two input signals (A) and (B). The logical expression generated using this Carnot map is shown below.

Equation (21) shows a logical expression generated using the input signal (A) as a selection signal.

[0111]

(Equation 7) Here, (•) represents a logical product and (+) represents a logical sum. (NA) is a logically inverted value of (A), and (A),
(NA) is input as a selector selection signal.

Expression (22) shows a logical expression generated using the input signal (B) as a selection signal.

[0113]

(Equation 8) Here, (NB) is a logically inverted value of (B),
(B) and (NB) are input as selector selection signals.

FIG. 10 is a block diagram of a logic circuit obtained by expanding the above equations (21) and (22) into logic using pass transistors. In FIG. 10, 1010 is obtained by the equation (2).
A logic circuit corresponding to the logic when the input signals (B) and (NB) shown in 2) are created as selection signals;
Is a logic circuit corresponding to the logic when the input signals (A) and (NA) shown in Expression (21) are created as selection signals. Since the outputs of the logic circuits 1010 and 1011 have the same logic, the outputs are connected (wired OR). This has the same configuration as the circuits shown in FIGS.

Next, the configuration of the logic circuit shown in FIG. 10 will be described. In FIG. 10, 1001, 1003, 1
004 and 1006 are NchMOS transistors, 100
2,1005 is a PchMOS transistor.

First, the logic circuit 1010 will be described. N
The source of the chMOS transistor 1001 is connected to the ground, and the gate is connected to the input signal (B).
The input signal (NA) is connected to the source of the PchMOS transistor 1002, and the input signal (B) is connected to the gate. The input signal (NA) is connected to the source of the NchMOS transistor 1003, and the input signal (NB) is connected to the gate. That is, the MOS transistors 1002 and 1003 have a transistor configuration in which the source and the drain are commonly used.

With this configuration, the logic circuit 10
When the input signal (B) is at the level (1), the NchMOS transistor is turned on and the level (0) is output to the drain, and when the input signal (B) is at the level (0), the PchMOS Transistor 1002 and NchMO
The S transistor 1003 is turned on, and the potential of the input signal (NA) to the source terminal is output to the drain. Therefore, the logic of the logic circuit 1010 is as shown in Expression (22).

Next, the logic circuit 1011 is described. Nc
The source of the hMOS transistor 1004 is connected to ground, and the gate is connected to the input signal (A). Pch
The input signal (N
B) is connected, and the input signal (A) is connected to the gate. The input signal (NB) is connected to the source of the NchMOS transistor 1006, and the input signal (NA) is connected to the gate. That is, the MOS transistor 10
05 and 1006 have a transistor configuration in which the source and the drain are commonly used.

With this configuration, the logic circuit 10
When the input signal (A) is at the level (1), the NchMOS transistor is turned on and the level (0) is output to the drain, and when the input signal (A) is at the level (0), the PchMOS Transistor 1002 and NchMO
The S transistor 1003 is turned on, and the potential of the input signal (NA) to the source terminal is output to the drain. Therefore, the logic of the logic circuit 1010 is as shown in Expression (22).

The drain outputs of the logic circuits 1010 and 1011 are wired-ORed, and the inverted value of the logical sum (A + B) of the input signals (A) and (B) is output. Note that FIG.
Is compared with the conventional logic circuit, the transistor whose signal is input to the source terminal is PchM
The difference is that the OS and NchMOS transistors are configured so as to have a complementary type in which a source terminal and a drain terminal are commonly used.

At this time, the change of the output with respect to the change of the input signal (A) and the input signal (B) is as shown in the equation (30) from the equation (23).

[0122]

(Equation 9) FIG. 11 shows a timing chart in the case of Expression (23).

A waveform 1101 is a change in the potential of each terminal of the NchMOS transistor 1001 when the NchMOS transistor 1001 changes as in the above equation (23). At this time, the gate terminal 10012 changes from level (0) to (1). When the potential difference between the gate and the source becomes equal to or higher than the threshold voltage Vtn of the NchMOS transistor, the NchMOS transistor 1001 forms a channel under the gate oxide film. As a result, a conduction state is established between the source and the drain, the source potential starts to be transmitted to the drain, and the drain potential drops to the level (0). The time when the drain potential starts to drop is 220.

A waveform 1102 shows a change in the potential of each terminal of the PchMOS transistor 1002 when the PchMOS transistor 1002 changes as in the above equation (23). At this time, the potential of the source terminal 10021 changes to level (1), while the potential of the gate terminal 10022 changes from level (0) to (1). Since the gate potential of the PchMOS transistor 1002 is at level (1), no channel is generated below the gate oxide film, and the source and drain are non-conductive. That is, the potential of the drain terminal becomes HiZ.

A waveform 1103 shows a change in the potential of each terminal of the NchMOS transistor 1003 when the NchMOS transistor 1003 changes as in the above equation (23). At this time, the source terminal is at level (1), while the gate terminal 10032 is
The level changes from (1) to (0). The NchMOS transistor 1003 is an NchMOS transistor 100
Since the gate potential of No. 3 is at the level (0), no channel is formed below the gate oxide film, and the source-drain is non-conductive. That is, the drain potential becomes HiZ.

A waveform 1104 shows a change in the potential of each terminal of the NchMOS transistor 1004 when the NchMOS transistor 1004 changes as in the above equation (23). At this time, the source terminal 10041 is at level (0), while the gate terminal 10
Reference numeral 042 is level (0). In the NchMOS transistor 1004, since the gate potential of the NchMOS transistor 1004 is at the level (0), no channel is formed below the gate oxide film, and the source-drain is non-conductive. That is, the drain potential becomes HiZ.

A waveform 1105 indicates a change in the potential of each terminal of the PchMOS transistor 1005 when the PchMOS transistor 1005 changes as in the above equation (23). At this time, the source terminal 10051 changes from level (1) to (0).
On the other hand, the gate terminal 10052 is at level (0).
The PchMOS transistor 1005 has a gate terminal 10
052 is at level (0) and the source terminal 100
Since the potential of 51 is at level (1) at time 210, the channel has been formed below the gate oxide film, and the source-drain becomes conductive. That is, the change in the potential of the source is reflected on the drain potential at time 210 with almost no delay.

A waveform 1106 is a change in the potential of each terminal of the NchMOS transistor 1006 when the NchMOS transistor 1006 changes as in the above equation (23). At this time, the source terminal 10061 transitions from level (1) to (0).
On the other hand, the gate terminal 10062 is at level (1).
The NchMOS transistor 1006 has a gate terminal 10
062 is at level (1) and the source terminal 100
Since the potential of 61 is at level (1) at time 210, a channel is formed under the gate oxide film, and the source-drain becomes conductive. That is, the change in the potential of the source is reflected on the drain potential at time 210 with almost no delay.

As described above, the drain outputs of the waveforms 1101 to 1106 are wired-ORed, and the logical sum (A + B)
Will be output as the inverted value of. Therefore, the time when the change in the input potential starts to appear on the output is time 210, and the output value can be changed at substantially the same time as the change time of the input.

The above is a description of the case of the equation (24). However, in the case where the output signal changes due to a change of the input signal (equations (25), (27), and (28)), similarly, The use of the invention allows a change in the input signal to be propagated to the output signal at high speed.

Therefore, even if the voltage is reduced due to the evolution of the process and the threshold potential with respect to the power supply voltage is increased, the use of the present invention makes it possible to form a high-speed logic.

[0132]

As described above, according to the present invention, when a signal that arrives late among two input signals is input to each source terminal of the PchMOS transistor and the NchMOS transistor, it arrives first at that time. Since the source and the drain are brought into conduction by another signal, a signal arriving late can be transmitted to the drain terminal with almost no delay after being input to the source terminal.

Therefore, it is possible to reduce the time from the start of the operation of an arbitrary operation function to the time when a channel is formed under the gate oxide film of the transistor, and the circuit operation at the time of various operations can be performed at a higher speed than before. Can be

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a high-speed operation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a MOS transistor circuit according to the first embodiment;

FIG. 3 is a Karnaugh diagram showing an inverted value of a logical product of input signals (A) and (B) in the high-speed operation circuit according to the second embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration example of a high-speed operation circuit according to the second embodiment;

FIG. 5 is a timing chart showing an operation in the second embodiment.

FIG. 6 is a Karnaugh diagram showing an inverted value of an exclusive OR of input signals (A) and (B) in the high-speed operation circuit according to the third embodiment of the present invention;

FIG. 7 is a block diagram of a high-speed exclusive OR circuit which is a configuration example of the high-speed operation circuit according to the third embodiment;

FIG. 8 is a timing chart showing an operation in the third embodiment.

FIG. 9 is a Karnaugh diagram illustrating an inverted value of a logical sum of input signals (A) and (B) in the high-speed operation circuit according to the fourth embodiment of the present invention;

FIG. 10 is a block diagram of a high-speed OR circuit which is a configuration example of the high-speed operation circuit according to Embodiment 4;

FIG. 11 is a timing chart showing an operation in the fourth embodiment.

FIG. 12 is a block diagram of a logical product circuit which is a configuration example of a conventional high-speed operation circuit.

FIG. 13 is a block diagram of an exclusive OR circuit as another configuration example of the conventional high-speed operation circuit.

[Explanation of symbols]

Reference Signs List 101 MOS transistor logic circuit 102 MOS transistor logic circuit 103 Wired OR circuit 201 MOS circuit 202 NchMOS transistor (PchMOS transistor)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J042 BA18 CA21 CA24 CA25 CA26 DA03 5J056 AA03 BB02 CC26 CC27 DD13 DD29 EE03 EE15 FF09 GG09 GG14

Claims (5)

[Claims] 1. Two logically complementary signals are formed as a set of two P-channel and N-channel MOS transistors, and two sets of signals are defined as first and second input signals, and are logically complementary to each other. A CMOS logic circuit using a set of two signals as an output signal, comprising a plurality of MOS transistors, wherein the first input signal is supplied to each source of the MOS transistors, and the second input is supplied to each gate. A third MOS transistor group to which a signal is supplied and a plurality of MOS transistors, the second input signal is supplied to each source of the MOS transistors, and the first input signal is supplied to each gate. ,
A fourth MOS transistor group having the same output logic as the third MOS transistor group, and means for logically wired-ORing each output signal of the third MOS transistor group and the fourth MOS transistor group And a high-speed operation circuit that constitutes a high-speed logic circuit having: 2. A third MOS transistor group and a fourth M transistor group.
OS transistors are divided into a plurality of MOS transistors
P of which input signal is input to the source of the transistor
2. The high-speed operation circuit according to claim 1, wherein the chMOS transistor and the NchMOS transistor are paired and each source and each drain are short-circuited. 3. A pair of signals (A) and (NA) or (B) and (NB), which are constituted by P-channel and N-channel MOS transistors, and are paired with two signals logically complementary to each other. A two-input AND circuit having a first MOS logic circuit and a second MOS logic circuit as first and second input signals, wherein a power is supplied to a source of the first MOS logic circuit, and a gate is provided. Input signal (B)
Is supplied and the drain is connected to the third node.
a pair of PchMOS transistor and NchMOS transistor having a source and a drain commonly connected to each other, and an input signal (NA) is supplied to each source in the pair of PchMOS transistor and the NchMOS transistor; Is connected to the third node, and P
Input signal (NB) to the gate on the side of the chMOS transistor
And the input signal (B) is supplied to the gate on the side of the NchMOS transistor.
The OS logic circuit includes a PchMOS transistor having a source supplied with power, a gate supplied with the input signal (A), a drain connected to the fourth node, and a pair of PchMO transistors having a source and a drain commonly connected.
An S-channel transistor and an N-channel MOS transistor.
In the chMOS transistor, an input signal (NB) is supplied to each source, each drain is connected to the fourth node, an input signal (NA) is supplied to a gate on the PchMOS transistor side, and an input signal is supplied to a gate on the NchMOS transistor side. A signal (A) is provided,
A high-speed arithmetic circuit that forms a two-input AND circuit that short-circuits the third node and the fourth node and obtains a logical output from the short-circuit point. 4. Two sets of signals (A) and (NA) or (B) and (NB), which are constituted by Pch and Nch MOS transistors, and are paired with two signals that are logically complementary to each other, A two-input OR circuit having a first MOS logic circuit and a second MOS logic circuit as first and second input signals, wherein the first MOS logic circuit has a source connected to ground, a gate Input signal (B)
Is supplied, and the drain is connected to the third node.
a pair of PchMOS transistor and NchMOS transistor having a source and a drain commonly connected to each other, and an input signal (NA) is supplied to each source in the pair of PchMOS transistor and the NchMOS transistor; Is connected to the third node, and P
The input signal (B) is supplied to the gate on the chMOS transistor side, and the input signal (NB) is supplied to the gate on the NchMOS transistor side.
An OS logic circuit includes an NchMOS transistor having a source connected to ground, a gate supplied with an input signal (A), a drain connected to a fourth node, and a PchMO transistor having a source and a drain commonly connected to form a pair.
An S-channel transistor and an N-channel MOS transistor.
In the chMOS transistor, an input signal (NB) is supplied to each source, each drain is connected to the fourth node, an input signal (A) is supplied to a gate on the PchMOS transistor side, and an input signal is supplied to a gate on the NchMOS transistor side. Signal (NA) is provided,
A high-speed arithmetic circuit that forms a two-input OR circuit that short-circuits the third node and the fourth node and obtains a logical output from the short-circuit point. 5. Two sets of signals (A) and (NA) or (B) and (NB), which are constituted by Pch and Nch MOS transistors, and are paired with two signals which are logically complementary to each other. A two-input exclusive-OR circuit having a first MOS logic circuit and a second MOS logic circuit as first and second input signals, wherein the first MOS logic circuit has a common source and a common drain. PchMOS transistor and Nch connected to form a pair
An input signal (B) is supplied to each source of the pair of the PchMOS transistor and the NchMOS transistor;
Each drain is connected to the third node, and an input signal (NA) is supplied to a gate on the PchMOS transistor side;
An input signal (A) is applied to the gate on the NchMOS transistor side.
In the pair of the other PchMOS transistor and NchMOS transistor, an input signal (NB) is supplied to each source, each drain is connected to the third node, and an input signal (NB) is supplied to a gate on the PchMOS transistor side. A) is supplied, and the input signal (NA) is supplied to the gate of the Nch MOS transistor side. The second MOS logic circuit is composed of a pair of Pc having a source and a drain commonly connected to each other.
Two sets of hMOS transistors and NchMOS transistors are provided. In the one pair of the PchMOS transistor and the NchMOS transistor, an input signal (A) is supplied to each source, each drain is connected to the fourth node, and the PchMOS transistor side The input signal (NB) is supplied to the gate, the input signal (B) is supplied to the gate on the NchMOS transistor side, and the other pair of PchMOS transistor and Nch
In a MOS transistor, an input signal (N
A), each drain is connected to the fourth node, the input signal (B) is supplied to the gate on the PchMOS transistor side, and the input signal (NB) is supplied to the gate on the NchMOS transistor side. A high-speed operation circuit configured to short-circuit the third node and the fourth node to form a two-input exclusive-OR circuit that obtains a logical output from the short-circuit point.