JP2002076286A - Metal oxide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS semiconductor device which is highly integrated, and capable of easily improving infinitesimal current, due to a parasitic transistor. SOLUTION: A shielding layer 5 formed of a metal or a shielding layer formed of a polysilicon is formed only on the upper part of a low-voltage circuit region 2, and its upper part is sealed by a protective oxide film 4 and furthermore by a potting resin layer 3 on top of it. Thus, a distance between the region 2 and the layer 3 is broadened, and the influence of electric charges in the layer 3 is alleviated by the influences of high-voltage regions 1 and 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a metal oxide (M) having a low voltage circuit driven by a logic voltage and a high withstand voltage circuit driven by a voltage higher or lower than the logic voltage.
The present invention relates to a semiconductor device including an (OS) type transistor.

[0002]

2. Description of the Related Art A semiconductor device comprising a metal oxide (MOS) transistor having a low voltage circuit driven by a logic voltage and a high withstand voltage circuit driven by a voltage higher or lower than the logic voltage has conventionally been known. Are known.

Hereinafter, the conventional MOS type semiconductor circuit device will be described with reference to the drawings.

FIG. 5 shows a low voltage circuit 2 composed of a MOS type semiconductor operating at a logic voltage and high voltage circuits 1, 1 composed of a MOS type semiconductor operating at a voltage higher than the logic voltage. FIG. 2 is a configuration diagram of a MOS type semiconductor circuit device in which the high withstand voltage circuit portions 1 and 1 are arranged outside the low voltage circuit portion 2. A potting resin layer 3 for encapsulating a semiconductor device is provided around a region of the high voltage circuits 1 and 1 driven by a voltage higher than the logic voltage and a region of the low voltage circuit 2 driven by the logic voltage, and a surface of the semiconductor circuit device. A protective oxide film 4 for protecting the substrate is formed.

[0005]

The above-mentioned conventional device has a low voltage circuit 2 driven by a logic voltage and high voltage circuits 1, 1 driven by a voltage higher or lower than the logic voltage. , Potting resin layer 3
When the package is mounted, since the potential of the high-withstand-voltage circuit regions 1 and 1 is high, charges are charged on the potting resin layer 3 and the low-voltage circuit 2 is disposed inside the high-withstand-voltage circuits 1 and 1. Therefore, the area of the potting resin layer 3 above the area of the low-voltage circuit 2 is also charged with a high voltage under the influence of the area of the high-voltage circuits 1 and 1. Therefore, there is a problem that when the potential becomes higher than the ON potential of the parasitic transistor formed in the low-voltage circuit section region 2, the parasitic transistor is turned on and a minute current is generated.

In order to eliminate the parasitic transistor, as shown in FIG.
Must be surrounded by a P-type diffusion region 11 having the same potential as the source potential of the N-type transistor source 13 or the distance between the N-type MOS transistor 10 and the adjacent N-type MOS transistor 10 must be increased. There was a problem that it had to be larger.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS semiconductor device which is highly integrated and can easily reduce a small current caused by a parasitic transistor in order to solve the above-mentioned conventional problems.

[0008]

To achieve the above object, a first metal oxide semiconductor device of the present invention is a low voltage circuit composed of a metal oxide (MOS) semiconductor operated at a logic voltage. And a high-voltage circuit constituted by a MOS semiconductor operating at a low voltage different from the logic voltage, wherein the high-voltage circuit section is arranged so as to sandwich the low-voltage circuit section. A metal layer different from a wiring layer is formed in a portion on the low-voltage circuit section region.

Next, a second metal oxide semiconductor device according to the present invention is a metal oxide (MO) operating at a logic voltage.
S) a low-voltage circuit composed of a semiconductor, and a high-voltage circuit composed of a MOS semiconductor that operates at a low voltage different from the logic voltage, wherein the high-voltage circuit is sandwiched by the low-voltage circuit unit And a second polysilicon layer different from the first polysilicon layer for forming a transistor is formed in a portion on the low-voltage circuit portion region.

In the semiconductor device, a layer covering the entire surface of the low-voltage circuit area is formed by a logic voltage or a ground (G).
It is preferable to fix the voltage to ND).

In the semiconductor device, a logic voltage is applied to the entire surface of the P-type well on the low-voltage circuit area, and a potential different from GND is applied to the entire surface of the N-type well. It is preferable to form by fixing.

Next, a third metal oxide semiconductor device of the present invention is a metal oxide (MO) device which operates at a logic voltage.
S) a low-voltage circuit composed of a semiconductor and a high-voltage circuit composed of a MOS-type semiconductor operating at a voltage different from the logic voltage, wherein the high-voltage circuit is arranged so as to sandwich the low-voltage circuit; Semiconductor device,
A first covering a region of the low-voltage circuit portion and the high-withstand-voltage circuit portion;
And a second protective film is further formed on the entire surface of the protective oxide film on the low voltage circuit region.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOS type semiconductor device according to the present invention
A metal layer such as aluminum, a polysilicon layer, or a polyimide protective film is formed on the protective oxide film only over the entire area of the low voltage circuit section driven by the logic voltage. When a metal layer such as aluminum or a polysilicon layer is used, the potential of each layer is fixed to VDD (logic voltage) or VSS (ground voltage) as indicated by 7 and 8. .

According to this configuration, the distance from the potting resin layer to the low-voltage circuit driven by the logic voltage is increased, so that the influence of the electric charges charged on the potting resin is less likely to be received by the low-voltage circuit driven by the logic voltage. According to another embodiment, by fixing the potential, the influence of the potting resin is further reduced by a low-voltage circuit driven by a logic voltage. Also, since there is no need to increase the distance between the transistors to increase the ON voltage of the parasitic transistor or to surround each transistor with a guard band, a MOS type semiconductor device that is highly integrated and does not generate a small current due to the parasitic transistor. Can be obtained.

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a MOS type semiconductor circuit device having a low voltage circuit driven by a logic voltage and a high withstand voltage circuit driven by a voltage higher than the logic voltage, and sealed with a potting resin.
FIG. 1B is a cross-sectional view thereof.

In FIGS. 1A and 1B, the high-withstand-voltage circuit regions 1 and 1 are arranged outside the low-voltage circuit region 2 so as to sandwich the low-voltage circuit region 2 therebetween. The metal layer 5 is formed only in the upper part of the low voltage part circuit region 2, and the upper part is sealed with the protective oxide film 4 and the potting resin layer 3.

By forming the metal layer 5 between the low-pressure part region 2 and the potting resin layer 3, the distance between the low-pressure part region 2 and the potting resin layer 3 is widened, and the influence of the high-pressure part regions 1 and 1 is increased. The effect of the electric charge charged on the potting resin layer 3 can be reduced.

In the above, the high withstand voltage circuit regions 1 and 1, the low voltage circuit region 2, the potting resin layer 3, the protective oxide film 4
Can be formed by a known method. When an aluminum layer (a metal layer different from the wiring layer) is used as the metal layer 5, for example, a protective oxide film is formed on the surface of the wiring layer, and the surface can be formed by a known method such as an evaporation method.

(Embodiment 2) FIG. 2 shows a MOS type semiconductor circuit device having a low voltage circuit driven by a logic voltage and a high withstand voltage circuit driven by a voltage higher than the logic voltage, and sealed with a potting resin. It is a block diagram.

In FIG. 2, the high breakdown voltage circuit regions 1 and 1 are arranged outside the low voltage circuit region 2,
The polysilicon layer 6 is disposed only above the low-voltage section circuit region 2, and the upper portion thereof is sealed with a protective oxide film 4 and a potting resin layer 3.

By forming a shield layer of polysilicon 6 between the low-voltage part region 2 and the potting resin layer 3, the distance between the low-voltage part region 2 and the potting resin layer 3 is increased, and The influence of the electric charge charged on the potting resin layer 3 can be reduced by the influence.

In the above, the high withstand voltage section circuit regions 1, 1,.
The low-voltage circuit region 2, the potting resin layer 3, and the first protective oxide film (first polysilicon layer) 4 can be formed by a known method. The polysilicon layer 6 can also be formed by a known method.

(Embodiment 3) FIG. 3 shows a MOS type semiconductor circuit device having a low voltage circuit driven by a logic voltage and a high withstand voltage circuit driven by a voltage higher than the logic voltage, and sealed with a potting resin. It is a block diagram.

In FIG. 3, the high withstand voltage circuit areas 1, 1,.
Low-voltage circuit area 2, potting resin layer 3, protective oxide film 4, shield layer 7 fixed by logic voltage, GND
The shield layer 8 is fixed at the voltage V.sub.1, and the shield layer 7 is formed on the region of the N-type well and the shield layer 8 is formed on the region of the P-type well.

In this semiconductor circuit device, the high-withstand-voltage circuit regions 1 and 1 are arranged outside the low-voltage circuit region 2 so as to sandwich the low-voltage circuit region 2.
Shield layers 7 and 8 made of a metal layer or polysilicon are formed only on the upper portion of the substrate, and the upper portions thereof are sealed with a protective oxide film 4 and a potting resin layer 3.

By fixing the shield layers 7 and 8 made of metal or polysilicon to a logic power source or a GND power source between the low-voltage part region 2 and the potting resin layer 3, potting is effected by the high-voltage part region 1. The influence of the electric charge charged on the resin layer 3 can be prevented from affecting the circuit in the low-voltage section region 2. The shield layers 7, 8 can also be formed by a known method.

(Embodiment 4) In FIG. 4, reference numeral 1 denotes a high withstand voltage circuit region, 2 denotes a low voltage circuit region, 3 denotes a potting resin, 4 denotes a protective oxide film, and 9 denotes a protective film made of polyimide.

In this semiconductor circuit device, the high breakdown voltage circuit regions 1 and 1 are formed outside the low voltage circuit region 2 and are arranged so as to sandwich the low voltage circuit region 2. A polyimide protective film 7 is formed on the protective oxide film and is sealed with a potting resin layer 3.

By forming the polyimide protective film 9 between the low-pressure part region 2 and the potting resin layer 3, the distance between the low-pressure part region 2 and the potting resin layer 3 is increased, and the influence of the high-pressure part regions 1 and 1 is increased. 3 can reduce the influence of the electric charge charged on the potting resin layer 3. The polyimide protective film 9 can also be formed by a known method.

As described above, according to the embodiment of the present invention, the low-voltage circuit section region 2 driven by the logic voltage is formed of the metal layer 5 of aluminum or the like, the polysilicon layer 6 or the polyimide protection film 9 is formed of the protection oxide film 4. When the metal layer 5 such as aluminum or the polysilicon layer 6 is used, or when the potential of each layer is fixed like the fixed potential layers 8 and 9, the logic voltage is reduced from the potting resin layer 3. It is possible to increase the distance to the low-voltage circuit driven by the low-voltage circuit 2 driven by the logic voltage, due to the influence of the electric charge charged on the potting resin layer.
In addition, by fixing the potential, the influence of the potting resin can be further reduced by a low-voltage circuit driven by a logic voltage. In addition, since it is not necessary to increase the distance between the transistors to increase the ON voltage of the parasitic transistor or to surround each transistor with a guard band, a MOS type semiconductor device which is highly integrated and does not generate a small current in the parasitic transistor. Can be obtained.

[0031]

According to the present invention, a shield layer made of metal or a shield layer made of polysilicon is formed only on the upper part of the low-voltage circuit region, and the upper part is sealed with a protective oxide film and a potting resin. Thereby, the distance between the low-pressure region and the potting resin can be increased, and the influence of the electric charge on the potting resin due to the influence of the high-pressure region can be reduced. This makes it possible to improve the small current caused by the parasitic transistor with high integration and easily.
An OS type semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1A shows an MO according to a first embodiment of the present invention.
Plan view of an S-type semiconductor, and FIG.

FIG. 2 is a sectional view showing a configuration of a MOS semiconductor according to a second embodiment of the present invention;

FIG. 3 is a sectional view showing a configuration of semiconductor output protection according to a third embodiment of the present invention;

FIG. 4 is a sectional view showing a configuration of semiconductor output protection according to a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the configuration of a conventional N-type MOS semiconductor formed in a P-well region operated at a logic voltage.

FIG. 6 is a plan view showing a circuit configuration of a conventional MOS output circuit.

[Explanation of symbols]

 1, 1 high withstand voltage circuit area 2 low voltage circuit area 3 potting resin layer 4 first protective oxide film (first polysilicon layer) 5 aluminum layer (metal layer different from wiring layer) 6 second polysilicon layer Layer 7 Fixed potential layer (VDD) 8 Fixed potential layer (VSS) 9 Polyimide protective film (second protective film) 10 N-type MOS transistor 11 P-type diffusion region 12 Contact 13 N-type transistor source 14 N-type transistor drain (ON Potential) 15 N-type MOS transistor drain (OFF potential)

Claims (5)

[Claims] 1. A metal oxide (MO) operating at a logic voltage.
S) a low-voltage circuit composed of a semiconductor, and a high-voltage circuit composed of a MOS semiconductor that operates at a low voltage different from the logic voltage, wherein the high-voltage circuit is sandwiched by the low-voltage circuit unit A metal oxide semiconductor device, wherein a metal layer different from a wiring layer is formed in a portion on the low-voltage circuit portion region. 2. A metal oxide (MO) operating at a logic voltage.
S) a low-voltage circuit composed of a semiconductor, and a high-voltage circuit composed of a MOS semiconductor that operates at a low voltage different from the logic voltage, wherein the high-voltage circuit is sandwiched by the low-voltage circuit unit A metal part, wherein a second polysilicon layer different from a first polysilicon layer forming a transistor is formed in a part on the low-voltage circuit part region, wherein Oxide semiconductor devices. 3. The metal oxide semiconductor device according to claim 1, wherein a layer covering the entire surface of the low-voltage circuit section region is fixed to a logic voltage or a ground (GND) voltage. 4. A logic voltage is applied to the entire surface of the region forming the P-type well on the low-voltage circuit region, and the entire surface of the region forming the N-type well is fixed to a potential different from GND. 3. The metal oxide semiconductor device according to claim 1, wherein 5. A metal oxide (MO) operating at a logic voltage.
S) a low-voltage circuit composed of a semiconductor and a high-voltage circuit composed of a MOS-type semiconductor operating at a voltage different from the logic voltage, wherein the high-voltage circuit is arranged so as to sandwich the low-voltage circuit; Semiconductor device,
A first covering a region of the low-voltage circuit portion and the high-withstand-voltage circuit portion;
And a second protective film is further formed on the entire surface of the protective oxide film on the low-voltage circuit region.