JP2002076246A - Method for manufacturing circuit device - Google Patents

Method for manufacturing circuit device

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Publication number
JP2002076246A
JP2002076246A JP2000266737A JP2000266737A JP2002076246A JP 2002076246 A JP2002076246 A JP 2002076246A JP 2000266737 A JP2000266737 A JP 2000266737A JP 2000266737 A JP2000266737 A JP 2000266737A JP 2002076246 A JP2002076246 A JP 2002076246A
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Prior art keywords
circuit device
insulating resin
conductive
method
circuit
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JP2000266737A
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JP3600131B2 (en
Inventor
Yuusuke Igarashi
Yoshiyuki Kobayashi
Eiju Maehara
Yukio Okada
Junji Sakamoto
Noriaki Sakamoto
Yukitsugu Takahashi
優助 五十嵐
栄寿 前原
則明 坂本
義幸 小林
幸夫 岡田
純次 阪本
幸嗣 高橋
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Sanyo Electric Co Ltd
三洋電機株式会社
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Priority to JP2000266737A priority Critical patent/JP3600131B2/en
Publication of JP2002076246A publication Critical patent/JP2002076246A/en
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Publication of JP3600131B2 publication Critical patent/JP3600131B2/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a circuit device which is mounted on a circuit element using a ceramic board or a flexible board as a supporting board that the thickness of the supporting board impedes reduction of size and thickness of the circuit device. SOLUTION: After a conductive pattern 51 for each bock has been formed on a conductive foil 60 using isolation trenches 61, a circuit element is mounted and molded of insulating resin 50, before being isolated by a conductive pattern formed by etching the rear surface of the conductive foil. Furthermore, resource- saving manufacturing method of a circuit device suitable for mass production can be implemented, by introducing a measuring process for each bock and a dicing process.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、回路装置の製造方法に関し、特に支持基板を不要にした薄型の回路装置の製造方法に関するものである。 The present invention relates to relates to a method of manufacturing a circuit device, a method of manufacturing a thin circuit device particularly unnecessary support substrate.

【0002】 [0002]

【従来の技術】従来、電子機器にセットされる回路装置は、携帯電話、携帯用のコンピューター等に採用されるため、小型化、薄型化、軽量化が求められている。 Conventionally, circuit devices to be set in the electronic device, since the mobile phone, is employed in a computer or the like of the portable, compact, thinner, lighter is required.

【0003】例えば、回路装置として半導体装置を例にして述べると、一般的な半導体装置として、従来通常のトランスファーモールドで封止されたパッケージ型半導体装置がある。 For example, when described as an example of a semiconductor device as a circuit device, as a general semiconductor device, there is a conventional normal package type semiconductor device sealed by transfer molding. この半導体装置は、図10のように、プリント基板PSに実装される。 The semiconductor device, as shown in FIG. 10, is mounted on the printed board PS.

【0004】またこのパッケージ型半導体装置は、半導体チップ2の周囲を樹脂層3で被覆し、この樹脂層3の側部から外部接続用のリード端子4が導出されたものである。 [0004] The packaged semiconductor device, the periphery of the semiconductor chip 2 covered with a resin layer 3, in which the lead terminal 4 from the side of the external connection resin layer 3 was derived.

【0005】しかしこのパッケージ型半導体装置1は、 [0005] However, this package type semiconductor device 1,
リード端子4が樹脂層3から外に出ており、全体のサイズが大きく、小型化、薄型化および軽量化を満足するものではなかった。 Lead terminals 4 are to go out from the resin layer 3, a large overall size, size reduction, did not satisfy the thickness and weight reduction.

【0006】そのため、各社が競って小型化、薄型化および軽量化を実現すべく、色々な構造を開発し、最近ではCSP(チップサイズパッケージ)と呼ばれる、チップのサイズと同等のウェハスケールCSP、またはチップサイズよりも若干大きいサイズのCSPが開発されている。 [0006] Therefore, miniaturization competing each company, in order to realize a thin and lightweight, to develop a variety of structure, recently called a CSP (chip size package), the size of the chip and the equivalent of wafer scale CSP, or CSP slightly larger size have been developed than the chip size.

【0007】図11は、支持基板としてガラスエポキシ基板5を採用した、チップサイズよりも若干大きいCS [0007] Figure 11 adopts the glass epoxy substrate 5, slightly larger than the chip size CS as the support substrate
P6を示すものである。 It shows the P6. ここではガラスエポキシ基板5 Here, the glass epoxy substrate 5
にトランジスタチップTが実装されたものとして説明していく。 Will be described as a transistor chip T is mounted on.

【0008】このガラスエポキシ基板5の表面には、第1の電極7、第2の電極8およびダイパッド9が形成され、裏面には第1の裏面電極10と第2の裏面電極11 [0008] On the surface of this glass epoxy substrate 5, the first electrode 7, the second electrode 8 and a die pad 9 are formed, the first back electrode 10 on the back side second back electrode 11
が形成されている。 There has been formed. そしてスルーホールTHを介して、 And through a through hole TH,
前記第1の電極7と第1の裏面電極10が、第2の電極8と第2の裏面電極11が電気的に接続されている。 Wherein the first electrode 7 is the first back electrode 10, and the second electrode 8 and the second back electrode 11 are electrically connected. またダイパッド9には前記ベアのトランジスタチップTが固着され、トランジスタのエミッタ電極と第1の電極7 The transistor chip T of the bare is fixed to the die pad 9, the emitter electrode and the first electrode of the transistor 7
が金属細線12を介して接続され、トランジスタのベース電極と第2の電極8が金属細線12を介して接続されている。 There are connected via a thin metal wire 12, a base electrode and a second electrode 8 of the transistor is connected via a metal thin wire 12. 更にトランジスタチップTを覆うようにガラスエポキシ基板5に樹脂層13が設けられている。 The resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.

【0009】前記CSP6は、ガラスエポキシ基板5を採用するが、ウェハスケールCSPと違い、チップTから外部接続用の裏面電極10、11までの延在構造が簡単であり、安価に製造できるメリットを有する。 [0009] The CSP6 is to employ a glass epoxy substrate 5, unlike the wafer scale CSP, it is easy extending structure from the chip T to the back electrodes 10 and 11 for external connection, the benefits can be manufactured at low cost a.

【0010】また前記CSP6は、図10のように、プリント基板PSに実装される。 [0010] The CSP6, as in FIG. 10, is mounted on the printed board PS. プリント基板PSには、 The printed circuit board PS,
電気回路を構成する電極、配線が設けられ、前記CSP Electrodes, wiring is provided to constitute an electric circuit, the CSP
6、パッケージ型半導体装置1、チップ抵抗CRまたはチップコンデンサCC等が電気的に接続されて固着される。 6, the package type semiconductor device 1, a chip resistor CR or chip capacitor CC and the like are fixed to be electrically connected.

【0011】そしてこのプリント基板で構成された回路は、色々なセットの中に取り付けられる。 [0011] The circuit constituted by the printed circuit board is mounted in a variety of sets.

【0012】つぎに、このCSPの製造方法を図12および図13を参照しながら説明する。 [0012] will be described below with reference to FIGS. 12 and 13 the method of manufacturing the CSP.

【0013】まず基材(支持基板)としてガラスエポキシ基板5を用意し、この両面に絶縁性接着剤を介してC [0013] First, the glass epoxy substrate 5 is prepared as the substrate (support substrate), C via an insulating adhesive to the both surfaces
u箔20、21を圧着する。 Crimping the u foil 20 and 21. (以上図12Aを参照) 続いて、第1の電極7,第2の電極8、ダイパッド9、 (Or see Fig. 12A) Then, the first electrode 7, the second electrode 8, the die pad 9,
第1の裏面電極10および第2の裏面電極11対応するCu箔20、21に耐エッチング性のレジスト22を被覆し、Cu箔20、21をパターニングする。 Coating the etching resistance of the resist 22 on the Cu foil 20 and 21 corresponding first back electrode 10 and the second back electrode 11, patterning the Cu foil 20, 21. 尚、パターニングは、表と裏で別々にしても良い。 In addition, patterning, may be separately in the front and back. (以上図12 (More than 12
Bを参照) 続いて、ドリルやレーザを利用してスルーホールTHのための孔を前記ガラスエポキシ基板に形成し、この孔にメッキを施し、スルーホールTHを形成する。 B See) Subsequently, the hole for the through hole TH formed in the glass epoxy substrate using a drill or laser, plating in the hole to form a through hole TH. このスルーホールTHにより第1の電極7と第1の裏面電極1 The through hole TH and the first electrode 7 first back electrode 1
0、第2の電極8と第2の裏面電極10が電気的に接続される。 0, a second electrode 8 and the second back electrode 10 are electrically connected. (以上図12Cを参照) 更に、図面では省略をしたが、ボンデイングポストと成る第1の電極7,第2の電極8にAuメッキを施すと共に、ダイボンディングポストとなるダイパッド9にAu (Or see Fig. 12C) further, in the drawings have the omitted first electrode 7 serving as a bonding post, is performed with the Au plating on the second electrode 8, the die pad 9 which becomes a die bonding post Au
メッキを施し、トランジスタチップTをダイボンディングする。 Plated, die bonding the transistor chip T.

【0014】最後に、トランジスタチップTのエミッタ電極と第1の電極7、トランジスタチップTのベース電極と第2の電極8を金属細線12を介して接続し、樹脂層13で被覆している。 [0014] Finally, the emitter electrode and the first electrode 7 of the transistor chip T, a base electrode and a second electrode 8 of the transistor chip T is connected via the metal thin wire 12, it is covered with the resin layer 13. (以上図12Dを参照) 以上の製造方法により、支持基板5を採用したCSP型の電気素子が完成する。 The (or see FIG. 12D) the manufacturing method described above, CSP type electrical device employing the supporting substrate 5 is completed. この製造方法は、支持基板としてフレキシブルシートを採用しても同様である。 This manufacturing method is also adopted a flexible sheet as the support substrate.

【0015】一方、セラミック基板を採用した製造方法を図13のフローに示す。 Meanwhile, showing a manufacturing method adopting a ceramic substrate to the flow of FIG 13. 支持基板であるセラミック基板を用意した後、スルーホールを形成し、その後、導電ペーストを使い、表と裏の電極を印刷し、焼結している。 After preparing the ceramic substrate which is a supporting substrate, forming a through hole, then use the conductive paste was printed front and back electrodes, and sintering. その後、前製造方法の樹脂層を被覆するまでは図1 Thereafter, until covering the resin layer before the manufacturing method 1
2の製造方法と同じであるが、セラミック基板は、非常にもろく、フレキシブルシートやガラスエポキシ基板と異なり、直ぐに欠けてしまうため金型を用いたモールドができない問題がある。 Is the same as the second manufacturing method, the ceramic substrate is very fragile, unlike flexible sheet or a glass epoxy substrate, the mold there is a problem that can not be using a mold for would immediately chipped. そのため、封止樹脂をポッティングし、硬化した後、封止樹脂を平らにする研磨を施し、最後にダイシング装置を使って個別分離している。 Therefore, potted sealing resin, after curing, polished to flatten the sealing resin are individually separated with the last dicing apparatus.

【0016】 [0016]

【発明が解決しようとする課題】図11に於いて、トランジスタチップT、接続手段7〜12および樹脂層13 In FIG. 11 [0008], the transistor chip T, connecting means 7 to 12 and the resin layer 13
は、外部との電気的接続、トランジスタの保護をする上で、必要な構成要素であるが、これだけの構成要素で小型化、薄型化、軽量化を実現する回路素子を提供するのは難しかった。 An electrical connection to the outside, in order to protect the transistor, is a necessary component, miniaturization only this component, thinner, to provide circuit elements for realizing the weight reduction is difficult .

【0017】また、支持基板となるガラスエポキシ基板5は、前述したように本来不要なものである。 Further, the glass epoxy substrate 5 which becomes the support substrate is unnecessary originally as described above. しかし製造方法上、電極を貼り合わせるため、支持基板として採用しており、このガラスエポキシ基板5を無くすことができなかった。 But the manufacturing process, for bonding the electrode adopts as the supporting substrate, it was not possible to eliminate this glass epoxy substrate 5.

【0018】そのため、このガラスエポキシ基板5を採用することによって、コストが上昇し、更にはガラスエポキシ基板5が厚いために、回路素子として厚くなり、 [0018] Therefore, by adopting this glass epoxy substrate 5, the cost increases, even for thick glass epoxy substrate 5, thickened as a circuit element,
小型化、薄型化、軽量化に限界があった。 Smaller, thinner, there is a limit to the weight reduction.

【0019】更に、ガラスエポキシ基板やセラミック基板では必ず両面の電極を接続するスルーホール形成工程が不可欠であり、製造工程も長くなる問題もあった。 Furthermore, the through hole forming step of connecting a sure both sides of the electrodes in a glass epoxy substrate or a ceramic substrate is essential, there is also the manufacturing process becomes long problems.

【0020】 [0020]

【課題を解決するための手段】本発明は、前述した多くの課題に鑑みて成され、導電箔を用意し、少なくとも回路素子の搭載部を多数個形成する導電パターンを除く領域の前記導電箔に前記導電箔の厚みよりも浅い分離溝を形成して導電パターンを形成する工程と、所望の前記導電パターンの前記各搭載部に回路素子を固着する工程と、各搭載部の前記回路素子を一括して被覆し、前記分離溝に充填されるように絶縁性樹脂で共通モールドする工程と、前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、前記絶縁性樹脂で一括してモールドされた各搭載部の前記回路素子の特性の測定を行う工程と、前記絶縁性樹脂を各搭載部毎にダイシングにより分離する工程とを具備することを特徴とする。 The present invention SUMMARY OF] is made in view of the many problems described above, providing a conductive foil, the conductive foil regions except the conductive patterns to a large number forming a mounting portion of at least the circuit elements forming a conductive pattern to form a shallow isolation trench than the thickness of the conductive foil, a step of fixing the circuit element to the respective mounting portions of the desired of the conductive pattern, the circuit elements of the mounting portion collectively coated, a step of common molding an insulating resin to be filled in the isolation trench, and removing the conductive foil having a thickness of a portion not provided the separation grooves, collectively the insulating resin characterized by comprising by the steps of performing a measurement of a property of the circuit elements of the mounting portion which is mold, and separating by dicing the insulating resin for each mounting portion.

【0021】本発明では、導電パターンを形成する導電箔がスタートの材料であり、絶縁性樹脂がモールドされるまでは導電箔が支持機能を有し、モールド後は絶縁性樹脂が支持機能を有することで支持基板を不要にでき、 In the present invention, the conductive foil to form the conductive pattern is a material of the start, until the insulating resin is molded has a conductive foil supporting function after molding the insulating resin has a supporting function can the support substrate required by,
従来の課題を解決することができる。 It is possible to solve the conventional problems. また本発明では、 In the present invention also,
モールド、測定およびダイシングをブロック毎にできるので、多数個の回路装置を量産でき、従来の課題を解決することができる。 Mold, since the measurement and dicing it in each block, can mass-produce a large number of circuit devices, it is possible to solve the conventional problems.

【0022】 [0022]

【発明の実施の形態】まず本発明の回路装置の製造方法について図1を参照しながら説明する。 Referring to FIG. 1 will be described a method for manufacturing the circuit device of the embodiment of the invention First invention.

【0023】本発明は、導電箔を用意し、少なくとも回路素子の搭載部を多数個形成する導電パターンを除く領域の前記導電箔に前記導電箔の厚みよりも浅い分離溝を形成して導電パターンを形成する工程と、所望の前記導電パターンの前記各搭載部に回路素子を固着する工程と、各搭載部の前記回路素子を一括して被覆し、前記分離溝に充填されるように絶縁性樹脂で共通モールドする工程と、前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、前記絶縁性樹脂で一括してモールドされた各搭載部の前記回路素子の特性の測定を行う工程と、前記絶縁性樹脂を各搭載部毎にダイシングにより分離する工程から構成されている。 [0023] The present invention is to provide a conductive foil, the conductive foil conductive pattern to form a shallow isolation trench than the thickness of the conductive foil regions except the conductive patterns to a large number forming a mounting portion of at least the circuit elements forming a desired a step of fixing the circuit elements to the each mounting portion of the conductive pattern, the coated collectively circuit elements of each mounting portion, the insulating so as to fill the isolation trench a step of common molded with resin, and removing the conductive foil having a thickness of a portion not provided the separation groove, the measurement of characteristics of the circuit elements of the mounting portion which is molded at once with the insulating resin and performing, and a step of separating by dicing the insulating resin for each mounting portion.

【0024】図1に示すフローは上述した工程とは一致していないが、Cu箔、Agメッキ、ハーフエッチングの3つのフローで導電パターンの形成が行われる。 The flow shown in FIG. 1 is not identical with the process described above, Cu foil, Ag plating, formation of the conductive pattern in three flows of half-etching is performed. ダイボンドおよびワイヤーボンディングの2つのフローで各搭載部への回路素子の固着と回路素子の電極と導電パターンの接続が行われる。 Connecting die bonding and electrode and the conductive pattern of the fixed and the circuit elements of the circuit element to the respective mounting portions in two flows of wire bonding is performed. トランスファーモールドのフローでは絶縁性樹脂による共通モールドが行われる。 In the flow of transfer molding is performed common mold by the insulating resin. 裏面Cu箔除去のフローでは分離溝のない厚み部分の導電箔のエッチングが行われる。 In the flow of the back surface Cu foil removal etching of the conductive foil having a thickness of parts without isolation trench is performed. 裏面処理のフローでは裏面に露出した導電パターンの電極処理が行われる。 In the flow of the backside treatment electrode process of the conductive pattern exposed on the back surface it is performed. 測定のフローでは各搭載部に組み込まれた回路素子の良品判別や特性ランク分けが行われる。 In the flow measurement good discrimination and characteristics ranking of the circuit elements incorporated in the mounting portion is performed. ダイシングのフローでは絶縁性樹脂からダイシングで個別の回路素子への分離が行われる。 In the dicing of the flow takes place is separated into individual circuit elements by the dicing the insulating resin.

【0025】以下に、本発明の各工程を図2〜図9を参照して説明する。 [0025] The following describes the steps of the present invention with reference to Figures 2-9.

【0026】本発明の第1の工程は、図2から図4に示すように、導電箔60を用意し、少なくとも回路素子5 The first step of the present invention, as shown in FIGS. 2-4, prepared conductive foil 60, at least the circuit elements 5
2の搭載部を多数個形成する導電パターン51を除く領域の導電箔60に導電箔60の厚みよりも浅い分離溝6 Shallow isolation trench 6 than the thickness of the conductive foil 60 to conductive foil 60 in the region excluding the conductive pattern 51 of a large number forms a second mounting section
1を形成して導電パターン51を形成することにある。 It is to form a conductive pattern 51 to form a 1.

【0027】本工程では、まず図2Aの如く、シート状の導電箔60を用意する。 [0027] In this step, first, as shown in FIG. 2A, is prepared a sheet-like conductive foil 60. この導電箔60は、ロウ材の付着性、ボンディング性、メッキ性が考慮されてその材料が選択され、材料としては、Cuを主材料とした導電箔、Alを主材料とした導電箔またはFe−Ni等の合金から成る導電箔等が採用される。 The conductive foil 60, adhesion of brazing material, bonding property, plating property is selected the material is considered that, as the material, a conductive foil of Cu as a main material, conductive foil or Fe in which the Al as a main material conductive foil made of an alloy such as -Ni is employed.

【0028】導電箔の厚さは、後のエッチングを考慮すると10μm〜300μm程度が好ましく、ここでは7 The thickness of the conductive foil is preferably about 10μm~300μm Considering later etching, here 7
0μm(2オンス)の銅箔を採用した。 It adopted the copper foil of 0μm (2 ounces) of. しかし300μ However 300μ
m以上でも10μm以下でも基本的には良い。 Even 10μm or less at more than m is basically good. 後述するように、導電箔60の厚みよりも浅い分離溝61が形成できればよい。 As described below, a shallow trench 61 may if formed than the thickness of the conductive foil 60.

【0029】尚、シート状の導電箔60は、所定の幅、 [0029] The sheet-like conductive foil 60 is a predetermined width,
例えば45mmでロール状に巻かれて用意され、これが後述する各工程に搬送されても良いし、所定の大きさにカットされた短冊状の導電箔60が用意され、後述する各工程に搬送されても良い。 For example it is prepared in a rolled at 45 mm, which may be carried to each process to be described later, the strip-like conductive foil 60 was cut into a predetermined size are prepared and are carried to each process described later and it may be.

【0030】具体的には、図2Bに示す如く、短冊状の導電箔60に多数の搭載部が形成されるブロック62が4〜5個離間して並べられる。 [0030] Specifically, as shown in Figure 2B, the block 62 a number of the mounting portion in a strip-like conductive foil 60 is formed are arranged four to five apart from. 各ブロック62間にはスリット63が設けられ、モールド工程等での加熱処理で発生する導電箔60の応力を吸収する。 Between each block 62 slit 63 is provided to absorb the stress of the conductive foil 60 generated by heat treatment in the molding process or the like. また導電箔60 The conductive foil 60
の上下周端にはインデックス孔64が一定の間隔で設けられ、各工程での位置決めに用いられる。 The upper and lower peripheral end index holes 64 are provided at regular intervals, used for positioning in each step.

【0031】続いて、導電パターンを形成する。 [0031] Subsequently, a conductive pattern.

【0032】まず、図3に示す如く、Cu箔60の上に、ホトレジスト(耐エッチングマスク)PRを形成し、導電パターン51となる領域を除いた導電箔60が露出するようにホトレジストPRをパターニングする。 [0032] First, as shown in FIG. 3, on the Cu foil 60, patterning the photoresist PR as photoresist to form a (anti-etching mask) PR, the conductive foil 60 excluding the region where the conductive pattern 51 is exposed to.
そして、図4Aに示す如く、ホトレジストPRを介して導電箔60を選択的にエッチングする。 Then, as shown in FIG. 4A, selectively etching the conductive foil 60 via the photoresist PR.

【0033】エッチングにより形成された分離溝61の深さは、例えば50μmであり、その側面は、粗面となるため絶縁性樹脂50との接着性が向上される。 The depth of the trench 61 formed by etching, for example, 50 [mu] m, its side, the adhesion between the insulating resin 50 to become a rough surface is improved.

【0034】またこの分離溝61の側壁は、模式的にストレートで図示しているが、除去方法により異なる構造となる。 Further the side wall of the trench 61, although illustrated in schematically straight, the different structures by removing method. この除去工程は、ウェットエッチング、ドライエッチング、レーザによる蒸発、ダイシングが採用できる。 This removal process, wet etching, dry etching, evaporation by laser, dicing can be employed. ウェットエッチングの場合、エッチャントは、塩化第二鉄または塩化第二銅が主に採用され、前記導電箔は、このエッチャントの中にディッピングされるか、このエッチャントでシャワーリングされる。 For wet etching, etchant, ferric or cupric chloride is mainly adopted chloride, the conductive foil is either dipped in this etchant is showered with this etchant. ここでウェットエッチングは、一般に非異方性にエッチングされるため、側面は湾曲構造になる。 Here the wet etching, since generally be etched in the non-anisotropic, side becomes curved structure.

【0035】またドライエッチングの場合は、異方性、 [0035] In the case of dry etching, anisotropic,
非異方性でエッチングが可能である。 In non-anisotropy can be etched. 現在では、Cuを反応性イオンエッチングで取り除くことは不可能といわれているが、スパッタリングで除去できる。 At present, it is said impossible to remove by reactive ion etching the Cu, it can be removed by sputtering. またスパッタリングの条件によって異方性、非異方性でエッチングできる。 The etching can be anisotropic, with the non-anisotropic by the sputtering conditions.

【0036】またレーザでは、直接レーザ光を当てて分離溝61を形成でき、この場合は、どちらかといえば分離溝61の側面はストレートに形成される。 [0036] In the laser can form a trench 61 by applying a direct laser beam, in this case, the side surface of the trench 61, if anything is formed straight.

【0037】なお、図3に於いて、ホトレジストの代わりにエッチング液に対して耐食性のある導電被膜(図示せず)を選択的に被覆しても良い。 [0037] Incidentally, in FIG. 3, (not shown) conductive coating with a corrosion resistance to the etching solution in place of the photoresist may be selectively coated. 導電路と成る部分に選択的に被着すれば、この導電被膜がエッチング保護膜となり、レジストを採用することなく分離溝をエッチングできる。 If selectively deposited on portions serving as the conductive path, can be etched isolation trenches without the conductive coating is serves as an etching protective film, employing a resist. この導電被膜として考えられる材料は、A Materials contemplated as the conductive coating, A
g、Ni、Au、PtまたはPd等である。 g, and Ni, Au, Pt or Pd, or the like. しかもこれら耐食性の導電被膜は、ダイパッド、ボンディングパッドとしてそのまま活用できる特徴を有する。 Moreover these corrosion-resistant conductive coating is characterized that it can be utilized the die pad, a bonding pad.

【0038】例えばAg被膜は、Auと接着するし、ロウ材とも接着する。 [0038] For example Ag coating to adhere and Au, bonding with the brazing material. よってチップ裏面にAu被膜が被覆されていれば、そのまま導電路51上のAg被膜にチップを熱圧着でき、また半田等のロウ材を介してチップを固着できる。 Therefore if Au film is coated on the back surface of the chip, as the chip can thermocompression bonding the Ag film on the conductive path 51, also the chip can be fixed via the brazing material such as solder. またAgの導電被膜にはAu細線が接着できるため、ワイヤーボンディングも可能となる。 Also since it adhesion Au thin wire in the conductive coating of Ag, it becomes possible wire bonding. 従ってこれらの導電被膜をそのままダイパッド、ボンディングパッドとして活用できるメリットを有する。 Thus an advantage that can take advantage of these conductive coating as a die pad, a bonding pad.

【0039】図4Bに具体的な導電パターン51を示す。 [0039] Figure 4B shows the specific conductive pattern 51. 本図は図2Bで示したブロック62の1個を拡大したもの対応する。 This figure corresponds to those that have been enlarged one block 62 shown in Figure 2B. 黒く塗られた部分の1個が1つの搭載部65であり、導電パターン51を構成し、1つのブロック62には5行10列のマトリックス状に多数の搭載部65が配列され、各搭載部65毎に同一の導電パターン51が設けられている。 One blackened portion is a one of the mounting portion 65 constitutes a conductive pattern 51, a number of mounting portions 65 are arranged in a matrix of 5 rows and 10 columns in one block 62, the mounting portion same conductive pattern 51 is provided for each 65. 各ブロックの周辺には枠状のパターン66が設けられ、それと少し離間してその内側にダイシング時の位置合わせマーク67が設けられている。 The periphery of each block is provided frame-like pattern 66, the same alignment mark 67 at the time of dicing the inside a little apart are provided. 枠状のパターン66はモールド金型との嵌合に使用され、また導電箔60の裏面エッチング後には絶縁性樹脂50の補強をする働きを有する。 Frame-like pattern 66 is used for the fitting of the mold, also after back surface etching of the conductive foil 60 has a function of reinforcing the insulating resin 50.

【0040】本発明の第2の工程は、図5に示す如く、 The second step of the present invention, as shown in FIG. 5,
所望の導電パターン51の各搭載部65に回路素子52 Circuit element 52 in the respective mounting portion 65 of the desired conductive pattern 51
を固着し、各搭載部65の回路素子52の電極と所望の導電パターン51とを電気的に接続する接続手段を形成することにある。 The fixed is to the the electrode of the circuit element 52 of the mounting portion 65 and the desired conductive pattern 51 forms a connection means for electrically connecting.

【0041】回路素子52としては、トランジスタ、ダイオード、ICチップ等の半導体素子、チップコンデンサ、チップ抵抗等の受動素子である。 [0041] As the circuit element 52, a transistor, a diode, a semiconductor device such as an IC chip, chip capacitors, a passive element chip resistor or the like. また厚みが厚くはなるが、CSP、BGA等のフェイスダウンの半導体素子も実装できる。 The thicker the thickness is, but may CSP, also semiconductor elements face-down such as a BGA mounting.

【0042】ここでは、ベアのトランジスタチップ52 [0042] Here, the bare transistor chip 52
Aが導電パターン51Aにダイボンディングされ、エミッタ電極と導電パターン51B、ベース電極と導電パターン51Bが、熱圧着によるボールボンディングあるいは超音波によるウェッヂボンディング等で固着された金属細線55Aを介して接続される。 A is die-bonded to the conductive pattern 51A, an emitter electrode and the conductive pattern 51B, the base electrode and the conductive pattern 51B is connected via a thin metal wire 55A that is fixed in the wedge bonding or the like by the ball bonding or ultrasonic waves by thermocompression . また52Bは、チップコンデンサまたは受動素子であり、半田等のロウ材または導電ペースト55Bで固着される。 Further 52B is a chip capacitor or the passive element, is fixed by the brazing material or the conductive paste 55B such as solder.

【0043】本工程では、各ブロック62に多数の導電パターン51が集積されているので、回路素子52の固着およびワイヤーボンディングが極めて効率的に行える利点がある。 [0043] In this step, since the number of conductive patterns 51 in each block 62 are integrated, there is the advantage that anchoring and wire bonding of the circuit element 52 can be performed very efficiently.

【0044】本発明の第3の工程は、図6に示す如く、 The third step of the present invention, as shown in FIG. 6,
各搭載部63の回路素子52を一括して被覆し、分離溝61に充填されるように絶縁性樹脂50で共通モールドすることにある。 Coated collectively circuit elements 52 of each mounting portion 63 is to the common mold with the insulating resin 50 so as to fill the trench 61.

【0045】本工程では、図6Aに示すように、絶縁性樹脂50は回路素子52A、52Bおよび複数の導電パターン51A、51B、51Cを完全に被覆し、導電パターン51間の分離溝61には絶縁性樹脂50が充填されてた導電パターン51A、51B、51Cの側面の湾曲構造と嵌合して強固に結合する。 [0045] In this step, as shown in FIG. 6A, the insulating resin 50 is the circuit elements 52A, 52B and a plurality of conductive patterns 51A, 51B, 51C and completely cover the, the trench 61 between the conductive pattern 51 the insulating resin 50 is filled has conductive patterns 51A, 51B, fitted with a curved structure of the side surface of the 51C firmly bonded. そして絶縁性樹脂5 The insulating resin 5
0により導電パターン51が支持されている。 Conductive pattern 51 is supported by the 0.

【0046】また本工程では、トランスファーモールド、インジェクションモールド、またはディッピングにより実現できる。 [0046] In this step can also be realized by transfer molding, injection molding or dipping. 樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。 As the resin material, thermosetting resin such as epoxy resin can be realized by transfer molding, a polyimide resin, a thermoplastic resin such as polyphenylene sulfide can be realized by injection molding.

【0047】更に、本工程でトランスファーモールドあるいはインジェクションモールドする際に、図6Bに示すように各ブロック62は1つの共通のモールド金型に搭載部63を納め、各ブロック毎に1つの絶縁性樹脂5 [0047] Further, when the transfer molding or injection molding in this step, the block 62 as shown in FIG. 6B pay mounting portion 63 into one common mold, one insulating resin for each block 5
0で共通にモールドを行う。 Carry out the mold in common with 0. このために従来のトランスファーモールド等の様に各搭載部を個別にモールドする方法に比べて、大幅な樹脂量の削減が図れる。 Compared to a method of molding individually each mounting portion as such conventional transfer molding for this, thereby the significant reduction of the amount of resin.

【0048】導電箔60表面に被覆された絶縁性樹脂5 The conductive foil 60 insulating resin is coated on the surface 5
0の厚さは、回路素子52のボンディングワイヤー55 The thickness of 0, a bonding wire 55 of the circuit element 52
Aの最頂部から約100μm程度が被覆されるように調整されている。 About 100μm order of the highest portion of A is adjusted so as to be covered. この厚みは、強度を考慮して厚くすることも、薄くすることも可能である。 This thickness, also, it is possible to thin to thick in consideration of strength.

【0049】本工程の特徴は、絶縁性樹脂50を被覆するまでは、導電パターン51となる導電箔60が支持基板となることである。 [0049] The present process features, until covering the insulating resin 50, the conductive foil 60 serving as the conductive pattern 51 is to be a supporting substrate. 従来では、図12の様に、本来必要としない支持基板5を採用して導電路7〜11を形成しているが、本発明では、支持基板となる導電箔60 Conventionally, as in FIG. 12, to form a conductive path 7-11 employs a support substrate 5 which is not originally required, in the present invention, the conductive foil 60 serving as a support substrate
は、電極材料として必要な材料である。 Is a material required as an electrode material. そのため、構成材料を極力省いて作業できるメリットを有し、コストの低下も実現できる。 Therefore, it has a merit of work by omitting the constituent material as much as possible, reduction of cost can be realized.

【0050】また分離溝61は、導電箔の厚みよりも浅く形成されているため、導電箔60が導電パターン51 [0050] The trench 61, because they are shallower than the thickness of the conductive foil, the conductive foil 60 is a conductive pattern 51
として個々に分離されていない。 Not separated individually as. 従ってシート状の導電箔60として一体で取り扱え、絶縁性樹脂50をモールドする際、金型への搬送、金型への実装の作業が非常に楽になる特徴を有する。 Therefore handled integrally as a sheet-like conductive foil 60, when molding the insulating resin 50, having the features conveying into the mold, the implementation of the work to the mold becomes very easy.

【0051】本発明の第4の工程は、図6に示す如く、 The fourth step of the present invention, as shown in FIG. 6,
分離溝61を設けていない厚み部分の導電箔60を除去することにある。 It is to remove the conductive foil 60 of a thickness portion not provided with the separation groove 61.

【0052】本工程は、導電箔60の裏面を化学的および/または物理的に除き、導電パターン51として分離するものである。 [0052] In this step, chemical and / or physical except the back surface of the conductive foil 60 is for separating as the conductive pattern 51. この工程は、研磨、研削、エッチング、レーザの金属蒸発等により施される。 This process, polishing, grinding, etching, is performed by laser metal evaporation or the like.

【0053】実験では研磨装置または研削装置により全面を30μm程度削り、分離溝61から絶縁性樹脂50 [0053] shaved about 30μm entirely by the polishing apparatus or grinding apparatus in the experiment, isolated from the trench 61 resin 50
を露出させている。 It is exposed to. この露出される面を図6では点線で示している。 It shows this exposed the surface by dotted lines in FIG. 6. その結果、約40μmの厚さの導電パターン51となって分離される。 As a result, it is separated a conductive pattern 51 having a thickness of about 40 [mu] m. また、絶縁性樹脂50が露出する手前まで、導電箔60を全面ウェトエッチングし、その後、研磨または研削装置により全面を削り、絶縁性樹脂50を露出させても良い。 Also, until just before the insulating resin 50 is exposed, the entire surface web preparative etched conductive foil 60, then scraping the entire surface by a polishing or grinding apparatus may expose the insulating resin 50. 更に、導電箔60を点線で示す位置まで全面ウェトエッチングし、絶縁性樹脂50を露出させても良い。 Furthermore, entirely web preparative etching to a position that indicates the conductive foil 60 by a dotted line, may be exposed to the insulating resin 50.

【0054】この結果、絶縁性樹脂50に導電パターン51の裏面が露出する構造となる。 [0054] As a result, a structure in which the back surface is exposed in the conductive pattern 51 on the insulating resin 50. すなわち、分離溝6 That is, the separation groove 6
1に充填された絶縁性樹脂50の表面と導電パターン5 Filled insulating resin 50 of the surface 1 and the conductive pattern 5
1の表面は、実質的に一致する構造となっている。 1 surface has a substantially matching configuration. 従って、本発明の回路装置53は図11に示した従来の裏面電極10、11のように段差が設けられないため、マウント時に半田等の表面張力でそのまま水平に移動してセルフアラインできる特徴を有する。 Accordingly, the circuit device 53 of the present invention, since a step like the conventional back surface electrodes 10 and 11 shown in FIG. 11 is not provided, a feature that can be self-aligned by moving it horizontally by surface tension of the solder when mounting a.

【0055】更に、導電パターン51の裏面処理を行い、図7に示す最終構造を得る。 [0055] Further, it performs rear surface treatment of the conductive pattern 51, a final structure shown in FIG. すなわち、必要によって露出した導電パターン51に半田等の導電材を被着し、回路装置として完成する。 That is, depositing a conductive material such as solder to a conductive pattern 51 exposed by the need to complete the circuit device.

【0056】本発明の第5の工程は、図8に示す如く、 [0056] The fifth step of the present invention, as shown in FIG. 8,
絶縁性樹脂50で一括してモールドされた各搭載部63 Each mounting portion 63 which is molded at once with the insulating resin 50
の回路素子52の特性の測定を行うことにある。 In carrying out the measurement of the characteristics of the circuit elements 52.

【0057】前工程で導電箔60の裏面エッチングをした後に、導電箔60から各ブロック62が切り離される。 [0057] After the back surface etching of the conductive foil 60 in the previous step, each block 62 is separated from the conductive foil 60. このブロック62は絶縁性樹脂50で導電箔60の残余部と連結されているので、切断金型を用いず機械的に導電箔60の残余部から剥がすことで達成できる。 This block 62 is connected to the remainder of the conductive foil 60 with the insulating resin 50 can be accomplished by peeling from the remainder of the mechanically conductive foil 60 without using a cutting die.

【0058】各ブロック62の裏面には図8に示すように導電パターン51の裏面が露出されており、各搭載部65が導電パターン51形成時と全く同一にマトリックス状に配列されている。 [0058] are arranged in a matrix identical back surface is the back surface of the conductive pattern 51 is exposed, as shown in FIG. 8, at the time of each mounting portion 65 is a conductive pattern 51 formed in each block 62. この導電パターン51の絶縁性樹脂50から露出した裏面電極56にプローブ68を当てて、各搭載部65の回路素子52の特性パラメータ等を個別に測定して良不良の判定を行い、不良品には磁気インク等でマーキングを行う。 The back electrode 56 exposed from the insulating resin 50 of the conductive pattern 51 by applying a probe 68, a characteristic parameter of the circuit element 52 of each mounting portion 65 makes a determination of individually yo measured defective, the defective to mark with magnetic ink or the like.

【0059】本工程では、各搭載部65の回路装置53 [0059] In this step, the circuit device 53 of the respective mounting portions 65
は絶縁性樹脂50でブロック62毎に一体で支持されているので、個別にバラバラに分離されていない。 Since is supported integrally for each block 62 with the insulating resin 50, not separated into pieces individually. 従って、テスターの載置台に置かれたブロック62は搭載部65のサイズ分だけ矢印のように縦方向および横方向にピッチ送りをすることで、極めて早く大量にブロック6 Thus, block 62 placed on the stage of the tester by the longitudinal and transverse directions in pitch feed as indicated by the arrow by the size of the mounting portion 65, a large amount very quickly block 6
2の各搭載部65の回路装置53の測定を行える。 Perform the measurement of the second circuit device 53 of the mounting portion 65. すなわち、従来必要であった回路装置の表裏の判別、電極の位置の認識等が不要にできるので、測定時間の大幅な短縮を図れる。 That is, discrimination of the front and back of the conventionally required circuit arrangement, since the recognition or the like of the position of the electrodes can be eliminated, thereby significantly shortening the measurement time.

【0060】本発明の第6の工程は、図9に示す如く、 [0060] The sixth step of the present invention, as shown in FIG. 9,
絶縁性樹脂50を各搭載部65毎にダイシングにより分離することにある。 It is to separate by dicing the insulating resin 50 in each mounting portion 65.

【0061】本工程では、ブロック62をダイシング装置の載置台に真空で吸着させ、ダイシングブレード69 [0061] In this step, adsorbed in vacuo block 62 on the mounting table of the dicing apparatus, the dicing blade 69
で各搭載部65間のダイシングライン70に沿って分離溝61の絶縁性樹脂50をダイシングし、個別の回路装置53に分離する。 In diced insulating resin 50 of the trench 61 along the dicing line 70 between the mounting portion 65, separated into individual circuit devices 53.

【0062】本工程で、ダイシングブレード69はほぼ絶縁性樹脂50を切断する切削深さで行い、ダイシング装置からブロック62を取り出した後にローラでチョコレートブレークするとよい。 [0062] In this step, performed by the cutting depth of cutting the dicing blade 69 is substantially insulating resin 50, may be chocolate break roller after removal of the block 62 from the dicing device. あるいはダイシングブレード69は完全に絶縁性樹脂50を切断する切削深さで行い、載置台から直接吸着コレットでテーピングをしても良い。 Alternatively dicing blade 69 is carried by the cutting depth of cutting completely insulating resin 50 may be taping directly suction collet from the table.

【0063】なお、ダイシング時は予め前述した第1の工程で設けた各ブロックの周辺の枠状のパターン66の内側に設けた相対向する位置合わせマーク67を認識して、これを基準としてダイシングを行う。 [0063] Incidentally, during dicing recognizes the first alignment marks 67 which faces provided on the inside of the frame-like pattern 66 of the periphery of each block disposed in the step of pre-above, dicing this as reference I do. 周知ではあるが、ダイシングは縦方向にすべてのダイシングライン7 Albeit well known, all dicing lines dicing longitudinally 7
0をダイシングをした後、載置台を90度回転させて横方向のダイシングライン70に従ってダイシングを行う。 0 After the dicing, dicing is performed according to the lateral direction of the dicing line 70 by rotating the mounting table 90 degrees.

【0064】 [0064]

【発明の効果】本発明では、導電パターンの材料となる導電箔自体を支持基板として機能させ、分離溝の形成時あるいは回路素子の実装、絶縁性樹脂の被着時までは導電箔で全体を支持し、また導電箔を各導電パターンとして分離する時は、絶縁性樹脂を支持基板にして機能させている。 In the present invention, the conductive foil itself serving as the material of the conductive patterns to function as a supporting substrate, mounting the formation or at a circuit element separation groove, the whole until the deposition of the insulating resin with a conductive foil supporting, also when separating conductive foil as the conductive patterns is made to function with the insulating resin to a supporting substrate. 従って、回路素子、導電箔、絶縁性樹脂の必要最小限で製造できる。 Accordingly, circuit elements, conductive foil, can be manufactured by necessary minimum of the insulating resin. 従来例で説明した如く、本来回路装置を構成する上で支持基板が要らなくなり、コスト的にも安価にできる。 As described in the conventional example, the supporting substrate no longer needed in constructing the original circuit device can be cheaper in cost. また支持基板が不要であること、導電パターンが絶縁性樹脂に埋め込まれていること、更には絶縁性樹脂と導電箔の厚みの調整が可能であることにより、非常に薄い回路装置が形成できるメリットもある。 It is also supporting substrate is not required, that the conductive pattern is buried in the insulating resin, merits further by it is possible to adjust the thickness of the insulating resin and the conductive foil, it can form a very thin circuit device there is also.

【0065】次に、本発明では絶縁性樹脂のモールド工程でブロック毎の共通モールドを行うことにより大幅な樹脂量の削減が図れる 更に、測定工程およびダイシング工程でブロック毎に処理を行える利点を有する。 Next, the present invention has the advantage of enabling the processing for each block further attained the significant reduction of the amount of resin by performing a common mold for each block in the molding process of the insulating resin, the measuring step and the dicing step . 従って、測定工程では極めて早く大量にブロックの各搭載部の回路装置の測定を行え、従来必要であった回路装置の表裏の判別、電極の位置の認識等が不要にできるので、測定時間の大幅な短縮を図れる。 Thus, performing the measurement of the circuit arrangement of the mounting portion of the very fast mass blocked the measuring step, the determination of the front and back of the conventionally required circuit arrangement, since the recognition or the like of the position of the electrodes can be eliminated, the measurement time greatly attained the Do not shortened. またダイシング工程では位置合わせマークを用いてダイシングラインの認識が早く確実に行われる利点を有する。 In the dicing step has the advantage that recognition of the dicing line is quickly ensured with the alignment mark. 更にダイシングは絶縁性樹脂層のみの切断でよく、導電箔を切断しないことによりダイシングブレードの寿命も長くでき、導電箔を切断する場合に発生する金属バリの発生もない。 Further dicing may be a cut of only the insulating resin layer, the life of the dicing blade by not cutting the conductive foil can also be longer, there is no occurrence of metal burrs occurring when cutting conductive foil. 更にまたダイシングシートを用いないので、ダイシングシートへのブロックの貼り付け作業や剥離作業も不要となる。 Further, since no or using a dicing sheet, becomes unnecessary pasting and peeling operation of the block to the dicing sheet.

【0066】また図13から明白なように、スルーホールの形成工程、導体の印刷工程(セラミック基板の場合)等を省略できるので、従来より従来より製造工程を大幅に短縮でき、全行程を内作できる利点を有する。 [0066] As is also evident from FIG. 13, steps of forming the through hole, it is possible to omit such conductor printing process (for ceramic substrates), can significantly reduce the hitherto manufacturing process conventionally inner all the way It has the advantage of being able to work. またフレーム金型も一切不要であり、極めて短納期となる製造方法である。 The frame mold is also no unnecessary, is a manufacturing method which is a very short delivery time.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の製造フローを説明する図である。 1 is a diagram illustrating a production flow of the present invention.

【図2】本発明の回路装置の製造方法を説明する図である。 Is a diagram for explaining a manufacturing method of the circuit device of the present invention; FIG.

【図3】本発明の回路装置の製造方法を説明する図である。 3 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図4】本発明の回路装置の製造方法を説明する図である。 Is a diagram for explaining a manufacturing method of the circuit device of the present invention; FIG.

【図5】本発明の回路装置の製造方法を説明する図である。 5 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図6】本発明の回路装置の製造方法を説明する図である。 6 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図7】本発明の回路装置の製造方法を説明する図である。 7 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図8】本発明の回路装置の製造方法を説明する図である。 8 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図9】本発明の回路装置の製造方法を説明する図である。 9 is a diagram for explaining a manufacturing method of the circuit device of the present invention.

【図10】従来の回路装置の実装構造を説明する図である。 10 is a diagram illustrating a mounting structure of a conventional circuit device.

【図11】従来の回路装置を説明する図である。 11 is a diagram for explaining the conventional circuit device.

【図12】従来の回路装置の製造方法を説明する図である。 12 is a diagram for explaining a conventional method of manufacturing a circuit device.

【図13】従来の回路装置の製造方法を説明する図である。 13 is a diagram for explaining a conventional method of manufacturing a circuit device.

【符号の説明】 DESCRIPTION OF SYMBOLS

50 絶縁性樹脂 51 導電パターン 52 回路素子 53 回路装置 61 分離溝 62 ブロック 50 insulating resin 51 conductive pattern 52 circuit element 53 circuit device 61 separation groove 62 block

───────────────────────────────────────────────────── フロントページの続き (72)発明者 阪本 純次 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 岡田 幸夫 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 五十嵐 優助 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 前原 栄寿 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 高橋 幸嗣 群馬県伊勢崎市喜多町29番地 関東三洋電 子株式会社内 Fターム(参考) 5F061 AA01 BA01 BA03 CA21 DD12 DD13 FA02 5F067 AA01 AB00 AB04 DA16 DE01 ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Jun Sakamoto next Osaka Prefecture Moriguchi Keihanhondori 2-chome No. 5 No. 5 Sanyo within Co., Ltd. (72) inventor Yukio Okada Osaka Prefecture Moriguchi Keihanhondori 2-chome 5 Ban No. 5 Sanyo within Co., Ltd. (72) inventor Igarashi Yusuke Osaka Prefecture Moriguchi Keihanhondori 2-chome No. 5 No. 5 Sanyo within Co., Ltd. (72) inventor Eiju Maehara Osaka Prefecture Moriguchi Keihanhondori 2 chome No. 5 No. 5 Sanyo within Co., Ltd. (72) inventor Koji Takahashi Isesaki, Gunma Prefecture Kita-cho, 29 address Kanto Sanyo electronic Co., Ltd. in the F-term (reference) 5F061 AA01 BA01 BA03 CA21 DD12 DD13 FA02 5F067 AA01 AB00 AB04 DA16 DE01

Claims (19)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 導電箔を用意し、少なくとも回路素子の搭載部を多数個形成する導電パターンを除く領域の前記導電箔に前記導電箔の厚みよりも浅い分離溝を形成して導電パターンを形成する工程と、 所望の前記導電パターンの前記各搭載部に回路素子を固着する工程と、 各搭載部の前記回路素子を一括して被覆し、前記分離溝に充填されるように絶縁性樹脂で共通モールドする工程と、 前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、 前記絶縁性樹脂で一括してモールドされた各搭載部の前記回路素子の特性の測定を行う工程と、 前記絶縁性樹脂を各搭載部毎にダイシングにより分離する工程とを具備することを特徴とする回路装置の製造方法。 1. A prepared conductive foil, forming the conductive foil conductive pattern to form a shallow isolation trench than the thickness of the conductive foil regions except the conductive patterns to a large number forming a mounting portion of at least the circuit elements step and a step of fixing the circuit element to the respective mounting portions of the desired of the conductive pattern, and coated collectively the circuit elements of the mounting portion, an insulating resin to be filled in the separation grooves step of carrying out the steps of a common mold, and removing the conductive foil having a thickness of a portion not provided the separation groove, the measurement of characteristics of the circuit elements of the mounting portion which is molded at once with the insulating resin When manufacturing method of the circuit device characterized by comprising the step of separating by dicing the insulating resin for each mounting portion.
  2. 【請求項2】 導電箔を用意し、少なくとも回路素子の搭載部を多数個形成する導電パターンを除く領域の前記導電箔に前記導電箔の厚みよりも浅い分離溝を形成して導電パターンを形成する工程と、 所望の前記導電パターンの前記各搭載部に回路素子を固着する工程と、 前記各搭載部の回路素子の電極と所望の前記導電パターンとを電気的に接続する接続手段を形成する工程と 各搭載部の前記回路素子を一括して被覆し、前記分離溝に充填されるように絶縁性樹脂で共通モールドする工程と、 前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、 前記絶縁性樹脂で一括してモールドされた各搭載部の前記回路素子の特性の測定を行う工程と、 前記絶縁性樹脂を各搭載部毎にダイシングにより分離する工程とを具備すること 2. A prepared conductive foil, forming the conductive foil conductive pattern to form a shallow isolation trench than the thickness of the conductive foil regions except the conductive patterns to a large number forming a mounting portion of at least the circuit elements forming a step of a step of fixing the circuit element to the respective mounting portions of the desired of the conductive pattern, a connection means for electrically connecting said the electrode of the circuit element of each mounting portion and the desired the conductive pattern process and to the covering collectively circuit elements of each mounting portion, said a step of common molded with an insulating resin so as to fill the isolation trenches, removing the conductive foil having a thickness of a portion not provided the isolation trench comprising the steps, a step for measuring the characteristics of the circuit elements of the mounting portion which is molded at once with the insulating resin, and separating by dicing the insulating resin for each mounting unit for about を特徴とする回路装置の製造方法。 Method of manufacturing a circuit device according to claim.
  3. 【請求項3】 前記導電箔は銅、アルミニウム、鉄−ニッケルのいずれかで構成されることを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 Wherein said conductive foil is a copper, aluminum, iron - method of manufacturing has been the circuit device according to claim 1 or claim 2, characterized in that it is constituted by any one of nickel.
  4. 【請求項4】 前記導電箔の表面を導電皮膜で少なくとも部分的に被覆することを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 4. The process for producing the a circuit device according to claim 1 or claim 2, characterized in that at least partially covers the surface of the conductive foil with a conductive coating.
  5. 【請求項5】 前記導電被膜はニッケル、金あるいは銀メッキ形成されることを特徴とする請求項4に記載された回路装置の製造方法。 5. The method of manufacturing has been the circuit device according to claim 4, wherein the conductive coating is formed of nickel, gold or silver plated.
  6. 【請求項6】 前記導電箔に選択的に形成される前記分離溝は化学的あるいは物理的エッチングにより形成されることを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 6. The method of manufacturing has been the circuit device according to claim 1 or claim 2, wherein the separation groove is selectively formed on the conductive foil is formed by chemical or physical etching .
  7. 【請求項7】 前記回路素子は半導体ベアチップ、チップ回路部品のいずれかあるいは両方を固着されることを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 Wherein said circuit element is a semiconductor bare chip, a manufacturing method of the a circuit device according to claim 1 or claim 2, characterized in that it is secured to either or both of the chip circuit component.
  8. 【請求項8】 前記接続手段はワイヤーボンディングで形成されることを特徴とする請求項2に記載された回路装置の製造方法。 8. The method for producing the connection means is a circuit device according to claim 2, characterized in that it is formed by wire bonding.
  9. 【請求項9】 前記絶縁性樹脂はトランスファーモールドで付着されることを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 Wherein said insulating resin production method of the a circuit device according to claim 1 or claim 2, characterized in that it is deposited by transfer molding.
  10. 【請求項10】 前記導電箔には少なくとも回路素子の搭載部を多数個形成する導電パターンをマトリックス状に配列したブロックを複数個並べたことを特徴とする請求項1または請求項2に記載された回路装置の製造方法。 The method according to claim 10 wherein said conductive foil is described conductive patterns plurality forming a mounting portion of at least the circuit elements to claim 1 or claim 2, characterized in that arranged a plurality of blocks arranged in a matrix manufacturing method of the circuit device.
  11. 【請求項11】 前記絶縁性樹脂は前記ブロック毎にトランスファーモールドで付着されることを特徴とする請求項10に記載された回路装置の製造方法。 11. The method for producing the a circuit device according to claim 10 wherein the insulating resin is characterized in that it is deposited in transfer molding for each of the blocks.
  12. 【請求項12】 前記絶縁性樹脂でモールドされた前記各ブロックは前記分離溝を設けていない厚み部分の前記導電箔を除去する工程の後に前記導電箔の残余部から分離されることを特徴とする請求項10に記載された回路装置の製造方法。 12. The method of claim 11, wherein each block is molded in the insulating resin and characterized in that it is separated from the remaining portion of the conductive foil after the step of removing the conductive foil having a thickness of a portion not provided the isolation trench method of manufacturing has been the circuit device according to claim 10.
  13. 【請求項13】 前記絶縁性樹脂でモールドされた前記各ブロック毎に各搭載部の前記回路素子の特性の測定を行うことを特徴とする請求項10に記載された回路装置の製造方法。 13. The method of to the circuit device according to claim 10, characterized in that for measuring the characteristics of the circuit elements of the mounting part for each of the said molded with an insulating resin blocks.
  14. 【請求項14】 前記絶縁性樹脂でモールドされた前記各ブロック毎に各搭載部にダイシングにより分離することを特徴とする請求項10に記載された回路装置の製造方法。 14. The method of to the circuit device according to claim 10, characterized in that the separation by dicing the respective mounting portions in said molded each block with an insulating resin.
  15. 【請求項15】 前記導電パターンと一緒に形成した合わせマークを用いてダイシングを行うことを特徴とする請求項14に記載された回路装置の製造方法。 15. The method of to the circuit device according to claim 14, wherein the performing dicing by using the alignment mark formed with the conductive pattern.
  16. 【請求項16】 前記導電パターンと一緒に形成した対向する合わせマークを用いてダイシングを行うことを特徴とする請求項14に記載された回路装置の製造方法。 16. The method of manufacturing has been the circuit device according to claim 14, wherein the performing dicing by using the alignment mark facing formed with the conductive pattern.
  17. 【請求項17】 前記絶縁性樹脂でモールドされた前記各ブロックは載置台に真空で吸着してダイシングを行うことを特徴とする請求項14に記載された回路装置の製造方法。 17. The method is a circuit device according to claim 14, characterized in that dicing adsorbed by vacuum to said each block is molded with an insulating resin worktable.
  18. 【請求項18】 前記絶縁性樹脂のダイシング時の切削深さをほぼ前記絶縁性樹脂の厚みとし、その後機械的に割って独立した回路装置に分離することを特徴とする請求項17に記載された回路装置の製造方法。 18. a thickness of approximately the insulating resin cutting depth during dicing of the insulating resin, and subsequently according to claim 17, characterized in that the separation into independent circuit device by dividing the mechanical manufacturing method of the circuit device.
  19. 【請求項19】 前記絶縁性樹脂のダイシング時の切削深さを完全に前記絶縁性樹脂の厚み以上とし、ダイシング時に独立した回路装置に分離することを特徴とする請求項17に記載された回路装置の製造方法。 19. and the cutting depth during dicing the insulating resin completely the above thickness of the insulating resin, the circuit of claim 17, characterized in that the separation into independent circuit device during dicing manufacturing method of the device.
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US6972477B2 (en) 2002-12-20 2005-12-06 Sanyo Electric Co., Ltd. Circuit device with conductive patterns separated by insulating resin-filled grooves
US7105384B2 (en) 2002-12-04 2006-09-12 Sanyo Electric Co., Ltd Circuit device manufacturing method including mounting circuit elements on a conductive foil, forming separation grooves in the foil, and etching the rear of the foil
US7420266B2 (en) 2003-09-30 2008-09-02 Sanyo Electric Co., Ltd. Circuit device and manufacturing method thereof
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US8236612B2 (en) 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7622332B2 (en) 2002-04-29 2009-11-24 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7790500B2 (en) 2002-04-29 2010-09-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7799611B2 (en) 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7439097B2 (en) 2002-09-25 2008-10-21 Unisem (Mauritius) Holdings Limited Taped lead frames and methods of making and using the same in semiconductor packaging
US6953712B2 (en) 2002-12-04 2005-10-11 Sanyo Electric Co., Ltd. Circuit device manufacturing method
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US7105384B2 (en) 2002-12-04 2006-09-12 Sanyo Electric Co., Ltd Circuit device manufacturing method including mounting circuit elements on a conductive foil, forming separation grooves in the foil, and etching the rear of the foil
US7364941B2 (en) 2002-12-04 2008-04-29 Sanyo Electric Co., Ltd. Circuit device manufacturing method
US6972477B2 (en) 2002-12-20 2005-12-06 Sanyo Electric Co., Ltd. Circuit device with conductive patterns separated by insulating resin-filled grooves
US7420266B2 (en) 2003-09-30 2008-09-02 Sanyo Electric Co., Ltd. Circuit device and manufacturing method thereof
US7476972B2 (en) 2004-05-20 2009-01-13 Sanyo Electric Co., Ltd. Circuit device, manufacturing method thereof, and sheet-like board member
TWI397964B (en) * 2011-01-19 2013-06-01 Unisem Mauritius Holdings Ltd Partially patterned lead frames and methods of making and using the same in semiconductor packaging
WO2017104300A1 (en) * 2015-12-16 2017-06-22 オムロン株式会社 Electronic device and manufacturing method therefor
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