JP2002075877A - Method and device for forming polycrystalline semiconductor thin film, and solar cell using polycrystalline semiconductor thin film - Google Patents

Method and device for forming polycrystalline semiconductor thin film, and solar cell using polycrystalline semiconductor thin film

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Publication number
JP2002075877A
JP2002075877A JP2000261642A JP2000261642A JP2002075877A JP 2002075877 A JP2002075877 A JP 2002075877A JP 2000261642 A JP2000261642 A JP 2000261642A JP 2000261642 A JP2000261642 A JP 2000261642A JP 2002075877 A JP2002075877 A JP 2002075877A
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JP
Japan
Prior art keywords
film
thin film
semiconductor
forming
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000261642A
Other languages
Japanese (ja)
Inventor
Manabu Komota
学 古茂田
Hideki Matsumura
英樹 松村
Atsushi Masuda
淳 増田
Koji Kamezaki
浩司 亀崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
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Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000261642A priority Critical patent/JP2002075877A/en
Publication of JP2002075877A publication Critical patent/JP2002075877A/en
Pending legal-status Critical Current

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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells

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  • Photovoltaic Devices (AREA)
  • Catalysts (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem in the conventional technique where process costs increase in the plasma CVD method using such special high-pressure gas as SiH4, the crystal particle diameter of Si film is small, light trapping is not sufficient, and the area of a semiconductor film to be formed cannot be increased easily. SOLUTION: A substrate for forming a semiconductor film is arranged in a chamber for introducing an etching gas, at the same time a solid-like semiconductor material is provided, further a heating catalyst body for activating the etching gas to be introduced into the chamber is provided, the etching gas is brought into contact with the heating catalyst body for activation, then the activated etching gas is allowed to collide with the solid-like semiconductor to form a volatile compound, and the volatile compound is transported to the surface of the substrate to form the semiconductor thin film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する分野】本発明は、多結晶半導体薄膜の形
成方法およびその形成装置およびその多結晶半導体薄膜
を用いた太陽電池に関する。
The present invention relates to a method and an apparatus for forming a polycrystalline semiconductor thin film and a solar cell using the polycrystalline semiconductor thin film.

【0002】[0002]

【従来技術とその課題】近年、低コスト化と高変換効率
化とを両立する次世代太陽電池の研究開発が活発に進め
られている。とりわけSiを主材料とした薄膜多結晶S
i太陽電池は、コスト、変換効率、資源問題、環境問題
等を総合的に考慮した上で、次世代太陽電池として最も
有力であると考えられている。
2. Description of the Related Art In recent years, research and development of next-generation solar cells that achieve both low cost and high conversion efficiency have been actively promoted. In particular, thin-film polycrystalline S mainly composed of Si
An i-solar cell is considered to be the most promising next-generation solar cell after comprehensively considering costs, conversion efficiency, resource issues, environmental issues, and the like.

【0003】この薄膜多結晶Si太陽電池において、低
コスト化を図るためには、材料費や設備費等のコストダ
ウンが要求されるが、現在、太陽電池用Si薄膜の形成
方法として主流であるSiH4、Si26、SiHxCl
y等といった特殊高圧ガスをプロセスガスとして用いた
プラズマCVD法等においては、ガスの製造、運搬、管
理、排ガス処理など、多岐の段階において厳重な対応処
理が要求されるため、結果としてプロセスコストを増大
させる要因となっている。
In this thin-film polycrystalline Si solar cell, cost reduction such as material cost and equipment cost is required in order to reduce the cost, but it is currently the mainstream method of forming a Si thin film for a solar cell. SiH 4 , Si 2 H 6 , SiH x Cl
In a plasma CVD method using a special high-pressure gas such as y as a process gas, strict response processing is required at various stages, such as gas production, transportation, management, and exhaust gas treatment. It is a factor that increases.

【0004】一方で、多結晶Siを光活性層に用いた薄
膜太陽電池の高効率化を図るには、高品質な光活性層の
形成、及びライトトラッピング構造の形成が最も重要な
要件であり、結晶構造因子においては、多結晶Si膜の
結晶粒径が大きく、且つ結晶層の表面が適当なテキスチ
ャー形状を有していることが理想であるといえる。
On the other hand, the formation of a high-quality photoactive layer and the formation of a light trapping structure are the most important requirements for improving the efficiency of a thin-film solar cell using polycrystalline Si for the photoactive layer. Regarding the crystal structure factor, it can be said that ideally, the polycrystalline Si film has a large crystal grain size and the surface of the crystal layer has an appropriate texture shape.

【0005】これに関しては、例えば特開平10−11
7006号に、プラズマCVD法を用いて光活性層を形
成し、Si層の表面に実質的に0.05〜3μmの自生
的な凹凸構造を形成する内容が掲載されているが、Si
膜の結晶粒径が数nm〜数100nmと小さいことが問
題として挙げられる。
[0005] Regarding this, for example, Japanese Patent Laid-Open No. Hei 10-11
No. 7006 describes that a photoactive layer is formed by using a plasma CVD method and a spontaneous uneven structure of 0.05 to 3 μm is formed on the surface of the Si layer.
A problem is that the crystal grain size of the film is as small as several nm to several hundred nm.

【0006】また、この製膜方法では、プラズマCVD
法を用いているため、装置の構成上、触媒CVD法等に
比べて大面積な製膜が困難であるといった課題も抱えて
いる。
In this film forming method, plasma CVD is used.
Since the method is used, there is a problem that it is difficult to form a large-area film as compared with the catalytic CVD method or the like due to the configuration of the apparatus.

【0007】本発明はこのような従来技術の問題点に鑑
みてなされたものであり、SiH4等の特殊高圧ガスを
用いたプラズマCVD法ではプロセスコストが増大し、
Si膜の結晶粒径が小さいために、ライトトラッピング
が充分でなく、また形成される半導体膜の大面積化が困
難であるという従来技術の問題点を解消した多結晶半導
体薄膜およびその形成方法およびその形成装置およびそ
の多結晶半導体薄膜を用いた半導体装置を提供すること
を目的とする。
[0007] The present invention has been made in view of such problems of the prior art, and the plasma CVD method using a special high-pressure gas such as SiH 4 increases the process cost.
Since the crystal grain size of the Si film is small, light trapping is not sufficient, and it is difficult to increase the area of the semiconductor film to be formed. It is an object of the present invention to provide a forming device and a semiconductor device using the polycrystalline semiconductor thin film.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に係る多結晶半導体薄膜の形成方法では、
エッチング性ガスを加熱触媒体に接触させて活性化した
後、この活性化したエッチングガスを固体状半導体に衝
突させて揮発性化合物を形成し、この揮発性化合物を前
記基板の表面に輸送して半導体薄膜を形成することを特
徴とする。
According to a first aspect of the present invention, there is provided a method for forming a polycrystalline semiconductor thin film.
After activating the etching gas by contacting the heating catalyst with the heating catalyst, the activated etching gas collides with the solid semiconductor to form a volatile compound, and transports the volatile compound to the surface of the substrate. The method is characterized in that a semiconductor thin film is formed.

【0009】上記多結晶半導体薄膜の形成方法では、前
記エッチング性ガスが水素ガス、フッ素系ガス、または
塩素系ガスのいずれか一種または複数種から成ることが
望ましい。
In the method of forming a polycrystalline semiconductor thin film, it is preferable that the etching gas is one or more of a hydrogen gas, a fluorine-based gas, and a chlorine-based gas.

【0010】上記多結晶半導体薄膜の形成方法では、前
記固体状半導体がシリコン、ゲルマニウム、またはセレ
ンのいずれか一種または複数種から成ることが望まし
い。
In the method of forming a polycrystalline semiconductor thin film, it is preferable that the solid semiconductor is made of one or more of silicon, germanium, and selenium.

【0011】上記多結晶半導体膜の形成方法では、前記
揮発性化合物を前記加熱触媒体に接触させた後に前記基
板の表面に輸送して半導体膜を形成してもよい。
In the method of forming a polycrystalline semiconductor film, the volatile compound may be brought into contact with the heating catalyst and then transported to the surface of the substrate to form a semiconductor film.

【0012】上記多結晶半導体薄膜の形成方法では、前
記加熱触媒体を1500〜2000℃の温度で加熱する
ことが望ましい。
In the method for forming a polycrystalline semiconductor thin film, it is preferable that the heating catalyst is heated at a temperature of 1500 to 2000 ° C.

【0013】上記多結晶半導体薄膜の形成方法では、前
記基板温度が前記固体状半導体の温度よりも高く設定さ
れていることが望ましい。
In the method of forming a polycrystalline semiconductor thin film, it is preferable that the substrate temperature is set higher than the temperature of the solid semiconductor.

【0014】また、請求項7に係る多結晶半導体膜の形
成装置では、エッチング性ガスを導入することができる
チャンバー内に半導体膜を形成する基板を配設すると共
に、固体状半導体材料を配設し、さらにこのチャンバー
内に導入されるエッチング性ガスを活性化させるための
加熱触媒体を配設したことを特徴とする。
In the apparatus for forming a polycrystalline semiconductor film according to the present invention, a substrate for forming a semiconductor film is provided in a chamber into which an etching gas can be introduced, and a solid semiconductor material is provided. Further, a heating catalyst for activating the etching gas introduced into the chamber is provided.

【0015】上記多結晶半導体膜の形成装置では、前記
加熱触媒体がタングステン、タンタル、白金、またはモ
リブデンのうちのいずれか1種または複数種から成るこ
とが望ましい。
In the above-described apparatus for forming a polycrystalline semiconductor film, it is preferable that the heating catalyst is made of one or more of tungsten, tantalum, platinum, and molybdenum.

【0016】上記多結晶半導体膜の形成装置では、前記
加熱触媒体が前記基板と前記固体状半導体の間に配設さ
れていることが望ましい。
In the above-described apparatus for forming a polycrystalline semiconductor film, it is preferable that the heating catalyst is disposed between the substrate and the solid semiconductor.

【0017】また、請求項10に係る太陽電池では、請
求項1ないし請求項6に記載の方法で形成した多結晶半
導体薄膜を用いることを特徴とする。
According to a tenth aspect of the present invention, there is provided a solar cell using a polycrystalline semiconductor thin film formed by the method according to the first to sixth aspects.

【0018】[0018]

【発明の実施の形態】以下、各請求項に係る発明の実施
形態を詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail.

【0019】図1は本発明に係る多結晶半導体薄膜の形
成装置の一実施形態を示す図であり、1はチャンバー、
2はガス導入口、3は固体状半導体、4は加熱触媒体、
5は基板である。
FIG. 1 is a view showing one embodiment of an apparatus for forming a polycrystalline semiconductor thin film according to the present invention.
2 is a gas inlet, 3 is a solid semiconductor, 4 is a heating catalyst,
5 is a substrate.

【0020】チャンバー1内の上部に下方を向けて基板
5を配設し、このチャンバー1内の下部に固体状半導体
3を配設し、基板1と固体状半導体3との間に加熱触媒
体4を配設して、チャンバー1の下部にガス導入口2を
設けたものである。
A substrate 5 is disposed downward in the upper part of the chamber 1, a solid semiconductor 3 is disposed in a lower part of the chamber 1, and a heating catalyst is provided between the substrate 1 and the solid semiconductor 3. 4 is provided, and a gas inlet 2 is provided in the lower part of the chamber 1.

【0021】基板5はガラスなどの絶縁基板やSUSな
どで構成され、支持板内にヒータなどの加熱手段(不図
示)を設けることによって、500℃程度の温度まで加
熱することができるように構成されている。
The substrate 5 is made of an insulating substrate such as glass, SUS, or the like, and can be heated to a temperature of about 500 ° C. by providing a heating means (not shown) such as a heater in the support plate. Have been.

【0022】前記加熱触媒体4はタングステン、タンタ
ル、白金、またはモリブデンのうちのいずれか1種また
は複数種から成る。
The heating catalyst 4 is made of one or more of tungsten, tantalum, platinum, and molybdenum.

【0023】この加熱触媒体4はエッチング性ガスで固
体状半導体3を均一にエッチングするためには、固体状
半導体3と基板5との間に配設されていることが望まし
いが、エッチング性ガスを活性化できる位置であれば、
それに限らない。
The heating catalyst 4 is preferably disposed between the solid semiconductor 3 and the substrate 5 in order to uniformly etch the solid semiconductor 3 with an etching gas. If the position can activate
Not limited to that.

【0024】このような装置を用いて、エッチング性ガ
スを加熱触媒体4に接触させて活性化した後、この活性
化したエッチング性ガスを固体状半導体3に衝突させて
揮発性化合物を形成し、この揮発性化合物を基板5の表
面に輸送して半導体薄膜を形成する。すなわち、このよ
うな形成方法で得られる多結晶半導体膜は基板5に水平
な方向の結晶粒径が0.1〜1μmの結晶粒となる。こ
れは、エッチング性ガスが加熱触媒体で活性化されてエ
ッチング作用を有するようになり、半導体膜の成長初期
における基板5の表面の核発生密度、及び成長中におけ
る二次核の発生速度が適度に抑制されているためである
と考えられる。また、この結晶成分の膜全体に占める割
合は90%以上となり、この多結晶半導体薄膜では、膜
の表面が0.05〜0.5μmの凹凸構造を有するよう
になる。
Using such an apparatus, an etching gas is brought into contact with the heating catalyst 4 to be activated, and then the activated etching gas is caused to collide with the solid semiconductor 3 to form a volatile compound. This volatile compound is transported to the surface of the substrate 5 to form a semiconductor thin film. That is, the polycrystalline semiconductor film obtained by such a formation method has crystal grains having a crystal grain size of 0.1 to 1 μm in a direction parallel to the substrate 5. This is because the etching gas is activated by the heating catalyst to have an etching action, and the nucleation density on the surface of the substrate 5 in the initial stage of the growth of the semiconductor film and the generation rate of the secondary nuclei during the growth are moderate. It is considered that this is because In addition, the ratio of the crystal component to the whole film is 90% or more, and in this polycrystalline semiconductor thin film, the surface of the film has an uneven structure of 0.05 to 0.5 μm.

【0025】前記エッチング性ガスとしては、水素ガ
ス、フッ素系ガス、または塩素系ガスのいずれか一種ま
たは複数種を用いることができる。フッ素系ガスとして
はCF 4、C26、SF6、BF4等、塩素系ガスとして
はCCl4、OCl3、BCl3、Cl2等、フッ素-塩素
系ガスとしてはCClF3、CCl22、CCl3F、C
2ClF5、C2Cl24等が用いられる。このエッチン
グ性ガスはチャンバー1内を13Pa程度に制御できる
ような流量に設定すればよい。
As the etching gas, hydrogen gas is used.
Gas, fluorine-based gas, or chlorine-based gas
Alternatively, a plurality of types can be used. As fluorine-based gas
Is CF Four, CTwoF6, SF6, BFFourEtc., as chlorine-based gas
Is CClFour, OCIThree, BClThree, ClTwoEtc., fluorine-chlorine
The system gas is CCIFThree, CClTwoFTwo, CClThreeF, C
TwoClFFive, CTwoClTwoFFourAre used. This etchin
Gas can control the inside of the chamber 1 to about 13 Pa
Such a flow rate may be set.

【0026】前記固体状半導体は、基板5上に形成する
多結晶半導体膜の主原料となるものであり、シリコン、
ゲルマニウム、またはセレンのいずれか一種または複数
種などから成る。
The solid semiconductor is a main raw material of a polycrystalline semiconductor film formed on the substrate 5.
It is made of one or more of germanium and selenium.

【0027】基板5に半導体膜を良好に形成するために
は、揮発性化合物を加熱触媒体4に再度接触させてもよ
い。このようにして形成すると、揮発性化合物がより活
性な状態になり、高速な堆積が期待できる。
In order to form a good semiconductor film on the substrate 5, the volatile compound may be brought into contact with the heating catalyst 4 again. When formed in this manner, the volatile compound becomes more active, and high-speed deposition can be expected.

【0028】前記加熱触媒体4は1500〜2000℃
に加熱する。この温度が1500℃以下であれば、加熱
触媒体4が揮発性化合物と反応して変質する事態を誘発
する。また、この温度が2000℃以上になると、加熱
触媒体4の成分が蒸発し、これが堆積膜中に不純物とし
て取り込まれ、半導体膜の品質が劣化する。
The heating catalyst 4 has a temperature of 1500 to 2000 ° C.
Heat to If this temperature is 1500 ° C. or lower, a situation where the heating catalyst 4 reacts with a volatile compound to cause deterioration is induced. Further, when the temperature becomes 2000 ° C. or higher, the components of the heating catalyst 4 evaporate, are taken in as impurities in the deposited film, and the quality of the semiconductor film deteriorates.

【0029】また、固体状半導体3は0〜300℃程度
に設定される。基板5は固体状半導体3の温度よりも1
00℃程度高く、すなわち100〜500℃に設定され
る。すなわち、高温となればなるほどエッチングレート
が低下するため、上記のように基板5の温度を固体状半
導体3の温度よりも高く設定することで、固体状半導体
のエッチングレートを高く維持しつつ、反面基板表面で
のエッチングレートを低くできるからである。
The temperature of the solid semiconductor 3 is set at about 0 to 300.degree. The temperature of the substrate 5 is higher than the temperature of the solid semiconductor 3 by one.
The temperature is set to be about 00 ° C. higher, that is, 100 to 500 ° C. That is, the higher the temperature, the lower the etching rate. Therefore, by setting the temperature of the substrate 5 higher than the temperature of the solid semiconductor 3 as described above, while maintaining the etching rate of the solid semiconductor high, This is because the etching rate on the substrate surface can be reduced.

【0030】次に、薄膜多結晶Si太陽電池の作成例を
図2に基づいて説明する。
Next, an example of forming a thin-film polycrystalline Si solar cell will be described with reference to FIG.

【0031】図2に示す薄膜太陽電池は、ガラス基板1
1上に、Ti、Ni、W、Mo、Cu、Ag、またはA
lのうち、少なくとも1種からなる金属膜、またはその
窒化膜、あるいはそのシリサイド膜で形成される薄膜層
12a、In、SnまたはZnのうち少なくとも一種を
含む酸化物層12b、p型多結晶Si下地層13、p型
多結晶Si光活性層14、n型の非単結晶Si層15、
及び受光面電極層を兼ねた導電性の反射防止膜16を順
次積層して成る。同図中の17は反射防止膜16の上面
に形成された表取り出し電極であり、18は酸化物層1
2bの上面に形成された裏取り出し電極である。
The thin-film solar cell shown in FIG.
1, Ti, Ni, W, Mo, Cu, Ag, or A
1, a thin film layer 12a formed of at least one kind of a metal film, a nitride film thereof, or a silicide film thereof, an oxide layer 12b containing at least one of In, Sn or Zn, a p-type polycrystalline Si An underlayer 13, a p-type polycrystalline Si photoactive layer 14, an n-type non-single-crystal Si layer 15,
And a conductive antireflection film 16 also serving as a light receiving surface electrode layer. In the figure, reference numeral 17 denotes a front extraction electrode formed on the upper surface of the antireflection film 16, and reference numeral 18 denotes the oxide layer 1.
It is a back extraction electrode formed on the upper surface of 2b.

【0032】このような薄膜太陽電池の製造にあたって
は、まず、ガラス基板11上に薄膜層12aを電子ビー
ム蒸着法、スパッタリング法等の真空製膜法によりシー
ト抵抗が1Ω/□程度以下となるように適当な膜厚に堆
積する。具体的には、Ti膜を0.1μm成膜し、この
上にAg膜を1μm成膜し、さらにTi膜を0.1μm
成膜するとシート抵抗0.1Ω/□以下が実現される。
なお、前記Ti及びAg膜は以下の工程で問題のない限
り他の金属等に置き換えてもよい。
In manufacturing such a thin film solar cell, first, a thin film layer 12a is formed on a glass substrate 11 by a vacuum film forming method such as an electron beam evaporation method or a sputtering method so that the sheet resistance becomes about 1 Ω / □ or less. To an appropriate thickness. Specifically, a Ti film is formed to a thickness of 0.1 μm, an Ag film is formed thereon to a thickness of 1 μm, and a Ti film is further formed to a thickness of 0.1 μm.
When the film is formed, a sheet resistance of 0.1Ω / □ or less is realized.
The Ti and Ag films may be replaced with other metals or the like in the following steps as long as there is no problem.

【0033】次に、薄膜層12a上にスパッタリング
法、イオンプレーティング法等の真空製膜法により酸化
物層12bを形成する。具体的には、表面に凹凸形状を
有したITO膜を形成する。次に、多結晶Si下地層1
3を前記酸化物上に形成する。具体的には、前記酸化物
層12b上に、プラズマCVD法または触媒CVD法等
により、Bが1E18〜1E22/cm3程度含まれた
多結晶Si層を1μm程度以下の膜厚に成膜し、高BS
F機能を有する下地層とする。
Next, an oxide layer 12b is formed on the thin film layer 12a by a vacuum film forming method such as a sputtering method or an ion plating method. Specifically, an ITO film having an uneven shape on the surface is formed. Next, the polycrystalline Si underlayer 1
3 is formed on the oxide. Specifically, a polycrystalline Si layer containing B at about 1E18 to 1E22 / cm 3 is formed on the oxide layer 12b to a thickness of about 1 μm or less by a plasma CVD method or a catalytic CVD method. , High BS
An underlayer having an F function is used.

【0034】次に、前記多結晶Si層13上に同層と同
一導電型(すなわちp型)のSi光活性層14となる多
結晶あるいは微結晶Si層を、図1に示した装置を用い
て厚さ1μm〜30μm程度に形成する。このとき、例
えばプロセスガスとしてH2、固体状半導体3として前
記多結晶Si層13と同一導電型の単結晶Si基板を用
い、H2=10sccm、基板温度を350℃〜500
℃、固体状半導体3の温度を150℃、直径0.5mm
のW(タングステン)触媒体4への投入電圧を〜50W
/m、触媒体と素子基板11との距離を〜5cm、成膜
圧力を〜13Paとする。この条件において形成される
多結晶あるいは微結晶Si層は、ラマン分光法によりそ
の結晶成分の膜全体に占める割合が90%以上であり、
SEM観察により結晶粒径が0.1〜1μmなる結晶粒
を含有することを確認している。また、同SEM観察か
ら同層表面が0.05〜0.5μmなる凹凸構造を有し
ていることも確認される。
Next, a polycrystalline or microcrystalline Si layer serving as a Si photoactive layer 14 of the same conductivity type (ie, p-type) as the same layer is formed on the polycrystalline Si layer 13 by using the apparatus shown in FIG. To a thickness of about 1 μm to 30 μm. At this time, such as H 2 as a process gas, a single-crystal Si substrate of the polycrystalline Si layer 13 of the same conductivity type is used as solid semiconductor 3, H 2 = 10 sccm, a substrate temperature of 350 ° C. to 500
° C, the temperature of the solid semiconductor 3 is 150 ° C, and the diameter is 0.5 mm.
Input voltage to the W (tungsten) catalyst 4 is ~ 50 W
/ M, the distance between the catalyst body and the element substrate 11 is up to 5 cm, and the deposition pressure is up to 13 Pa. A polycrystalline or microcrystalline Si layer formed under this condition has a crystal component occupying 90% or more of the entire film by Raman spectroscopy.
It has been confirmed by SEM observation that crystal grains having a crystal grain size of 0.1 to 1 μm are contained. The SEM observation also confirms that the surface of the layer has an uneven structure of 0.05 to 0.5 μm.

【0035】ここで、多結晶Si下地層13はSi光活
性層14の下地として機能し、Si光活性層14の結晶
粒径拡大、結晶品質向上を促進することができ、成膜条
件を最適化すればエピタキシャル成長をさせることも可
能である。
Here, the polycrystalline Si underlayer 13 functions as an underlayer of the Si photoactive layer 14 and can promote the expansion of the crystal grain size and the crystal quality of the Si photoactive layer 14, and optimize the film forming conditions. In this case, epitaxial growth can be performed.

【0036】次に、Si光活性層14上にSi下地層1
3とは反対の導電型(すなわちn型)の非晶質、多結晶
もしくは微結晶を含む非単結晶Si層15をプラズマC
VD法や触媒CVD法、またはスパッタリング法等の真
空製膜法により厚さ1μm以下に形成する。
Next, the Si underlayer 1 is formed on the Si photoactive layer 14.
A non-single-crystal Si layer 15 containing an amorphous, polycrystalline or microcrystalline of the opposite conductivity type (ie, n-type) to the plasma C
It is formed to a thickness of 1 μm or less by a vacuum film forming method such as a VD method, a catalytic CVD method, or a sputtering method.

【0037】ここで、Si光活性層14と非単結晶Si
層15とで形成されるpn接合の品質によっては、Si
光活性層14と非単結晶Si層15の間に、真性型(i
型)の非単結晶Si層を介在させてもよい。特に同層を
水素化アモルファスSiで形成する場合は、その膜厚を
2〜40nm程度にする。さらに、非単結晶Si層15
及び真性型非単結晶Si層を特に水素を含んだ雰囲気下
で形成すると、各層の界面及びその近傍の欠陥準位を水
素で終端することで不活性化でき、より品質の高いpn
接合またはpin接合を得ることができる。
Here, the Si photoactive layer 14 and the non-single-crystal Si
Depending on the quality of the pn junction formed with layer 15, Si
Between the photoactive layer 14 and the non-single-crystal Si layer 15, an intrinsic type (i
(Type) non-single-crystal Si layer may be interposed. In particular, when the same layer is formed of hydrogenated amorphous Si, the thickness is set to about 2 to 40 nm. Further, the non-single-crystal Si layer 15
In addition, when the intrinsic non-single-crystal Si layer is formed in an atmosphere containing hydrogen, in particular, the interface of each layer and a defect level in the vicinity thereof can be inactivated by terminating with hydrogen, and a higher quality pn can be obtained.
A junction or a pin junction can be obtained.

【0038】なお、RIE法を用いて、素子表面に結晶
Siの結晶方位に依存しない微細かつランダムな凹凸形
状を形成し、光利用効率を高めて素子変換効率を向上さ
せる場合は、pn接合を形成する前に、Si光活性層1
4に対してRIE法による処理を適用し、その後非単結
晶Si層15を形成する。用いる基板によっては薄膜層
12aの形成前にRIE法を用いて素子基板11の表面
に凹凸形状を形成してもよい。いずれにしても、このR
IE処理により少なくとも発電に寄与する光波長400
nm〜1000nmの範囲で、ベアSi表面の反射率を
10%以下にすることが可能である。
When the RIE method is used to form fine and random irregularities on the element surface independent of the crystal orientation of crystalline Si to increase the light use efficiency and improve the element conversion efficiency, the pn junction must be formed. Before forming, the Si photoactive layer 1
4 is subjected to RIE, and then a non-single-crystal Si layer 15 is formed. Depending on the substrate to be used, an uneven shape may be formed on the surface of the element substrate 11 by using the RIE method before forming the thin film layer 12a. In any case, this R
Light wavelength 400 contributing at least to power generation by IE processing
Within the range of nm to 1000 nm, the reflectance of the bare Si surface can be reduced to 10% or less.

【0039】次に、非単結晶Si層15上に、ITOや
SnO2等の導電性、あるいは窒化Si膜や酸化Si膜
等の絶縁性の反射防止膜16を、プラズマCVD法やス
パッタ法等の真空製膜法を用いて60〜100nm程度
の膜厚で製膜する。
Next, on the non-single-crystal Si layer 15, a conductive anti-reflection film 16 such as ITO or SnO 2 or an insulating anti-reflection film 16 such as a silicon nitride film or a silicon oxide film is formed by a plasma CVD method or a sputtering method. Is formed in a thickness of about 60 to 100 nm by using the vacuum film forming method described above.

【0040】次に、反射防止膜16上に表取り出し電極
17を、真空製膜技術、プリント及び焼成技術、さらに
メッキ技術等を用いて形成する。なお、絶緑性の反射防
止膜を非単結晶Si層15上に成膜した場合は、バッフ
ァードフッ酸等の適当な薬液によるエッチング技術によ
って表取り出し電極17を形成する領域について絶縁性
反射防止膜を除去して非単結晶Si層15を露出させ、
ここに表取り出し電極17を接触させるようにすればよ
い。
Next, a front extraction electrode 17 is formed on the antireflection film 16 by using a vacuum film forming technique, a printing and baking technique, and a plating technique. When an antireflection film having a green color is formed on the non-single-crystal Si layer 15, an insulating antireflection film is formed in a region where the front electrode 17 is formed by an etching technique using a suitable chemical such as buffered hydrofluoric acid. Removing the film to expose the non-single-crystal Si layer 15;
What is necessary is just to make the front extraction electrode 17 contact here.

【0041】また、裏取り出し電極18についても、薄
膜層12b上に真空製膜技術、プリント及び焼成技術、
さらにメッキ技術等を用いて形成することができる。ま
た、場合によっては裏電極層12aを露出させ、これに
裏取り出し電極18を形成してもよい。
The back electrode 18 is also formed on the thin film layer 12b by vacuum film forming technology, printing and baking technology,
Further, it can be formed using a plating technique or the like. In some cases, the back electrode layer 12a may be exposed, and the back extraction electrode 18 may be formed thereon.

【0042】以上によって、低コストで且つ高効率な薄
膜太陽電池を得ることができる。
As described above, a low-cost and highly efficient thin-film solar cell can be obtained.

【0043】なお、上記実施形態では、多結晶半導体薄
膜を太陽電池の光活性層に用いる例を説明したが、太陽
電池の他の層に用いることもできる。
In the above embodiment, an example was described in which the polycrystalline semiconductor thin film was used for the photoactive layer of the solar cell. However, the polycrystalline semiconductor thin film can be used for other layers of the solar cell.

【0044】[0044]

【発明の効果】以上のように、請求項1に係る多結晶半
導体薄膜の形成方法によれば、エッチング性ガスを加熱
触媒体に接触させて活性化した後、この活性化したエッ
チング性ガスを固体状半導体に衝突させて揮発性化合物
を形成し、この揮発性化合物を前記基板の表面に輸送し
て半導体薄膜を形成することから、結晶粒径が0.1〜
1μmで、この結晶成分の膜全体に占める割合が90%
以上となり、太陽電池の光活性層などに適した多結晶半
導体薄膜を形成することができる。また、取扱いが危険
なガスをプロセスガスとして用いることなく、比較的大
粒径を有する多結晶薄膜が低コストで得られ、各種薄膜
多結晶デバイスの製造コストの削減が可能となる。
As described above, according to the method for forming a polycrystalline semiconductor thin film according to the first aspect, after the etching gas is brought into contact with the heating catalyst to be activated, the activated etching gas is removed. A volatile compound is formed by colliding with a solid semiconductor, and the volatile compound is transported to the surface of the substrate to form a semiconductor thin film.
1 μm, the proportion of this crystal component in the whole film is 90%
As described above, a polycrystalline semiconductor thin film suitable for a photoactive layer or the like of a solar cell can be formed. Further, a polycrystalline thin film having a relatively large particle size can be obtained at low cost without using a dangerous gas as a process gas, and the manufacturing cost of various thin film polycrystalline devices can be reduced.

【0045】また、請求項7に係る多結晶半導体膜の形
成装置によれば、エッチング性ガスを導入することがで
きるチャンバー内に半導体膜を形成する基板を配設する
と共に、固体状半導体材料を配設し、さらにこのチャン
バー内に導入されるエッチング性ガスを活性化させるた
めの加熱触媒体を配設したことから、上述のような多結
晶半導体膜を容易に製造することができる。
According to the apparatus for forming a polycrystalline semiconductor film of the present invention, a substrate for forming a semiconductor film is provided in a chamber into which an etching gas can be introduced, and a solid semiconductor material is formed. Since the heating catalyst is provided for activating the etching gas introduced into the chamber, the above-described polycrystalline semiconductor film can be easily manufactured.

【0046】さらに、請求項10に係る太陽電池によれ
ば、上述のような多結晶半導体薄膜を用いることから、
多結晶半導体膜は結晶粒界の表面積が小さく、この界面
における光励起キャリアの再結合消滅を抑制することが
できるため、薄膜多結晶Si太陽電池に代表される薄膜
太陽電池の短絡電流及び開放電圧を向上できる。特に薄
膜多結晶Si太陽電池において短絡電流を増大させるに
は、ライトトラッピング構造の形成により光路長を増大
させ、長波長光感度を向上させることが極めて重要であ
るが、このライトトラッピング効果はテキスチャーの凹
凸の高低差及びアスペクト比によって大きく変化する。
一般に1〜2μm程度の多結晶Si光活性層を有する素
子においては、0.1μm程度の高低差が好ましいと考
えられており、上記多結晶半導体薄膜の凹凸の高低差は
この最適値に比較的近い値である。以上によって、高効
率薄膜太陽電池に好適な多結晶薄膜を低コストで得るこ
とができる。
Further, according to the solar cell according to the tenth aspect, since the above-described polycrystalline semiconductor thin film is used,
Since the polycrystalline semiconductor film has a small surface area of the crystal grain boundary and can suppress the recombination disappearance of photoexcited carriers at this interface, the short-circuit current and open-circuit voltage of a thin-film solar cell represented by a thin-film polycrystalline Si solar cell are reduced. Can be improved. In particular, in order to increase the short-circuit current in a thin-film polycrystalline Si solar cell, it is extremely important to increase the optical path length by forming a light trapping structure and improve long-wavelength light sensitivity. It changes greatly depending on the height difference of the unevenness and the aspect ratio.
Generally, in a device having a polycrystalline Si photoactive layer of about 1 to 2 μm, a height difference of about 0.1 μm is considered to be preferable, and the height difference of the unevenness of the polycrystalline semiconductor thin film is relatively small to this optimum value. It is a close value. As described above, a polycrystalline thin film suitable for a high-efficiency thin-film solar cell can be obtained at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多結晶半導体薄膜の形成装置の一実施
形態を示す図である。
FIG. 1 is a view showing one embodiment of a polycrystalline semiconductor thin film forming apparatus of the present invention.

【図2】本発明の多結晶半導体薄膜を用いた薄膜太陽電
池の一実施形態を示す図である。
FIG. 2 is a view showing one embodiment of a thin-film solar cell using a polycrystalline semiconductor thin film of the present invention.

【符号の説明】[Explanation of symbols]

1チャンバー 2ガス導入口 3固体状半導体 4加熱触媒体 5基板 11素子基板 12a裏電極層 12b酸化物層 13多結晶Si下地層 14多結晶Si光活性層 15非単結晶Si層 16反射防止膜 17表取り出し電極 18裏取り出し電極 1 chamber 2 gas inlet 3 solid semiconductor 4 heating catalyst 5 substrate 11 element substrate 12a back electrode layer 12b oxide layer 13 polycrystalline Si underlayer 14 polycrystalline Si photoactive layer 15 non-single crystalline Si layer 16 anti-reflection film 17 Front extraction electrode 18 Back extraction electrode

フロントページの続き Fターム(参考) 4G069 AA02 BC56A BC59A BC60A BC60B BC75A CD10 DA05 EE03 4K030 AA03 AA04 BA09 BA29 BA32 BB03 CA06 FA17 HA03 HA04 JA02 JA10 KA49 LA16 5F045 AB01 AB03 AB04 AB05 AC02 AD07 AD08 AD09 AE17 AF07 AF10 BB08 CA13 DA52 DP05 DQ08 EK07 5F051 AA03 CB04 CB29 CB30 GA04Continued on front page F-term (reference) 4G069 AA02 BC56A BC59A BC60A BC60B BC75A CD10 DA05 EE03 4K030 AA03 AA04 BA09 BA29 BA32 BB03 CA06 FA17 HA03 HA04 JA02 JA10 KA49 LA16 5F045 AB01 AB03 AB04 AB05 AC02 AD07 AD07 AF09 BP17 DQ08 EK07 5F051 AA03 CB04 CB29 CB30 GA04

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 エッチング性ガスを加熱触媒体に接触さ
せて活性化した後、この活性化したエッチング性ガスを
固体状半導体に衝突させて揮発性化合物を形成し、この
揮発性化合物を前記基板の表面に輸送して半導体薄膜を
形成する多結晶半導体薄膜の形成方法。
After activating an etching gas by contacting the heating gas with a heating catalyst, the activated etching gas is caused to collide with a solid semiconductor to form a volatile compound. Forming a semiconductor thin film by transporting to a surface of a semiconductor.
【請求項2】 前記エッチング性ガスが水素ガス、フッ
素系ガス、または塩素系ガスのいずれか一種または複数
種から成ることを特徴とする請求項1に記載の多結晶半
導体薄膜の形成方法。
2. The method for forming a polycrystalline semiconductor thin film according to claim 1, wherein the etching gas comprises one or more of a hydrogen gas, a fluorine-based gas, and a chlorine-based gas.
【請求項3】 前記固体状半導体がシリコン、ゲルマニ
ウム、またはセレンのいずれか一種または複数種から成
ることを特徴とする請求項1に記載の多結晶半導体薄膜
の形成方法。
3. The method according to claim 1, wherein the solid semiconductor is made of one or more of silicon, germanium, and selenium.
【請求項4】 前記揮発性化合物を前記加熱触媒体に接
触させた後に前記基板の表面に輸送して前記半導体薄膜
を形成することを特徴とする請求項1に記載の多結晶半
導体薄膜の形成方法。
4. The method according to claim 1, wherein the volatile compound is brought into contact with the heating catalyst, and then transported to the surface of the substrate to form the semiconductor thin film. Method.
【請求項5】 前記加熱触媒体を1500〜2000℃
の温度で加熱することを特徴とする請求項1に記載の多
結晶半導体薄膜の形成方法。
5. The heating catalyst is heated to a temperature of 1500 to 2000 ° C.
The method for forming a polycrystalline semiconductor thin film according to claim 1, wherein the heating is performed at a temperature of:
【請求項6】 前記基板温度が前記固体状半導体の温度
よりも高く設定されていることを特徴とする請求項1に
記載の多結晶半導体薄膜の形成方法。
6. The method according to claim 1, wherein the substrate temperature is set higher than the temperature of the solid semiconductor.
【請求項7】 エッチング性ガスを導入することができ
るチャンバー内に半導体膜を形成する基板を配設すると
共に、固体状半導体材料を配設し、さらにこのチャンバ
ー内に導入されるエッチング性ガスを活性化させるため
の加熱触媒体を配設した多結晶半導体膜の形成装置。
7. A substrate for forming a semiconductor film is provided in a chamber into which an etching gas can be introduced, a solid semiconductor material is provided, and the etching gas introduced into the chamber is further removed. An apparatus for forming a polycrystalline semiconductor film provided with a heating catalyst for activation.
【請求項8】 前記加熱触媒体がタングステン、タンタ
ル、白金、またはモリブデンのうちのいずれか1種また
は複数種から成ることを特徴とする請求項7に記載の多
結晶半導体膜の形成装置。
8. The polycrystalline semiconductor film forming apparatus according to claim 7, wherein the heating catalyst is made of one or more of tungsten, tantalum, platinum, and molybdenum.
【請求項9】 前記加熱触媒体が前記基板と前記固体状
半導体の間に配設されていることを特徴とする請求項7
に記載の多結晶半導体膜の形成装置。
9. The heating catalyst according to claim 7, wherein the heating catalyst is disposed between the substrate and the solid semiconductor.
3. The apparatus for forming a polycrystalline semiconductor film according to claim 1.
【請求項10】 請求項1ないし請求項6に記載の方法
で形成した多結晶半導体薄膜を用いた太陽電池。
10. A solar cell using a polycrystalline semiconductor thin film formed by the method according to claim 1.
JP2000261642A 2000-08-30 2000-08-30 Method and device for forming polycrystalline semiconductor thin film, and solar cell using polycrystalline semiconductor thin film Pending JP2002075877A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
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JP2003332605A (en) * 2002-05-15 2003-11-21 Sharp Corp Surface roughening method of semiconductor substrate and solar battery
KR100732858B1 (en) 2005-05-13 2007-06-27 삼성에스디아이 주식회사 Method for in-situ polycrystalline thin film growth
US8030223B2 (en) 2003-05-09 2011-10-04 Shin-Etsu Chemical Co., Ltd. Solar cell and method of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003332605A (en) * 2002-05-15 2003-11-21 Sharp Corp Surface roughening method of semiconductor substrate and solar battery
JP4518731B2 (en) * 2002-05-15 2010-08-04 シャープ株式会社 Method for forming irregularities on the surface of a polycrystalline silicon substrate
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