JP2002073415A - 遅延無効化コンピュータキャッシュシステム - Google Patents

遅延無効化コンピュータキャッシュシステム

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Publication number
JP2002073415A
JP2002073415A JP2001211630A JP2001211630A JP2002073415A JP 2002073415 A JP2002073415 A JP 2002073415A JP 2001211630 A JP2001211630 A JP 2001211630A JP 2001211630 A JP2001211630 A JP 2001211630A JP 2002073415 A JP2002073415 A JP 2002073415A
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JP
Japan
Prior art keywords
cache
level
line
transaction
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2001211630A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002073415A5 (enExample
Inventor
D Gaiser Brain
ブレイン・ディー・ガイザー
W Hereru Rass
ラス・ダブリュー・ヘレル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2002073415A publication Critical patent/JP2002073415A/ja
Publication of JP2002073415A5 publication Critical patent/JP2002073415A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2001211630A 2000-07-31 2001-07-12 遅延無効化コンピュータキャッシュシステム Withdrawn JP2002073415A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US629128 1996-04-08
US09/629,128 US6574710B1 (en) 2000-07-31 2000-07-31 Computer cache system with deferred invalidation

Publications (2)

Publication Number Publication Date
JP2002073415A true JP2002073415A (ja) 2002-03-12
JP2002073415A5 JP2002073415A5 (enExample) 2005-06-30

Family

ID=24521694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001211630A Withdrawn JP2002073415A (ja) 2000-07-31 2001-07-12 遅延無効化コンピュータキャッシュシステム

Country Status (2)

Country Link
US (1) US6574710B1 (enExample)
JP (1) JP2002073415A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007505407A (ja) * 2003-09-12 2007-03-08 インテル コーポレイション マルチインタフェースキャッシュにおけるジョイントコヒーレンシ状態のための方法及び装置
JP2007200292A (ja) * 2006-01-25 2007-08-09 Internatl Business Mach Corp <Ibm> エントリの時間経過によるキャッシュ・エントリの所有権喪失
KR100858527B1 (ko) 2007-04-18 2008-09-12 삼성전자주식회사 시간적 인접성 정보를 이용한 캐쉬 메모리 시스템 및데이터 저장 방법
JP2009295156A (ja) * 2008-05-30 2009-12-17 Intel Corp インバリデーショントランザクションのスヌープフィルタからの削除
JP6249120B1 (ja) * 2017-03-27 2017-12-20 日本電気株式会社 プロセッサ
JP2019530112A (ja) * 2016-09-06 2019-10-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 遅延キャッシュの利用のためのシステム及び方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6868481B1 (en) * 2000-10-31 2005-03-15 Hewlett-Packard Development Company, L.P. Cache coherence protocol for a multiple bus multiprocessor system
US6704844B2 (en) * 2001-10-16 2004-03-09 International Business Machines Corporation Dynamic hardware and software performance optimizations for super-coherent SMP systems
US6983348B2 (en) * 2002-01-24 2006-01-03 Intel Corporation Methods and apparatus for cache intervention
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US20040153611A1 (en) * 2003-02-04 2004-08-05 Sujat Jamil Methods and apparatus for detecting an address conflict
US7287126B2 (en) * 2003-07-30 2007-10-23 Intel Corporation Methods and apparatus for maintaining cache coherency
US7711901B2 (en) * 2004-02-13 2010-05-04 Intel Corporation Method, system, and apparatus for an hierarchical cache line replacement
US7373466B1 (en) * 2004-04-07 2008-05-13 Advanced Micro Devices, Inc. Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
US20070186045A1 (en) * 2004-07-23 2007-08-09 Shannon Christopher J Cache eviction technique for inclusive cache systems
US7669009B2 (en) * 2004-09-23 2010-02-23 Intel Corporation Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches
US20070124543A1 (en) * 2005-11-28 2007-05-31 Sudhir Dhawan Apparatus, system, and method for externally invalidating an uncertain cache line
US20080120469A1 (en) * 2006-11-22 2008-05-22 International Business Machines Corporation Systems and Arrangements for Cache Management
US8176255B2 (en) * 2007-10-19 2012-05-08 Hewlett-Packard Development Company, L.P. Allocating space in dedicated cache ways
US8200903B2 (en) 2008-02-14 2012-06-12 Hewlett-Packard Development Company, L.P. Computer cache system with stratified replacement
US20110320720A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Cache Line Replacement In A Symmetric Multiprocessing Computer
GB2566647B (en) * 2016-09-01 2021-10-27 Advanced Risc Mach Ltd Cache retention data management
US11556477B2 (en) * 2018-06-15 2023-01-17 Arteris, Inc. System and method for configurable cache IP with flushable address range
US11687459B2 (en) * 2021-04-14 2023-06-27 Hewlett Packard Enterprise Development Lp Application of a default shared state cache coherency protocol

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
US5577227A (en) * 1994-08-04 1996-11-19 Finnell; James S. Method for decreasing penalty resulting from a cache miss in multi-level cache system
US5860095A (en) * 1996-01-02 1999-01-12 Hewlett-Packard Company Conflict cache having cache miscounters for a computer memory system
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6134634A (en) * 1996-12-20 2000-10-17 Texas Instruments Incorporated Method and apparatus for preemptive cache write-back
US5996048A (en) * 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6078992A (en) * 1997-12-05 2000-06-20 Intel Corporation Dirty line cache
US6360301B1 (en) * 1999-04-13 2002-03-19 Hewlett-Packard Company Coherency protocol for computer cache
US6477635B1 (en) * 1999-11-08 2002-11-05 International Business Machines Corporation Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007505407A (ja) * 2003-09-12 2007-03-08 インテル コーポレイション マルチインタフェースキャッシュにおけるジョイントコヒーレンシ状態のための方法及び装置
JP2007200292A (ja) * 2006-01-25 2007-08-09 Internatl Business Mach Corp <Ibm> エントリの時間経過によるキャッシュ・エントリの所有権喪失
KR100858527B1 (ko) 2007-04-18 2008-09-12 삼성전자주식회사 시간적 인접성 정보를 이용한 캐쉬 메모리 시스템 및데이터 저장 방법
US8793437B2 (en) 2007-04-18 2014-07-29 Samsung Electronics Co., Ltd. Cache memory system using temporal locality information and a data storage method
JP2009295156A (ja) * 2008-05-30 2009-12-17 Intel Corp インバリデーショントランザクションのスヌープフィルタからの削除
JP2019530112A (ja) * 2016-09-06 2019-10-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 遅延キャッシュの利用のためのシステム及び方法
JP6249120B1 (ja) * 2017-03-27 2017-12-20 日本電気株式会社 プロセッサ
JP2018163571A (ja) * 2017-03-27 2018-10-18 日本電気株式会社 プロセッサ
US10565111B2 (en) 2017-03-27 2020-02-18 Nec Corporation Processor

Also Published As

Publication number Publication date
US6574710B1 (en) 2003-06-03

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