JP2002064367A - Clock multiplying circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the output clock having an arbitrary duty ratio over a wide input frequency range. SOLUTION: An input clock delayed by a variable delay circuit 3 and an original input clock are inputted to an EXOR circuit and a duplexed output clock is provided. The mean value of this output clock is obtained by a low-pass filter 5, the difference of that mean value and a duty ratio setting voltage is provided by a differential amplifier 6 and corresponding to that differential signal, the delay quantity of the variable delay circuit 3 is controlled. Thus, the duplexed clock having a duty ratio corresponding to the duty ratio setting signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock multiplying circuit for locally generating a multiplied clock of a system clock inside an LSI or on a wiring board on which the LSI is mounted.

[0002]

2. Description of the Related Art Advances in LSI technology have made it possible for LSI internal circuits to operate at clock frequencies reaching 1 GHz. However, especially in a large-scale device, it is difficult to distribute a high-frequency clock to the entire device. Therefore, a method of generating a high-frequency clock for driving the LSI by multiplying a low-frequency system clock inside the LSI or on a wiring board included in the device has been used.

As a circuit for multiplying a clock, a circuit using a phase locked loop (PLL) shown in FIG. 4 is typical. In FIG. 4, 41 is a clock input terminal, 42 is a clock output terminal, 43 is a phase comparator, 44 is a low-pass filter, 45 is a voltage controlled oscillator, and 46 is a frequency divider. In this PLL, it is possible to obtain an output clock of desired multiplication synchronized with the input clock. However, a frequency-multiplied clock can be generated only in a frequency range in which the frequency variable range of the voltage-controlled oscillator 45 can oscillate, and it is necessary to optimally design a PLL for each system clock of a device to which it is applied.

As another method, a simple multiplication circuit using a fixed delay circuit 53 and an EXOR circuit 54 shown in FIG. 5 is known. 51 is a clock input terminal and 52 is a clock output terminal. In this multiplier circuit, an output clock that is twice the input clock can be obtained. However, if the delay time of the fixed delay circuit 51 is Δt and the cycle of the multiplied clock is τ, the duty ratio is fixed to Δt / τ, and if the frequency of the input clock changes, the duty ratio greatly changes. There were drawbacks.

[0005]

As described above, it has been difficult for a conventional clock multiplication circuit to generate a multiplied clock having an appropriate duty ratio over a wide input frequency range.

[0006] The present invention has been made in view of the above points, and its object is to provide a 50-bit input frequency range.
An object of the present invention is to provide a clock multiplying circuit capable of obtaining an output clock having an arbitrary duty ratio such as%.

[0007]

According to a first aspect of the present invention, there is provided a variable delay circuit for delaying an input clock by a delay amount according to a control signal, and an input clock delayed by the variable delay circuit. EXOR circuit for outputting a signal of exclusive OR of the original input clock and an average value circuit for obtaining an average value of the output signal of the EXOR circuit, an average value output signal of the average value circuit, and a duty ratio setting signal And a differential amplifier that obtains a differential signal from the EXOR circuit and outputs the control signal to the variable delay circuit. The EXOR circuit outputs a doubled clock having a duty ratio corresponding to the duty ratio setting signal.

In a second aspect based on the first aspect, the variable delay circuit is replaced with a plurality of variable delay circuits having variable delay ranges different from each other, and one variable delay circuit of the plurality of variable delay circuits is provided. Select the output signal of the circuit and select EX
Selection means for inputting to the OR circuit is provided.

According to a third aspect of the present invention, a frequency divider for dividing the input clock by と, and a duty ratio setting signal having a duty ratio of 5
A first clock multiplying circuit according to the first or second invention, which is set to 0% and receives an output clock of the frequency divider;
And a second clock multiplying circuit according to the first or second invention for inputting an output clock of the clock multiplying circuit.

In a fourth aspect, the clock multiplying circuit of the first, second, or third aspect is cascaded in N stages (N ≧ 2), and the input clock is multiplied by 2 ^N and output.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a circuit diagram of a clock multiplication circuit according to a first embodiment of the present invention, and is a diagram showing a configuration according to claim 1. 1 is a clock input terminal, 2 is a clock output terminal, 3 is a variable delay circuit whose delay time can be externally controlled, 4 is an EXOR circuit for detecting a mismatch between two input signals, and 5 is a high-frequency component removing input signal. A low-pass filter (average circuit) for outputting an average value, and 6 is a difference amplifier.

Here, the input clock is supplied to the variable delay circuit 3
To the EXOR circuit 4 to obtain a multiplied clock. Further, the obtained multiplied clock is applied to a low-pass filter 5.
To detect the average value, find the difference between the average value and the duty ratio setting voltage Vd using the differential amplifier 6, and apply the output of the differential amplifier 6 as the delay time setting voltage of the variable delay circuit 3. A feedback loop is formed.

By this feedback loop, the delay amount of the variable delay circuit 3 is automatically controlled so that the average value output proportional to the duty ratio of the output clock coincides with the duty ratio set value, and the delay time of the variable delay circuit 3 is varied. A multiplied output clock having a desired duty ratio within the range can be obtained.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a clock multiplication circuit according to the embodiment of the present invention, showing a configuration according to claim 2. The same components as those in FIG. 1 are denoted by the same reference numerals. Here, n variable delay circuits 31 and 3 having different delay time variable ranges, respectively.
, 3n, and a selector (selecting means) 7 for selecting one output signal of the n delay circuits and inputting the output signal to the EXOR circuit 4.

In the multiplied clock circuit shown in FIG. 1, the frequency range of the input clock or the settable range of the duty ratio is limited by the variable delay time range of the variable delay circuit 3. Therefore, in the present embodiment, a variable delay circuit having a desired variable range can be selected by the selector 7 from n variable delay circuits 31, 31,.
The input frequency range and the duty ratio setting range can be selected from a wide range.

[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.
FIG. 9 is a circuit diagram of a clock multiplication circuit according to the third embodiment, and is a diagram showing a configuration according to claim 3. The same components as those in FIG. 1 are denoted by the same reference numerals. Here, the 1/2 frequency divider 8 is connected immediately after the clock input terminal 1 to increase the frequency of the input clock to 1/2 times and to set the duty ratio to 50%. The shooty ratio setting voltage set in the difference amplifier 6 is a voltage Vd1 for a duty ratio of 50%. Further, a clock multiplication circuit of a subsequent stage including a variable delay circuit 3A, an EXOR circuit 4A, a low-pass filter 5A, and a differential amplifier 6A is provided at a stage subsequent to the EXOR circuit 4.

In the clock multiplying circuit shown in FIG. 1, when the duty ratio of the input clock is not 50%, there occurs a problem that the cycle of the output clock varies every cycle. Therefore, in the present embodiment, the input clock is frequency-divided by で in the frequency divider 8 and the duty ratio is set to 50%, based on which the delay circuit 3, the EXOR circuit 4, the low-pass filter 5,
A clock having the same frequency as the input clock and a duty ratio of 50% is generated by a clock multiplication circuit in the preceding stage including the differential amplifier 6. Then, based on this, the delay circuit 3A,
A post-stage clock multiplication circuit including an EXOR circuit 4A, a low-pass filter 5A, and a differential amplifier 6A obtains an output clock having a constant cycle, which is twice the input clock.

[Other Embodiments] The first embodiment described above
In the third to third embodiments, the frequency of the input clock is multiplied by 2. However, if these clock multiplying circuits are set as a set and N stages (N ≧ 2) are cascaded,
The frequency of the input clock can be multiplied by 2 ^N.

[0019]

As described above, according to the present invention, it is possible to obtain an output clock having an arbitrary duty ratio in a wide range including 50% in a wider input frequency range than when a PLL circuit is used.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock multiplication circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a clock multiplication circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a clock multiplication circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a clock multiplying circuit using a conventional PLL circuit.

FIG. 5 is a block diagram of a clock multiplication circuit using a conventional EXOR circuit and a delay circuit.

[Explanation of symbols]

1: clock input terminal, 2: clock output terminal, 3, 3
A, 31, 32, 3n: Variable delay circuit, 4, 4A: EX
OR circuit, 5, 5A: low-pass filter, 6, 6A: differential amplifier.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasuhiro Ando 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5J039 AC03 KK11 KK13 KK18 KK27 KK29 KK33 MM06

Claims (4)

[Claims] 1. A variable delay circuit for delaying an input clock by a delay amount according to a control signal, and an EXOR for outputting a signal of an exclusive OR of the input clock delayed by the variable delay circuit and the original input clock Circuit, an average value circuit for obtaining an average value of the output signal of the EXOR circuit, a difference signal between the average value output signal of the average value circuit and the duty ratio setting signal, and output to the variable delay circuit as the control signal. And a differential amplifier that outputs a doubled clock having a duty ratio according to the duty ratio setting signal from the EXOR circuit. 2. The clock multiplying circuit according to claim 1, wherein said variable delay circuit is replaced with a plurality of variable delay circuits having different variable delay ranges, and one of said plurality of variable delay circuits is changed. A clock multiplying circuit comprising a selecting means for selecting an output signal of a delay circuit and inputting the signal to the EXOR circuit. 3. A frequency divider for dividing an input clock by １,
3. The first clock multiplying circuit according to claim 1, wherein a duty ratio setting signal is set to a duty ratio of 50%, and an output clock of the frequency divider is input, and an output clock of the first clock multiplying circuit is input. A clock multiplying circuit, comprising: the second clock multiplying circuit according to claim 1. 4. The clock multiplying circuit according to claim 1, 2 or 3, wherein N stages (N ≧ 2) are connected in cascade, and an input clock is 2 ^N
A clock multiplication circuit characterized by multiplying and outputting.