JP2002064278A - Multilayer wiring board and electronic part module using the same - Google Patents

Multilayer wiring board and electronic part module using the same

Info

Publication number
JP2002064278A
JP2002064278A JP2000251379A JP2000251379A JP2002064278A JP 2002064278 A JP2002064278 A JP 2002064278A JP 2000251379 A JP2000251379 A JP 2000251379A JP 2000251379 A JP2000251379 A JP 2000251379A JP 2002064278 A JP2002064278 A JP 2002064278A
Authority
JP
Japan
Prior art keywords
insulating layer
wiring board
multilayer wiring
powder
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000251379A
Other languages
Japanese (ja)
Inventor
Tadashi Nagasawa
忠 長澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000251379A priority Critical patent/JP2002064278A/en
Publication of JP2002064278A publication Critical patent/JP2002064278A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally capacitive elements having large capacitance cannot be formed in a multilayer wiring board and an electronic part module cannot be miniaturized in the multilayer wiring board, where an organic material is set to be an insulating layer. SOLUTION: In the multilayer wiring board 4, a plurality of insulating layers 1a to 1e constituted of the organic materials are laminated on upper and lower parts, and wiring conductors 2 are stuck to the surfaces of the insulating layers 1a to 1e. At least one layer in the insulating layers 1a to 1e is set to be the insulating layer 1c including conductive resin powders and dielectric powders, whose relative dielectric constant is not less than 20. The insulating layer 1c is oppositely sandwiched by the wiring conductors 2, stuck on the upper/lower faces of the layer so as to form the capacitive element A. The capacitance of the capacitive element A can be increased and consequently the area of the confronted electrodes of the capacitive element A can be reduced. Thus, the electronic part module 5 can be miniaturized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、各種AV機器や家
電機器・通信機器・コンピュータやその周辺機器等の電
子機器に使用される配線基板ならびにこれを用いた電子
部品モジュールに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for use in electronic devices such as various AV devices, home appliances, communication devices, computers and their peripheral devices, and an electronic component module using the same.

【0002】[0002]

【従来の技術】従来、半導体素子等の能動部品や容量素
子・抵抗素子等の受動部品を多数搭載し、所定の電子回
路を構成するようになした混成集積回路等の電子部品モ
ジュールは、通常、アルミナ等のセラミックス材料から
成る絶縁基板の内部および表面にタングステン・モリブ
デン等の高融点金属粉末から成る複数の配線導体を形成
した配線基板の表面に、半導体素子や容量素子・抵抗素
子等を搭載取着するとともにこれらの電極を各配線導体
に接続することによって形成されている。
2. Description of the Related Art Conventionally, an electronic component module such as a hybrid integrated circuit, in which a large number of active components such as semiconductor elements and passive components such as capacitance elements and resistance elements are mounted to constitute a predetermined electronic circuit, is usually used. Semiconductor elements, capacitance elements, resistance elements, etc. are mounted on the surface of a wiring board in which a plurality of wiring conductors made of a high melting point metal powder such as tungsten and molybdenum are formed inside and on the surface of an insulating substrate made of a ceramic material such as alumina. It is formed by attaching and connecting these electrodes to each wiring conductor.

【0003】しかしながら、このような配線基板は、配
線導体がタングステンやモリブデン等の高融点金属粉末
から成る導電ペーストをスクリーン印刷等の厚膜手法を
採用し所定パターンに印刷塗布することによって形成さ
れていることから、配線導体の微細化が困難で配線導体
を高密度に形成することができないという問題点を有し
ていた。
However, in such a wiring board, the wiring conductor is formed by printing and applying a conductive paste made of a refractory metal powder such as tungsten or molybdenum in a predetermined pattern by employing a thick film technique such as screen printing. Therefore, there is a problem that it is difficult to miniaturize the wiring conductor and it is not possible to form the wiring conductor with high density.

【0004】また、従来の配線基板は、表面に半導体素
子等の能動部品や容量素子・抵抗素子等の受動部品が多
数搭載され、部品の搭載数に応じて基板が大型化してし
まうという問題点も有していた。
Further, the conventional wiring board has a problem that a large number of active parts such as semiconductor elements and passive parts such as capacitance elements and resistance elements are mounted on the surface thereof, and the size of the board increases according to the number of mounted parts. Had also.

【0005】このような問題点を解決するために、特開
平11-68319号公報には、複数の有機材料絶縁層と複数の
薄膜配線導体とを交互に多層に積層するとともに、高誘
電率粉末を含有する有機材料絶縁層とそれを挟む対向電
極を用いて内部に容量素子を形成した多層配線基板が提
案されている。
In order to solve such a problem, Japanese Patent Application Laid-Open No. H11-68319 discloses that a plurality of organic material insulating layers and a plurality of thin film wiring conductors are alternately laminated in a multilayer, and a high dielectric constant powder is used. There has been proposed a multilayer wiring board in which a capacitive element is formed by using an organic material insulating layer containing the same and a counter electrode sandwiching the same.

【0006】この多層配線基板によれば、配線導体を薄
膜で形成したことから配線の微細化が可能となり、配線
を極めて高密度に形成することができ、また、多層配線
基板内部に容量素子を形成したことから多層配線基板に
半導体素子や容量素子・抵抗素子等の電子部品を搭載し
て混成集積回路装置等の電子部品モジュールを製作する
場合に、多層配線基板に別途、容量素子を多数実装する
必要はなく、その結果、多層配線基板に実装される部品
の数が減り、電子部品モジュールを小型化することがで
きるというものである。
According to this multilayer wiring board, since the wiring conductor is formed of a thin film, the wiring can be miniaturized, the wiring can be formed at an extremely high density, and a capacitor element is provided inside the multilayer wiring board. Due to the formation, when mounting electronic components such as semiconductor elements, capacitors and resistors on the multilayer wiring board to manufacture electronic component modules such as hybrid integrated circuit devices, a large number of separate capacitive elements are mounted on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board is reduced, and the size of the electronic component module can be reduced.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この多
層配線基板は高誘電率粉末を含有する有機材料絶縁層を
用いて容量素子を形成しているものの、有機材料絶縁層
を構成する有機材料の比誘電率が2〜5程度と低いため
に含有する高誘電率粉末の比誘電率を十分に発現させる
ことができず、高誘電率粉末を含有する有機材料絶縁層
の比誘電率は10程度と低いものとなり、その結果、大き
な静電容量の容量素子を得るためには対向電極の面積を
大きなものとする必要があり、近年の電子部品モジュー
ルの小型化の要求に十分答えることができないという問
題点を有していた。
However, although this multilayer wiring board forms a capacitive element using an organic material insulating layer containing a high dielectric constant powder, the ratio of the organic material constituting the organic material insulating layer is low. Since the dielectric constant is as low as about 2 to 5, the relative permittivity of the high-permittivity powder contained cannot be sufficiently expressed, and the relative permittivity of the organic material insulating layer containing the high-permittivity powder is about 10 As a result, in order to obtain a capacitive element having a large capacitance, it is necessary to increase the area of the counter electrode, and it is not possible to sufficiently respond to the recent demand for miniaturization of electronic component modules. Had a point.

【0008】また、大きな静電容量を得る別の方法とし
て、対向電極間の距離を短くする、すなわち有機材料絶
縁層の厚みを薄くした場合、所望の大きな静電容量を得
るためには絶縁層の厚みを極端に薄くする必要があり絶
縁層を形成する前駆体シートの強度が弱くなってしま
い、その結果、このシートを形成する際にシートが破れ
てしまったり、あるいは高誘電率粉末の分散ムラを生じ
均一な静電容量を得ることができないという問題点を有
していた。
As another method for obtaining a large capacitance, when the distance between the opposed electrodes is shortened, that is, when the thickness of the organic material insulating layer is reduced, the insulating layer is required to obtain a desired large capacitance. It is necessary to make the thickness of the precursor sheet extremely thin, so that the strength of the precursor sheet forming the insulating layer is weakened. As a result, the sheet is broken when forming this sheet, or the dispersion of the high dielectric constant powder is performed. There is a problem that unevenness occurs and a uniform capacitance cannot be obtained.

【0009】本発明はかかる従来技術の問題点に鑑みに
案出されたものであり、その目的は、静電容量の大きい
容量素子を内蔵した小型の多層配線基板およびこれを用
いた電子部品モジュールを提供することにある。
The present invention has been devised in view of the problems of the prior art, and has as its object to provide a small-sized multilayer wiring board having a built-in capacitive element having a large capacitance and an electronic component module using the same. Is to provide.

【0010】[0010]

【課題を解決するための手段】本発明の多層配線基板
は、有機材料から成る複数の絶縁層を積層するとともに
これら絶縁層の表面に配線導体を形成して成る多層配線
基板であって、絶縁層の少なくとも一層に導電性樹脂粉
末および比誘電率が20以上の誘電体粉末を含有させると
ともに、この絶縁層をその上下両面に被着した配線導体
で対向挟持することによって容量素子を形成したことを
特徴とするものである。
The multilayer wiring board according to the present invention is a multilayer wiring board comprising a plurality of insulating layers made of an organic material laminated and a wiring conductor formed on the surface of the insulating layers. At least one of the layers contains a conductive resin powder and a dielectric powder having a relative dielectric constant of 20 or more, and the capacitive element is formed by sandwiching the insulating layer oppositely with wiring conductors attached on both upper and lower surfaces thereof. It is characterized by the following.

【0011】また、本発明の多層配線基板は、上記構成
において、容量素子を形成した絶縁層が1〜30体積%の
導電性樹脂粉末と、10〜70体積%の比誘電率が20以上の
誘電体粉末と、10〜89体積%の有機材料とから成ること
を特徴とするものである。
Further, in the multilayer wiring board of the present invention, in the above structure, the insulating layer on which the capacitive element is formed has a conductive resin powder of 1 to 30% by volume, and a dielectric constant of 10 to 70% by volume having a relative dielectric constant of 20 or more. It is characterized by comprising a dielectric powder and 10 to 89% by volume of an organic material.

【0012】さらに、本発明の多層配線基板は、上記構
成において、容量素子を形成した絶縁層の配線導体間の
方向の比誘電率が、これに直交する方向の比誘電率の1.
2倍以上であることを特徴とするものである。
Further, in the multilayer wiring board of the present invention, in the above structure, the relative dielectric constant between the wiring conductors of the insulating layer on which the capacitive element is formed is 1.1 times the relative dielectric constant in the direction perpendicular to the direction.
It is characterized by being at least twice.

【0013】また、本発明の電子部品モジュールは、上
記の多層配線基板に電子部品を実装し、回路素子として
容量素子と電子部品とを含む電気的な回路を構成したこ
とを特徴とするものである。
Further, an electronic component module according to the present invention is characterized in that an electronic component is mounted on the multilayer wiring board and an electric circuit including a capacitor and an electronic component is formed as a circuit element. is there.

【0014】本発明の多層配線基板によれば、絶縁層の
少なくとも一層に導電性樹脂粉末および比誘電率が20以
上の誘電体粉末を含有させたことから、この絶縁層を配
線導体で対向挟持して形成した容量素子に外部から電圧
を印加した場合、導電性樹脂粉末が電気伝導性のために
電荷を効率よく分離して導体としての役目を果たし、導
電性樹脂粉末の絶縁層の厚み方向の長さ分だけ静電容量
に寄与する絶縁層の厚みを実質的に減少させることがで
き、その結果、絶縁層の厚みを極端に薄くしなくともそ
の静電容量を所望の大きなものとして容量素子を形成す
る対向電極の面積を小さなものとすることができ、多層
配線基板を小型化することが可能となる。
According to the multilayer wiring board of the present invention, since at least one of the insulating layers contains the conductive resin powder and the dielectric powder having a relative dielectric constant of 20 or more, the insulating layer is sandwiched between the wiring conductors. When a voltage is externally applied to the capacitive element formed in the above manner, the conductive resin powder efficiently separates electric charges due to electric conductivity and functions as a conductor, and serves as a conductor in the thickness direction of the insulating layer of the conductive resin powder. The thickness of the insulating layer that contributes to the capacitance can be substantially reduced by the length of the insulating layer. As a result, the capacitance can be increased to a desired value without extremely reducing the thickness of the insulating layer. The area of the counter electrode forming the element can be reduced, and the multilayer wiring board can be reduced in size.

【0015】また、本発明の多層配線基板によれば、容
量素子を形成した絶縁層を、1〜30体積%の導電性樹脂
粉末と、10〜70体積%の比誘電率が20以上の誘電体粉末
と、10〜89体積%の有機材料とから構成したことから、
導電性樹脂粉末および誘電体粉末を絶縁層中に均一に良
好に分散させることができ、静電容量のムラのない容量
素子を得ることができる。
Further, according to the multilayer wiring board of the present invention, the insulating layer on which the capacitance element is formed is made of a conductive resin powder of 1 to 30% by volume and a dielectric resin of 10 to 70% by volume having a relative dielectric constant of 20 or more. Because it is composed of body powder and 10-89% by volume of organic material,
The conductive resin powder and the dielectric powder can be uniformly and satisfactorily dispersed in the insulating layer, and a capacitance element having no variation in capacitance can be obtained.

【0016】さらに、本発明の多層配線基板によれば、
容量素子を形成した絶縁層を、配線導体間の方向の比誘
電率がこれに直交する方向の比誘電率の1.2倍以上のも
のとしたことから、絶縁層に含有する誘電体粉末の比誘
電率を配線導体間の方向で効率的に発現させることがで
き、その結果、この絶縁層を配線導体で対向挟持するこ
とにより、静電容量の大きな容量素子を得ることができ
る。
Further, according to the multilayer wiring board of the present invention,
Since the dielectric layer in which the capacitive element is formed has a relative dielectric constant of at least 1.2 times the relative dielectric constant in the direction between the wiring conductors in the direction orthogonal to the wiring conductor, the relative dielectric constant of the dielectric powder contained in the insulating layer is The ratio can be efficiently developed in the direction between the wiring conductors. As a result, by sandwiching the insulating layer between the wiring conductors, a capacitance element having a large capacitance can be obtained.

【0017】また、本発明の電子部品モジュールによれ
ば、上記の多層配線基板に電子部品を実装し、回路素子
として容量素子と電子部品とを含む電気的な回路を構成
したことから、多層配線基板に半導体素子や容量素子・
抵抗素子等の電子部品を搭載して混成集積回路装置等の
電子部品モジュールを製作する場合に、多層配線基板に
別途、容量素子を多数実装する必要はなく、その結果、
多層配線基板に実装される部品の数が減り、電子部品モ
ジュールを小型化することができる。
Further, according to the electronic component module of the present invention, since the electronic component is mounted on the above-mentioned multilayer wiring board and an electric circuit including the capacitor element and the electronic component is configured as a circuit element, the multilayer wiring board is formed. Semiconductor elements and capacitance elements
When electronic components such as a hybrid integrated circuit device are manufactured by mounting electronic components such as resistive elements, it is not necessary to separately mount a large number of capacitive elements on a multilayer wiring board.
The number of components mounted on the multilayer wiring board is reduced, and the size of the electronic component module can be reduced.

【0018】[0018]

【発明の実施の形態】次に本発明の多層配線基板および
これを用いた電子部品モジュールを添付の図面に基づい
て詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a multilayer wiring board of the present invention and an electronic component module using the same will be described in detail with reference to the accompanying drawings.

【0019】図1は、本発明の多層配線基板に、電子部
品として半導体素子を搭載した場合の電子部品モジュー
ルの一例を示す断面図である。この図において1は絶縁
基体、2は配線導体、3は半導体素子等の電子部品で、
主に絶縁基体1と配線導体2とで本発明の多層配線基板
4が構成され、また、主に多層配線基板4と電子部品3
とで本発明の電子部品モジュール5が構成されている。
FIG. 1 is a sectional view showing an example of an electronic component module when a semiconductor element is mounted as an electronic component on the multilayer wiring board of the present invention. In this figure, 1 is an insulating base, 2 is a wiring conductor, 3 is an electronic component such as a semiconductor element,
The multilayer wiring board 4 of the present invention is mainly composed of the insulating base 1 and the wiring conductor 2.
Thus, the electronic component module 5 of the present invention is configured.

【0020】絶縁基体1は、本例では5層の有機材料か
ら成る絶縁層1a・1b・1c・1d・1eが積層されて構成され
ており、絶縁基体1表面には、半導体素子等の電子部品
3が半田等の接続材6を介して接続固定される。また、
配線導体2は、本例では各絶縁層1a・1b・1c・1d・1e表
面に形成された配線導体層2aと各絶縁層1a・1b・1c・1d
・1eを貫通して各配線導体層2aを電気的に接続する貫通
導体2bとから構成されている。さらに、本例では、絶縁
基体1を構成する絶縁層1a・1b・1c・1d・1eのうち少な
くとも一層(この図の例では絶縁層1c)は、導電性樹脂
粉末および比誘電率が20以上の誘電体粉末を含有してお
り、さらに絶縁層1cをその上下面に被着した配線導体層
2aで対向挟持することにより容量素子Aを形成してい
る。
In this embodiment, the insulating substrate 1 is formed by laminating insulating layers 1a, 1b, 1c, 1d, and 1e made of five organic materials. The component 3 is connected and fixed via a connecting material 6 such as solder. Also,
In this example, the wiring conductor 2 includes a wiring conductor layer 2a formed on the surface of each of the insulating layers 1a, 1b, 1c, 1d, and 1e and the insulating layers 1a, 1b, 1c, and 1d.
A through conductor 2b that penetrates 1e and electrically connects each wiring conductor layer 2a. Furthermore, in this example, at least one of the insulating layers 1a, 1b, 1c, 1d, and 1e (the insulating layer 1c in this example) constituting the insulating base 1 has a conductive resin powder and a relative dielectric constant of 20 or more. Wiring conductor layer containing dielectric powder of
Capacitor element A is formed by being sandwiched in opposition in 2a.

【0021】絶縁基体1は、半導体素子等の電子部品3
を支持する支持体としての機能を有し、この絶縁基体1
を構成する絶縁層1a・1b・1c・1d・1eは有機材料により
形成されている。
The insulating substrate 1 is made of an electronic component 3 such as a semiconductor element.
Has a function as a support for supporting the insulating substrate 1
The insulating layers 1a, 1b, 1c, 1d, and 1e constituting the above are formed of an organic material.

【0022】絶縁層1a・1b・1c・1d・1eを形成する有機
材料としては、エポキシ樹脂やフェノール樹脂・ポリイ
ミド樹脂・熱硬化性ポリフェニレンエーテル樹脂・ビス
マレイミドトリアジン樹脂等の熱硬化性樹脂や液晶ポリ
エステルやフッ素樹脂・ポリフェニレンエーテル樹脂・
ポリエステル樹脂等の熱可塑性樹脂が用いられ、とりわ
け、絶縁層1a・1b・1c・1d・1eを形成する際の作業性・
絶縁層1a・1b・1c・1d・1eの絶縁特性・耐熱特性・機械
的特性等の観点からは、エポキシ樹脂・ポリイミド樹脂
・熱硬化性ポリフェニレンエーテル樹脂等の熱硬化性樹
脂が用いられることが好ましい。
As the organic material forming the insulating layers 1a, 1b, 1c, 1d, 1e, a thermosetting resin such as an epoxy resin, a phenol resin, a polyimide resin, a thermosetting polyphenylene ether resin, a bismaleimide triazine resin, or a liquid crystal is used. Polyester, fluororesin, polyphenylene ether resin,
A thermoplastic resin such as a polyester resin is used, and in particular, workability when forming the insulating layers 1a, 1b, 1c, 1d, 1e
From the viewpoint of the insulating properties, heat resistance properties, mechanical properties, etc. of the insulating layers 1a, 1b, 1c, 1d, 1e, thermosetting resins such as epoxy resins, polyimide resins, and thermosetting polyphenylene ether resins may be used. preferable.

【0023】また、絶縁層1a・1b・1d・1eには、熱膨張
変化を小さくする目的、あるいは機械的強度を向上する
目的で必要に応じて酸化アルミニウム・窒化珪素・窒化
アルミニウム・炭化珪素・酸化チタン・酸化バリウム・
酸化ストロンチウム・酸化ジルコニウム・酸化カルシウ
ム・ゼオライト等の無機絶縁粉末、あるいは、繊維状ガ
ラスを布状に織り込んだガラスクロス等を含有させても
よい。
The insulating layers 1a, 1b, 1d, and 1e may be provided with aluminum oxide, silicon nitride, aluminum nitride, silicon carbide, or the like as necessary for the purpose of reducing the change in thermal expansion or improving the mechanical strength. Titanium oxide, barium oxide,
An inorganic insulating powder such as strontium oxide, zirconium oxide, calcium oxide, or zeolite, or a glass cloth in which fibrous glass is woven into a cloth may be contained.

【0024】このような絶縁基体1は、例えば粒径が0.
1〜15μm程度の酸化アルミニウム・窒化珪素・窒化ア
ルミニウム・炭化珪素・酸化チタン・酸化バリウム・酸
化ストロンチウム・酸化ジルコニウム・酸化カルシウム
等の無機絶縁粉末に、エポキシ樹脂・フェノール樹脂・
ポリイミド樹脂・ビスマレイミド樹脂・熱硬化性ポリフ
ェニレンエーテル樹脂等の熱硬化性樹脂または液晶ポリ
エステル・ポリフェニレンエーテル樹脂等の熱可塑性樹
脂と溶剤・可塑剤・分散剤等を添加して得たペーストを
従来周知のドクタブレード法等のシート成型法を採用し
てシート状となすことによって絶縁基体1における絶縁
層1a・1b・1d・1eとなる複数の前駆体シートを得るとと
もにこの絶縁層1a・1b・1d・1eとなる前駆体シートと後
述する絶縁層1cとなる前駆体シートの各々に必要に応じ
て適当な打ち抜き加工を従来周知のパンチング法を採用
して施し、これらの打ち抜き加工が施された絶縁層1a・
1b・1c・1d・1eを所定の順に積層圧着し、最後に、積層
圧着された絶縁層1a・1b・1c・1d・1eを温度が約100〜3
00℃で圧力が0.4〜10MPaの条件で30分〜24時間ホッ
トプレスして加熱硬化させることによって製作される。
Such an insulating substrate 1 has, for example, a particle size of 0.1.
Inorganic insulating powder such as aluminum oxide, silicon nitride, aluminum nitride, silicon carbide, titanium oxide, barium oxide, strontium oxide, zirconium oxide, calcium oxide, etc.
Conventionally known pastes obtained by adding a thermosetting resin such as polyimide resin, bismaleimide resin, thermosetting polyphenylene ether resin, or a thermoplastic resin such as liquid crystal polyester or polyphenylene ether resin and a solvent, plasticizer, dispersant, etc. By forming a sheet by adopting a sheet forming method such as the doctor blade method, a plurality of precursor sheets to be the insulating layers 1a, 1b, 1d, and 1e in the insulating base 1 are obtained, and the insulating layers 1a, 1b, and 1d are obtained. A suitable punching process is applied to each of the precursor sheet to be 1e and a precursor sheet to be an insulating layer 1c to be described later by using a conventionally well-known punching method as necessary, and the insulating material subjected to these punching processes is applied. Layer 1a
1b, 1c, 1d, 1e are laminated and crimped in a predetermined order, and finally, the laminated and crimped insulating layers 1a, 1b, 1c, 1d, 1e are heated to a temperature of about 100 to 3
It is manufactured by hot-pressing at 00 ° C. under a pressure of 0.4 to 10 MPa for 30 minutes to 24 hours to heat and cure.

【0025】また、絶縁層1cは、1〜30体積%の導電性
樹脂粉末と、10〜70体積%の比誘電率が20以上の誘電体
粉末と、10〜89体積%の有機材料とから成り、絶縁層1c
をその上下両面に被着した配線導体層2aで対向挟持する
ことにより容量素子Aを形成している。
The insulating layer 1c is composed of 1 to 30% by volume of a conductive resin powder, 10 to 70% by volume of a dielectric powder having a relative dielectric constant of 20 or more, and 10 to 89% by volume of an organic material. Consisting of an insulating layer 1c
Are sandwiched between the wiring conductor layers 2a attached to the upper and lower surfaces thereof to form the capacitive element A.

【0026】本発明の多層配線基板4によれば、絶縁層
1a・1b・1c・1d・1eの少なくとも一層に導電性樹脂粉末
および比誘電率が20以上の誘電体粉末を含有させたこと
から、この絶縁層1cを配線導体層2aで対向挟持して形成
した容量素子Aに外部から電圧を印加した場合、導電性
樹脂粉末が電気伝導性のために電荷を効率よく分離して
導体としての役目を果たし、導電性樹脂粉末の絶縁層1c
の厚み方向の長さ分だけ静電容量に寄与する絶縁層1cの
厚みを実質的に減少させることができ、その結果、絶縁
層1cの厚みを極端に薄くしなくともその静電容量を所望
の大きなものとして容量素子Aを形成する対向電極の面
積を小さなものとすることができ、多層配線基板4を小
型化することが可能となる。
According to the multilayer wiring board 4 of the present invention, the insulating layer
Since at least one of the layers 1a, 1b, 1c, 1d, and 1e contains a conductive resin powder and a dielectric powder having a relative dielectric constant of 20 or more, the insulating layer 1c is formed by being sandwiched between the wiring conductor layers 2a. When a voltage is applied to the capacitive element A from the outside, the conductive resin powder efficiently separates electric charges due to electric conductivity and serves as a conductor, and the insulating layer 1c of the conductive resin powder.
The thickness of the insulating layer 1c, which contributes to the capacitance by the length in the thickness direction of the insulating layer 1c, can be substantially reduced. As a result, the desired capacitance can be obtained without making the thickness of the insulating layer 1c extremely thin. As a result, the area of the counter electrode forming the capacitive element A can be reduced, and the multilayer wiring board 4 can be reduced in size.

【0027】これは、容量素子Aの静電容量CがC=ε
ε0(S/d)(ただし、dは絶縁層1cの厚み、Sは対
向電極の面積、εは絶縁層1cの比誘電率、ε0は真空の
誘電率を示す)で表され、導電性樹脂粉末の絶縁層1cの
厚み方向の長さ分だけ静電容量に寄与する絶縁層1cの厚
みdが実質的に減少することにより静電容量Cが大きく
なることによるものである。
This is because the capacitance C of the capacitive element A is C = ε.
ε 0 (S / d) (where d is the thickness of the insulating layer 1c, S is the area of the counter electrode, ε is the relative permittivity of the insulating layer 1c, and ε 0 is the permittivity of a vacuum), This is because the capacitance C is increased by substantially reducing the thickness d of the insulating layer 1c that contributes to the capacitance by the length in the thickness direction of the insulating layer 1c of the conductive resin powder.

【0028】本発明の多層配線基板4によれば、絶縁層
1cに導電性樹脂粉末を含有させたことから、静電容量の
大きな容量素子Aを得るために絶縁層1cの膜厚を極端に
薄くする必要はなく、その結果、絶縁層1cを形成する前
駆体シートの強度が弱くなってシート形成ができなくな
ったり、あるいは誘電体粉末の分散が不均一となり絶縁
層1cの比誘電率の分布にムラができて均一な静電容量を
得ることができないということもない。
According to the multilayer wiring board 4 of the present invention, the insulating layer
Since the conductive resin powder is contained in 1c, it is not necessary to make the thickness of the insulating layer 1c extremely thin in order to obtain the capacitive element A having a large capacitance. As a result, the precursor for forming the insulating layer 1c is not required. That the strength of the body sheet becomes weak and the sheet cannot be formed, or that the distribution of the dielectric powder becomes uneven and the distribution of the relative permittivity of the insulating layer 1c becomes uneven, so that a uniform capacitance cannot be obtained. Not even.

【0029】絶縁層1cの導電性樹脂粉末は、その体積含
有率が絶縁層1cに対して1体積%未満となると、絶縁層
1cの静電容量を大きくするという効果が得られなくなる
傾向がある。また、30体積%を越えると導電性樹脂粉末
同士が接触して絶縁層1cの絶縁抵抗を低下させてしまう
傾向がある。従って、導電性樹脂粉末の体積含有率は1
〜30体積%の範囲とすることが好ましく、絶縁信頼性を
より高めるためには1〜10体積%の範囲とすることが好
ましい。
When the volume content of the conductive resin powder of the insulating layer 1c becomes less than 1% by volume with respect to the insulating layer 1c, the insulating layer
The effect of increasing the capacitance of 1c tends not to be obtained. On the other hand, when the content exceeds 30% by volume, the conductive resin powders tend to come into contact with each other to lower the insulation resistance of the insulating layer 1c. Therefore, the volume content of the conductive resin powder is 1
It is preferably in the range of 30 to 30% by volume, and more preferably in the range of 1 to 10% by volume in order to further improve insulation reliability.

【0030】また、導電性樹脂粉末の平均粒径は、0.1
〜15μmの範囲であることが好ましい。平均粒径が 0.1
μm未満であるとその比表面積が大きくなって導電性樹
脂粉末を添加混合した混練物の粘度が高いものとなり、
その結果、絶縁層1cを形成する際に絶縁層1cの厚みが不
均一となり、所定の均一厚みとすることが困難となる傾
向がある。また、15μmを超えると絶縁層1cの表面に導
電性樹脂粉末による凹凸が形成され、容量素子Aが形成
される領域における比誘電率にバラツキを生じたり、絶
縁層1cに打抜き加工を施す際の加工精度が低下してしま
う傾向がある。従って、絶縁層1cに含有される導電性樹
脂粉末は、その平均粒径を0.1〜15μmの範囲とするこ
とが好ましく、好適には0.3〜10μmの範囲とすること
が好ましい。
The average particle size of the conductive resin powder is 0.1
It is preferably in the range of 1515 μm. Average particle size 0.1
If it is less than μm, the specific surface area becomes large, and the viscosity of the kneaded product obtained by adding and mixing the conductive resin powder becomes high,
As a result, when the insulating layer 1c is formed, the thickness of the insulating layer 1c tends to be non-uniform, and it tends to be difficult to achieve a predetermined uniform thickness. On the other hand, if the thickness exceeds 15 μm, irregularities due to the conductive resin powder are formed on the surface of the insulating layer 1c, causing a variation in the relative dielectric constant in a region where the capacitor A is formed, or when performing punching on the insulating layer 1c. Processing accuracy tends to decrease. Therefore, the conductive resin powder contained in the insulating layer 1c preferably has an average particle size in the range of 0.1 to 15 μm, and more preferably 0.3 to 10 μm.

【0031】なお、ここで導電性樹脂粉末とは、電気伝
導度が1×103S/cm以上である有機樹脂粉末を指す。
Here, the conductive resin powder refers to an organic resin powder having an electric conductivity of 1 × 10 3 S / cm or more.

【0032】このような導電性樹脂粉末としては、ポリ
アセチレンやフェニルアセチレン・ポリ(1,6-ヘプタジ
イン)などのポリアセチレン系高分子、ポリピロール・
ポリチオフェン・ポリフラン・ポリセレノフェン・ポリ
テルロフェン等の複素環高分子、ポリアニリン・ポリ
(3-メチル,4-カルボキシピロール)等のイオン性高分
子、ポリアセン・ポリアセナセン・ポリペリナフタレン
・ポリペリアントラセン等のラダー状高分子等が用いら
れる。
Examples of the conductive resin powder include polyacetylene polymers such as polyacetylene and phenylacetylene / poly (1,6-heptadiyne), and polypyrrole / polypyrrole.
Heterocyclic polymers such as polythiophene / polyfuran / polyselenophene / polytellurophen; ionic polymers such as polyaniline / poly (3-methyl, 4-carboxypyrrole); polyacene / polyacenacene / polyperinaphthalene / polyperianthracene And the like are used.

【0033】また、絶縁層1cに含有される誘電体粉末と
しては、酸化チタン・酸化バリウム・酸化ストロンチウ
ム・酸化ジルコニウム・酸化カルシウム等の無機系誘電
体粉末やこれらの化合物・混合物、チタン酸カリウムウ
ィスカ・ホウ酸アルミニウムウィスカ・針状酸化チタン
・シリカアルミナ繊維・アルミナ繊維等の繊維状高誘電
体粉末、チタン酸バリウム・チタン酸カルシウム・スズ
酸バリウム・ジルコン酸バリウム・ジルコン酸ストロン
チウム等の高誘電体粉末が用いられ、その比誘電率が20
(室温1MHz)よりも小さいと、絶縁層1cの比誘電率
が小さくなって容量素子Aの容量値が実用に供すること
ができない小さな値となってしまう傾向がある。従っ
て、絶縁層1cに含有される誘電体粉末は、その比誘電率
を20(室温1MHz)以上とすることが好ましい。
Examples of the dielectric powder contained in the insulating layer 1c include inorganic dielectric powders such as titanium oxide, barium oxide, strontium oxide, zirconium oxide, and calcium oxide, compounds and mixtures thereof, and potassium titanate whiskers.・ Aluminum borate whisker ・ Acicular titanium oxide ・ Silica alumina fiber ・ Fibrous high dielectric powder such as alumina fiber, barium titanate ・ Calcium titanate ・ Barium stannate ・ Barium zirconate ・ Strontium zirconate etc. Powder is used and has a dielectric constant of 20
If it is lower than (room temperature 1 MHz), the relative dielectric constant of the insulating layer 1c tends to be small, and the capacitance of the capacitor A tends to be too small to be practically used. Accordingly, the dielectric powder contained in the insulating layer 1c preferably has a relative dielectric constant of 20 (room temperature 1 MHz) or more.

【0034】絶縁層1cの誘電体粉末は、その体積含有率
が絶縁層1cに対して10体積%未満となると絶縁層1cの比
誘電率が小さくなり、実用に供することができる容量素
子Aを形成するのが困難となる傾向がある。また、70体
積%を超えると有機材料との混練性が悪くなり、絶縁層
1cを形成することが困難となる傾向がある。従って、誘
電体粉末の体積含有率は10〜70体積%の範囲とすること
が好ましい。
When the volume content of the dielectric powder of the insulating layer 1c is less than 10% by volume with respect to the insulating layer 1c, the relative permittivity of the insulating layer 1c becomes small, and the capacitance element A which can be practically used is obtained. It tends to be difficult to form. On the other hand, if the content exceeds 70% by volume, the kneadability with the organic material deteriorates, and
Forming 1c tends to be difficult. Therefore, the volume content of the dielectric powder is preferably in the range of 10 to 70% by volume.

【0035】なお、誘電体粉末の平均粒径は、前述した
導電性樹脂粉末と同じ理由で、0.1〜15μmの範囲とす
ることが好ましく、好適には0.3〜10μmの範囲とする
ことが好ましい。
The average particle size of the dielectric powder is preferably in the range of 0.1 to 15 μm, more preferably 0.3 to 10 μm, for the same reason as the conductive resin powder described above.

【0036】また、絶縁層1cの有機材料は、その体積含
有率が絶縁層1cに対して10体積%未満であるとシートの
成形性が悪くなり、絶縁層1cを形成することが困難とな
る傾向がある。また、89体積%を越えると、上述したよ
うに導電性樹脂粉末および誘電体粉末の含有量が少なく
なって絶縁層1cの比誘電率が小さくなり、実用に供する
ことができる容量素子Aを形成することが困難となる傾
向がある。従って、絶縁層1cの有機材料の体積含有率は
10〜89体積%の範囲とすることが好ましい。
When the volume content of the organic material of the insulating layer 1c is less than 10% by volume with respect to the insulating layer 1c, the formability of the sheet becomes poor, and it becomes difficult to form the insulating layer 1c. Tend. On the other hand, if the content exceeds 89% by volume, the content of the conductive resin powder and the dielectric powder is reduced as described above, and the relative dielectric constant of the insulating layer 1c is reduced. Tends to be difficult. Therefore, the volume content of the organic material in the insulating layer 1c is
It is preferable to be in the range of 10 to 89% by volume.

【0037】本発明の多層配線基板4によれば、上記の
ように導電性樹脂粉末および誘電体粉末を含有する絶縁
層1cを、1〜30体積%の導電性樹脂粉末と、10〜70体積
%の比誘電率が20以上誘電体粉末と、10〜89体積%の有
機材料とから構成したことから、導電性樹脂粉末および
誘電体粉末を絶縁層中に均一に分散させることができ、
静電容量のムラのない容量素子Aを得ることができる。
According to the multilayer wiring board 4 of the present invention, as described above, the insulating layer 1c containing the conductive resin powder and the dielectric powder is mixed with 1 to 30% by volume of the conductive resin powder and 10 to 70% by volume. % Of the dielectric powder and the organic material of 10 to 89% by volume, the conductive resin powder and the dielectric powder can be uniformly dispersed in the insulating layer.
It is possible to obtain the capacitance element A without uneven capacitance.

【0038】また、絶縁層1cは容量素子Aを形成する対
向電極間の方向の比誘電率がこれに直交する方向の比誘
電率の1.2倍以上であることが好ましい。
It is preferable that the relative dielectric constant of the insulating layer 1c in the direction between the opposing electrodes forming the capacitive element A be 1.2 times or more the relative dielectric constant in the direction perpendicular to the direction.

【0039】絶縁層1cは、対向電極間の方向の比誘電率
をこれに直交する方向の比誘電率の1.2倍以上とするこ
とにより、絶縁層1cに含有される誘電体粉末の双極子モ
ーメントの方向も容易に対向電極間の方向に揃えること
ができ、誘電体粉末の比誘電率を対向電極間の方向で十
分に発現させることが可能となる。なお、対向電極間の
方向の比誘電率がこれに直交する方向の比誘電率の1.2
倍未満であると、誘電体粉末の双極子モーメントの方向
が揃いにくくなり、誘電体粉末の比誘電率を対向電極間
の方向で十分に発現させることが困難となる傾向にあ
る。従って、絶縁層1cは対向電極間の方向の比誘電率が
これに直交する方向の比誘電率の1.2倍以上であること
が好ましい。
The insulating layer 1c has a relative dielectric constant in the direction between the opposing electrodes of 1.2 times or more as large as the relative dielectric constant in a direction perpendicular to the opposite electrode, so that the dipole moment of the dielectric powder contained in the insulating layer 1c is increased. Can easily be aligned with the direction between the opposing electrodes, and the relative dielectric constant of the dielectric powder can be sufficiently developed in the direction between the opposing electrodes. The relative permittivity in the direction between the opposing electrodes is 1.2 times the relative permittivity in the direction orthogonal to the direction.
If the ratio is less than twice, the directions of the dipole moments of the dielectric powder become difficult to be uniform, and it tends to be difficult to sufficiently develop the relative permittivity of the dielectric powder in the direction between the opposed electrodes. Therefore, it is preferable that the relative permittivity of the insulating layer 1c in the direction between the opposing electrodes is 1.2 times or more the relative permittivity in the direction orthogonal to the opposite electrode.

【0040】このような絶縁層1cに用いられる有機材料
としては、エポキシ樹脂やフェノール樹脂・ポリイミド
樹脂・熱硬化性ポリフェニレンエーテル樹脂・ビスマレ
イミドトリアジン樹脂等の熱硬化性樹脂や液晶ポリエス
テルやフッ素樹脂・ポリフェニレンエーテル樹脂・ポリ
エステル樹脂等の熱可塑性樹脂が用いられ、とりわけ、
有機材料の分子中に配向性部位を有するとともに主軸方
向の比誘電率εpと主軸方向と直交する比誘電率εvの比
εpvが1.2以上であるものが好ましい。
As the organic material used for the insulating layer 1c, a thermosetting resin such as an epoxy resin, a phenol resin, a polyimide resin, a thermosetting polyphenylene ether resin, a bismaleimide triazine resin, a liquid crystal polyester, a fluororesin, etc. Thermoplastic resins such as polyphenylene ether resin and polyester resin are used,
It is preferable that the organic material has an oriented site in the molecule and has a ratio ε p / ε v of the relative permittivity ε p in the main axis direction and the relative permittivity ε v orthogonal to the main axis direction of 1.2 or more.

【0041】ここで配向性部位とは、主に剛直性のパラ
置換の芳香族環や直線性のビフェニル、シクロヘキシル
系・置換ナフチル系の芳香族環から成るものであり、分
子中にこれらの配向性部位を有することにより、分子は
細長い棒状あるいは平板状となり良好な配向性を有する
こととなる。
Here, the orienting site mainly comprises a rigid para-substituted aromatic ring or a linear biphenyl or cyclohexyl / substituted naphthyl aromatic ring. By having a sexual site, the molecule becomes elongated rod-like or plate-like and has good orientation.

【0042】また、分子の主軸方向とは、分子の比誘電
率が一番高く発現される方向であり、通常は分子中の原
子が一番長く連なっている主鎖方向である。さらに、分
子の直交する方向とは直交する全ての方向を示す。
The principal axis direction of a molecule is the direction in which the relative dielectric constant of the molecule is expressed highest, and is usually the direction of the main chain in which the atoms in the molecule are the longest. Further, the direction orthogonal to the molecule indicates all directions orthogonal to each other.

【0043】なお、絶縁層1cの有機材料のεpvが1.2
未満であると後述するように外部より直流の高電圧を印
加しても主軸方向を対向電極間の方向に揃えることが困
難になり、対向電極間の方向の比誘電率がこれに直交す
る方向の比誘電率の1.2倍以上とすることが困難となる
傾向がある。従って、絶縁層1cの有機材料のεpv
1.2以上であることが好ましい。
Note that ε p / ε v of the organic material of the insulating layer 1c is 1.2
If it is less than this, it will be difficult to align the main axis direction to the direction between the opposing electrodes even if a high DC voltage is applied from outside as described later, and the relative permittivity in the direction between the opposing electrodes will be orthogonal to the direction. There is a tendency that it is difficult to make the relative permittivity 1.2 times or more of the above. Therefore, ε p / ε v of the organic material of the insulating layer 1c is
It is preferably 1.2 or more.

【0044】絶縁層1cは、例えば、平均粒径が0.1〜15
μm程度のチタン酸バリウムやチタン酸カルシウム・ス
ズ酸バリウム・ジルコン酸バリウム・ジルコン酸ストロ
ンチウム等の誘電体粉末に、エポキシ樹脂・フェノール
樹脂・ポリイミド樹脂・ビスマレイミド樹脂・熱硬化性
ポリフェニレンエーテル樹脂等の熱硬化性樹脂あるいは
液晶ポリエステル・ポリフェニレンエーテル系樹脂等の
熱可塑性樹脂と、適当な溶剤・可塑剤・分散剤等を添加
して得たペーストを従来周知のドクタブレード法等のシ
ート形成法を採用してシート状となすとともに、60〜10
0℃の温度で5分〜3時間加熱して絶縁層1cとなる半硬
化状の前駆体シートを得、さらに半硬化状の前駆体シー
トの上下面にめっき法や金属箔を転写する転写法等を採
用して金属電極を被着させ、この金属電極間に60〜100
℃の温度で1〜20KV/mmの直流電圧を30分〜24時間
印加することにより有機材料の分子を直流電圧を印加し
た方向に配向させ、最後に、金属電極をエッチングやラ
ッピングにより取り除くことにより、絶縁層1cの前駆体
シートが製作される。
The insulating layer 1c has, for example, an average particle size of 0.1 to 15
Dielectric powders such as barium titanate, calcium titanate, barium stannate, barium zirconate, strontium zirconate, etc. Adopts a paste obtained by adding a thermosetting resin or a thermoplastic resin such as liquid crystal polyester or polyphenylene ether-based resin and a suitable solvent, plasticizer, dispersant, etc., using a sheet forming method such as the well-known doctor blade method. To make a sheet, and 60 to 10
Heating at a temperature of 0 ° C. for 5 minutes to 3 hours to obtain a semi-cured precursor sheet to be the insulating layer 1c, and a plating method or a transfer method of transferring a metal foil to the upper and lower surfaces of the semi-cured precursor sheet. Etc., and a metal electrode is adhered.
By applying a DC voltage of 1 to 20 KV / mm at a temperature of 30 ° C. for 30 minutes to 24 hours, the molecules of the organic material are oriented in the direction to which the DC voltage is applied, and finally, the metal electrode is removed by etching or lapping. Then, a precursor sheet for the insulating layer 1c is manufactured.

【0045】さらに、絶縁層1cには熱膨張変化を小さく
する目的、あるいは機械的強度を向上する目的で、必要
に応じて酸化アルミニウム・窒化珪素・窒化アルミニウ
ム・炭化珪素・酸化チタン・酸化バリウム・酸化ストロ
ンチウム・酸化ジルコニウム・酸化カルシウム・ゼオラ
イト等の無機絶縁粉末、あるいは、繊維状ガラスを布状
に織り込んだガラスクロス等を含有させてもよい。
Further, for the purpose of reducing the change in thermal expansion or improving the mechanical strength, the insulating layer 1c may be made of aluminum oxide, silicon nitride, aluminum nitride, silicon carbide, titanium oxide, barium oxide, An inorganic insulating powder such as strontium oxide, zirconium oxide, calcium oxide, or zeolite, or a glass cloth in which fibrous glass is woven into a cloth may be contained.

【0046】また、絶縁基体1を構成する絶縁層1a・1b
・1c・1d・1eでは、有機材料と無機絶縁粉末の親和性を
高め、これらの接合性向上と絶縁基体1の機械的強度を
高める目的で、絶縁層1a・1b・1c・1d・1eにシラン系カ
ップリング剤やチタネート系カップリング剤等のカップ
リング剤を1種類以上添加してもよい。
The insulating layers 1a and 1b constituting the insulating base 1
In 1c ・ 1d ・ 1e, the insulating layers 1a ・ 1b ・ 1c ・ 1d ・ 1e are used to increase the affinity between the organic material and the inorganic insulating powder, to improve their bonding properties and to increase the mechanical strength of the insulating substrate 1. One or more coupling agents such as a silane coupling agent and a titanate coupling agent may be added.

【0047】さらに、絶縁層1a・1b・1c・1d・1eからな
る絶縁基体1には、絶縁層1a・1b・1c・1d・1e表面に配
線導体層2aおよび各配線導体層2a同士を電気的に接続す
る貫通導体2bが形成されている。
Further, the insulating base 1 composed of the insulating layers 1a, 1b, 1c, 1d, and 1e is provided on the surface of the insulating layers 1a, 1b, 1c, 1d, and 1e with the wiring conductor layers 2a and the respective wiring conductor layers 2a electrically connected to each other. A through conductor 2b is formed to be electrically connected.

【0048】配線導体層2aおよび貫通導体2bから成る配
線導体2は、多層配線基板4に実装される半導体素子等
の電子部品3を外部電気回路(図示せず)に電気的に接
続する機能を有するとともに、絶縁層1cをその上下両面
に被着された配線導体層2aで対向挟持することにより容
量素子Aを形成する機能を有する。
The wiring conductor 2 composed of the wiring conductor layer 2a and the through conductor 2b has a function of electrically connecting an electronic component 3 such as a semiconductor element mounted on the multilayer wiring board 4 to an external electric circuit (not shown). And a function of forming the capacitive element A by sandwiching the insulating layer 1c between the wiring conductor layers 2a attached to the upper and lower surfaces thereof.

【0049】このような配線導体層2aは、絶縁基体1に
おける絶縁層1a・1b・1c・1d・1eとなる複数の前駆体シ
ートに、銅・銀・金等の低抵抗金属を従来周知のスクリ
ーン印刷法により形成する方法や、パターン形成した銅
・金等から成る金属箔を転写法等により被着形成する方
法・無電解めっき法・蒸着法・スパッタリング法等の薄
膜形成方法を採用することにより形成される。
Such a wiring conductor layer 2a is formed by adding a low-resistance metal such as copper, silver, or gold to a plurality of precursor sheets serving as the insulating layers 1a, 1b, 1c, 1d, and 1e in the insulating base 1. Adopt a method of forming by screen printing, a method of depositing and forming a metal foil composed of patterned copper, gold, etc. by a transfer method, etc., adopt a thin film forming method such as electroless plating, vapor deposition, sputtering, etc. Formed by

【0050】なお、本発明の多層配線基板4では、配線
導体層2aを薄膜で形成したことから配線の微細化が可能
となり、配線を極めて高密度に形成することができ、小
型の多層配線基板4とすることができる。
In the multilayer wiring board 4 of the present invention, since the wiring conductor layer 2a is formed of a thin film, the wiring can be miniaturized. 4 can be set.

【0051】また、貫通導体2bは、絶縁層1a・1b・1c・
1d・1eとなる複数の前駆体シートにパンチング法等によ
り打抜き加工を施した後、この貫通孔に銅・銀・金等か
ら成る導電性ペーストをスクリーン印刷法等により埋め
込むことにより形成される。
The through conductor 2b is formed of the insulating layers 1a, 1b, 1c,
After a plurality of precursor sheets 1d and 1e are punched by a punching method or the like, a conductive paste made of copper, silver, gold, or the like is embedded in the through holes by a screen printing method or the like.

【0052】なお、配線導体層2a・貫通導体2bは、その
露出する表面にニッケル・金等の耐蝕性に優れ、かつ良
導電性の金属をめっき法により1.0〜20μmの厚みに被
着させておくと配線導体層2a・貫通導体2bの酸化腐蝕を
有効に防止することができるとともに配線導体層2a・貫
通導体2bと半導体素子等の電子部品3や外部電気回路の
配線導体(図示せず)とを強固に電気的に接続させるこ
とができる。従って、配線導体層2a・貫通導体2bの露出
する表面には、ニッケルや金等の耐蝕性に優れ、かつ良
導電性の金属をめっき法により1.0〜20μmの厚みに被
着させておくことが好ましい。
The wiring conductor layer 2a and the penetrating conductor 2b are formed by coating a metal having excellent corrosion resistance, such as nickel and gold, and having good conductivity with a thickness of 1.0 to 20 μm by plating on the exposed surface. In addition, it is possible to effectively prevent the oxidative corrosion of the wiring conductor layer 2a and the through conductor 2b, and at the same time, the wiring conductor of the electronic component 3 such as the semiconductor element and the external electric circuit (not shown). Can be firmly and electrically connected. Therefore, on the exposed surfaces of the wiring conductor layer 2a and the through conductor 2b, a metal having excellent corrosion resistance such as nickel or gold and having good conductivity is preferably applied to a thickness of 1.0 to 20 μm by plating. preferable.

【0053】本発明の多層配線基板4によれば、このよ
うな容量素子Aを形成したことから、多層配線基板4に
半導体素子や容量素子・抵抗素子等の電子部品3を搭載
して混成集積回路装置等の電子部品モジュール5を製作
する場合に、多層配線基板4に別途、容量素子Aを多数
実装する必要はなく、その結果、多層配線基板4に実装
される部品の数が減り、電子部品モジュール5を小型化
することができる。
According to the multilayer wiring board 4 of the present invention, since such a capacitive element A is formed, the electronic component 3 such as a semiconductor element, a capacitive element, and a resistive element is mounted on the multilayer wiring board 4 to form a hybrid integrated circuit. When manufacturing an electronic component module 5 such as a circuit device, it is not necessary to separately mount a large number of capacitive elements A on the multilayer wiring board 4, and as a result, the number of components mounted on the multilayer wiring board 4 decreases, and The component module 5 can be downsized.

【0054】このような容量素子Aの容量値は、多層配
線基板4に要求される機能により決定され、導電性樹脂
粉末および誘電体粉末の含有量や含有される誘電体粉末
の比誘電率・絶縁層1cの厚み・容量素子Aを形成する配
線導体2の面積等を適宜決めることにより決定される。
The capacitance value of such a capacitive element A is determined by the function required of the multilayer wiring board 4, and includes the contents of the conductive resin powder and the dielectric powder, the relative permittivity of the contained dielectric powder, It is determined by appropriately determining the thickness of the insulating layer 1c, the area of the wiring conductor 2 forming the capacitive element A, and the like.

【0055】かくして本発明の多層配線基板4によれ
ば、容量素子Aを形成した絶縁層1cに誘電体粉末および
導電性樹脂粉末を含有させたことから、容量素子Aに外
部から電圧を印加した場合、導電性樹脂粉末が電気伝導
性のために電荷を効率よく分離して導体としての役目を
果たし、導電性樹脂粉末の絶縁層1cの厚み方向の長さ分
だけ静電容量に寄与する絶縁層1cの厚みを実質的に減少
させることができ、その結果、絶縁層1cの厚みを極端に
薄くしなくとも絶縁層1cの静電容量を所望の大きなもの
とし、容量素子Aを形成する対向電極の面積を小さなも
のとすることができ多層配線基板4を小型化することが
可能となる。
Thus, according to the multilayer wiring board 4 of the present invention, since the dielectric powder and the conductive resin powder are contained in the insulating layer 1c on which the capacitive element A is formed, a voltage is externally applied to the capacitive element A. In this case, the conductive resin powder efficiently separates electric charges due to electrical conductivity and functions as a conductor, and the insulation that contributes to the capacitance by the length in the thickness direction of the insulating layer 1c of the conductive resin powder. The thickness of the layer 1c can be substantially reduced. As a result, the capacitance of the insulating layer 1c can be increased to a desired value without making the thickness of the insulating layer 1c extremely small, and the opposite The area of the electrode can be reduced, and the multilayer wiring board 4 can be reduced in size.

【0056】また、本発明の電子部品モジュール5は、
上記の多層配線基板4表面に被着形成された配線導体2
に半導体素子や容量素子・抵抗素子等の電子部品3の各
電極を接続材6を介して電気的に接続固定することによ
って形成される。
The electronic component module 5 of the present invention
Wiring conductor 2 formed on the surface of the multilayer wiring board 4
Are formed by electrically connecting and fixing the electrodes of the electronic component 3 such as a semiconductor element, a capacitance element and a resistance element via a connection member 6.

【0057】このような接続材6は、金や鉛―錫、錫―
亜鉛、錫―銀―ビスマス等の導電性材料から成り、例え
ば、接続材6が鉛―錫から成る場合、このペーストを多
層配線基板4表面の配線導体2上にスクリーン印刷法で
印刷することにより、配線導体2上に被着形成される。
さらに、電子部品3を接続材6に載置し、リフロー炉を
通し配線導体2と半導体素子や容量素子・抵抗素子等の
電子部品3の各電極とを電気的に接続することにより、
本発明の電子部品モジュール5と成る。
The connecting material 6 is made of gold, lead-tin, tin-
When the connecting material 6 is made of lead-tin, for example, made of a conductive material such as zinc, tin-silver-bismuth, the paste is printed on the wiring conductor 2 on the surface of the multilayer wiring board 4 by screen printing. Is formed on the wiring conductor 2.
Further, the electronic component 3 is placed on the connection member 6, and the wiring conductor 2 is electrically connected to each electrode of the electronic component 3 such as a semiconductor element, a capacitance element, and a resistance element through a reflow furnace.
The electronic component module 5 of the present invention is provided.

【0058】なお、接続材6の保護および電子部品3と
多層配線基板4とを強固に固着するために、電子部品3
と多層配線基板4との間に、熱硬化性樹脂とフィラーと
から成るアンダーフィル材を注入してもよい。
In order to protect the connection member 6 and firmly fix the electronic component 3 to the multilayer wiring board 4, the electronic component 3
An underfill material made of a thermosetting resin and a filler may be injected between the substrate and the multilayer wiring board 4.

【0059】かくして、本発明の電子部品モジュール5
によれば、多層配線基板4に電子部品3を実装し、容量
素子Aを構成する配線導体2と電子部品3とで電気的な
回路を構成したことから、多層配線基板4に半導体素子
や容量素子・抵抗素子等の電子部品3を搭載して混成集
積回路装置等の電子部品モジュール5を製作する場合
に、多層配線基板4に別途、容量素子を多数実装する必
要はなく、その結果、多層配線基板4に実装される部品
の数が減り、電子部品モジュール5を小型化することが
できる。また、例えば電子部品3が半導体素子の場合、
容量素子Aを形成する配線導体2の一方の電極を半導体
素子の電源電極に、他方の電極を半導体素子の接地電極
に接続することにより高周波電源電流の拡散を防止する
デカップリングの強化をすることができ、半導体素子の
誤動作を有効に防止することもできる。
Thus, the electronic component module 5 of the present invention
According to the method, the electronic component 3 is mounted on the multilayer wiring board 4 and an electric circuit is formed by the wiring conductor 2 and the electronic component 3 forming the capacitive element A. When an electronic component module 5 such as a hybrid integrated circuit device is manufactured by mounting the electronic components 3 such as elements and resistance elements, it is not necessary to separately mount a large number of capacitive elements on the multilayer wiring board 4. The number of components mounted on the wiring board 4 is reduced, and the size of the electronic component module 5 can be reduced. Further, for example, when the electronic component 3 is a semiconductor element,
By connecting one electrode of the wiring conductor 2 forming the capacitive element A to the power supply electrode of the semiconductor element and connecting the other electrode to the ground electrode of the semiconductor element, the decoupling for preventing the diffusion of the high frequency power supply current is strengthened. Therefore, malfunction of the semiconductor element can be effectively prevented.

【0060】なお、本発明の多層配線基板4および電子
部品モジュール5は上述の実施例に限定されるものでは
なく、本発明の要旨を逸脱しない範囲であれば種々の変
更は可能であり、例えば、上述の実施例では5層の絶縁
層1a・1b・1c・1d・1eを積層することによって絶縁基体
1を製作したが、3層や4層、あるいは6層以上の絶縁
層を積層して絶縁基体1を製作してもよい。また、上述
の実施例では誘電体粉末および導電性樹脂粉末を含む絶
縁層を1層としたが、2層(連続層を含む)以上として
もよい。
The multilayer wiring board 4 and the electronic component module 5 of the present invention are not limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention. In the above-described embodiment, the insulating base 1 is manufactured by stacking five insulating layers 1a, 1b, 1c, 1d, and 1e. However, three, four, or six or more insulating layers are stacked. The insulating base 1 may be manufactured. Further, in the above-described embodiment, the insulating layer including the dielectric powder and the conductive resin powder is one layer, but may be two or more layers (including a continuous layer).

【0061】また、上述の実施例では容量素子Aは、対
向電極が誘電体粉末および導電性樹脂粉末を含む絶縁層
を1層挟持して形成されているが、2層以上挟持して形
成されていてもよい。
In the above-described embodiment, the capacitor A has the counter electrode formed by sandwiching one insulating layer containing the dielectric powder and the conductive resin powder, but is formed by sandwiching two or more layers. May be.

【0062】さらに、絶縁層1a・1b・1c・1d・1eには、
熱安定性を改善するための酸化防止剤や耐光性を改善す
るための紫外線吸収剤等の光安定剤、難燃性を改善する
ためのハロゲン系もしくはリン酸系の難燃性剤、アンチ
モン系化合物やホウ酸亜鉛・メタホウ酸バリウム・酸化
ジルコニウム等の難燃助剤、潤滑性を改善するための高
級脂肪酸や高級脂肪酸エステル・高級脂肪酸金属塩・フ
ルオロカーボン系界面活性剤等の外部滑剤効果を有する
もの等を1種以上添加してもよい。
Further, the insulating layers 1a, 1b, 1c, 1d, 1e
Light stabilizers such as antioxidants for improving thermal stability and ultraviolet absorbers for improving light resistance, halogen-based or phosphoric-based flame retardants for improving flame retardancy, antimony-based Compounds and flame retardant aids such as zinc borate, barium metaborate, and zirconium oxide; and external lubricant effects such as higher fatty acids, higher fatty acid esters, higher fatty acid metal salts, and fluorocarbon surfactants to improve lubricity One or more of these may be added.

【0063】[0063]

【発明の効果】本発明の多層配線基板によれば、絶縁層
の少なくとも一層に導電性樹脂粉末および比誘電率が20
以上の誘電体粉末を含有させたことから、この絶縁層を
配線導体で対向挟持して形成した容量素子に外部から電
圧を印加した場合、導電性樹脂粉末が電気伝導性のため
に電荷を効率よく分離して導体としての役目を果たし、
導電性樹脂粉末の絶縁層の厚み方向の長さ分だけ静電容
量に寄与する絶縁層の厚みを実質的に減少させることが
でき、その結果、絶縁層の厚みを極端に薄くしなくとも
その静電容量を所望の大きなものとして容量素子を形成
する対向電極の面積を小さなものとすることができ、多
層配線基板を小型化することが可能となる。
According to the multilayer wiring board of the present invention, at least one of the insulating layers has a conductive resin powder and a relative dielectric constant of at least 20.
Due to the inclusion of the above dielectric powder, when a voltage is externally applied to a capacitive element formed by sandwiching the insulating layer between the wiring conductors, the electric charge is efficiently reduced due to the electrical conductivity of the conductive resin powder. Well separated and serve as conductor,
The thickness of the insulating layer contributing to the capacitance can be substantially reduced by the length of the conductive resin powder in the thickness direction of the insulating layer. As a result, even if the thickness of the insulating layer is not extremely thinned, By setting the capacitance to a desired large value, the area of the counter electrode forming the capacitor can be reduced, and the multilayer wiring board can be reduced in size.

【0064】また、本発明の多層配線基板によれば、容
量素子を形成した絶縁層を、1〜30体積%の導電性樹脂
粉末と、10〜70体積%の比誘電率が20以上の誘電体粉末
と、10〜89体積%の有機材料とから構成したことから、
導電性樹脂粉末および誘電体粉末を絶縁層中に均一に良
好に分散させることができ、静電容量のムラのない容量
素子を得ることができる。
According to the multilayer wiring board of the present invention, the insulating layer on which the capacitive element is formed is made of a conductive resin powder of 1 to 30% by volume and a dielectric resin of 10 to 70% by volume having a relative dielectric constant of 20 or more. Because it is composed of body powder and 10-89% by volume of organic material,
The conductive resin powder and the dielectric powder can be uniformly and satisfactorily dispersed in the insulating layer, and a capacitance element having no variation in capacitance can be obtained.

【0065】さらに、本発明の多層配線基板によれば、
容量素子を形成した絶縁層を、配線導体間の方向の比誘
電率がこれに直交する方向の比誘電率の1.2倍以上のも
のとしたことから、絶縁層に含有する誘電体粉末の比誘
電率を配線導体間の方向で効率的に発現させることがで
き、その結果、この絶縁層を配線導体で対向挟持するこ
とにより、静電容量の大きな容量素子を得ることができ
る。
Further, according to the multilayer wiring board of the present invention,
Since the dielectric layer in which the capacitive element is formed has a relative dielectric constant of at least 1.2 times the relative dielectric constant in the direction between the wiring conductors in the direction orthogonal to the wiring conductor, the relative dielectric constant of the dielectric powder contained in the insulating layer is The ratio can be efficiently developed in the direction between the wiring conductors. As a result, by sandwiching the insulating layer between the wiring conductors, a capacitance element having a large capacitance can be obtained.

【0066】また、本発明の電子部品モジュールによれ
ば、上記の多層配線基板に電子部品を実装し、回路素子
として容量素子と電子部品とを含む電気的な回路を構成
したことから、多層配線基板に半導体素子や容量素子・
抵抗素子等の電子部品を搭載して混成集積回路装置等の
電子部品モジュールを製作する場合に、多層配線基板に
別途、容量素子を多数実装する必要はなく、その結果、
多層配線基板に実装される部品の数が減り、電子部品モ
ジュールを小型化することができる。
According to the electronic component module of the present invention, since the electronic component is mounted on the above-described multilayer wiring board and an electric circuit including the capacitor element and the electronic component is configured as a circuit element, the multilayer wiring board is formed. Semiconductor elements and capacitance elements
When electronic components such as a hybrid integrated circuit device are manufactured by mounting electronic components such as resistive elements, it is not necessary to separately mount a large number of capacitive elements on a multilayer wiring board.
The number of components mounted on the multilayer wiring board is reduced, and the size of the electronic component module can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板に、電子部品として半導
体素子を搭載した場合の電子部品モジュールの一例を示
す断面図である。
FIG. 1 is a cross-sectional view showing an example of an electronic component module when a semiconductor element is mounted as an electronic component on a multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・・・・絶縁基体 1a・1b・1d・1e ・・絶縁層 1c・・・・・・・・・絶縁層(導電性樹脂粉末および誘
電体粉末含有絶縁層) 2・・・・・・・・・配線導体 2a ・・・・・・・・配線導体層 2b ・・・・・・・・貫通導体 3・・・・・・・・・電子部品 4・・・・・・・・・多層配線基板 5・・・・・・・・・電子部品モジュール A・・・・・・・・・容量素子
1 ... Insulating base 1a 1b 1d 1e ... Insulating layer 1c ... Insulating layer (insulating layer containing conductive resin powder and dielectric powder) 2. ······················································································ ····· Multilayer wiring board 5 ······· Electronic component module A ······ Capacitance element

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 有機材料から成る複数の絶縁層を積層す
るとともにこれら絶縁層の表面に配線導体を形成して成
る多層配線基板であって、前記絶縁層の少なくとも一層
に導電性樹脂粉末および比誘電率が20以上の誘電体粉
末を含有させるとともに、この絶縁層をその上下両面に
被着した前記配線導体で対向挟持することによって容量
素子を形成したことを特徴とする多層配線基板。
1. A multilayer wiring board comprising a plurality of insulating layers made of an organic material laminated on each other and a wiring conductor formed on the surface of the insulating layers, wherein at least one of the insulating layers has a conductive resin powder and a conductive resin powder. A multilayer wiring board comprising a dielectric element having a dielectric constant of 20 or more, and a capacitor element formed by sandwiching the insulating layer between the wiring conductors applied to the upper and lower surfaces thereof.
【請求項2】 前記容量素子を形成した絶縁層は、1〜
30体積%の前記導電性樹脂粉末と、10〜70体積%
の前記誘電体粉末と、10〜89体積%の前記有機材料
とから成ることを特徴とする請求項1記載の多層配線基
板。
2. The method according to claim 1, wherein the insulating layer on which the capacitive element is formed has a thickness of
30% by volume of the conductive resin powder and 10 to 70% by volume
2. The multilayer wiring board according to claim 1, comprising said dielectric powder and 10 to 89% by volume of said organic material.
【請求項3】 前記容量素子を形成した絶縁層は、前記
配線導体間の方向の比誘電率がこれに直交する方向の比
誘電率の1.2倍以上であることを特徴とする請求項1
または請求項2記載の多層配線基板。
3. The insulating layer on which the capacitive element is formed, wherein a relative dielectric constant in a direction between the wiring conductors is 1.2 times or more as large as a relative dielectric constant in a direction orthogonal to the wiring conductor. 1
Or the multilayer wiring board according to claim 2.
【請求項4】 請求項1乃至請求項3のいずれかに記載
の多層配線基板に電子部品を実装し、回路素子として前
記容量素子と前記電子部品とを含む電気的な回路を構成
したことを特徴とする電子部品モジュール。
4. An electronic circuit comprising: the electronic component mounted on the multilayer wiring board according to claim 1; and an electric circuit including the capacitor and the electronic component as circuit elements. Electronic component module featuring.
JP2000251379A 2000-08-22 2000-08-22 Multilayer wiring board and electronic part module using the same Pending JP2002064278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000251379A JP2002064278A (en) 2000-08-22 2000-08-22 Multilayer wiring board and electronic part module using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000251379A JP2002064278A (en) 2000-08-22 2000-08-22 Multilayer wiring board and electronic part module using the same

Publications (1)

Publication Number Publication Date
JP2002064278A true JP2002064278A (en) 2002-02-28

Family

ID=18740795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000251379A Pending JP2002064278A (en) 2000-08-22 2000-08-22 Multilayer wiring board and electronic part module using the same

Country Status (1)

Country Link
JP (1) JP2002064278A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7189598B2 (en) 2003-03-03 2007-03-13 Seiko Epson Corporation Wiring board, method of manufacturing the same, semiconductor device, and electronic instrument

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7189598B2 (en) 2003-03-03 2007-03-13 Seiko Epson Corporation Wiring board, method of manufacturing the same, semiconductor device, and electronic instrument

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