JP2002062943A - Saturation detecting circuit and output control circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a saturation detecting circuit capable of precisely and surely detecting the saturated state of a transistor with a simple circuit. SOLUTION: This circuit comprises a transistor Q2 for outputting a collector detecting current Ic2 according to the magnitude of the collector current Ic1 of a transistor Q1 to be detected for saturation; a base current driving means for driving the base current Ib1 of the transistor Q1; a transistor Q5 for outputting a base detecting current Ib3 according to the magnitude of the base current Ib1 of the transistor Q1; a transistor Q3 for inputting the base detecting current Ib3 to a base and outputting a collector reproduction current Ic3 from a collector; and a current mirror circuit consisting of transistors Q6 and Q7 for outputting a saturation detection signal Is according to the difference between the collector detecting current Ic2 and the collector reproduction current Ic3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a saturation detection circuit for detecting a saturation state of a transistor in which a current amplification factor of a collector current with respect to a base current is reduced, and to receive the output current from an output transistor. The present invention relates to an output control circuit for controlling a voltage or a current of a load, and more particularly, to a saturation detection circuit and an output control circuit formed on an integrated circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a general voltage control circuit using bipolar transistors. 5 includes a pnp transistor Q1, an npn transistor Q4, an npn transistor Q9, a differential amplifier OP1, a constant voltage circuit CV1, resistors R1 to R4, and a terminal T1.
To T4.

[0003] The pnp transistor Q1 has an emitter connected to the input terminal T1, a collector connected to the output terminal T3, and a base connected to the collector of the npn transistor Q4. Further, a resistor R1 is connected between the base and the emitter. The npn-type transistor Q4 has a collector connected to the pnp-type transistor Q1.
And the emitter is connected to the ground terminal T2, and the base is connected to the emitter of the npn transistor Q9. Further, a resistor R2 is connected between the base and the emitter. The collector of the npn-type transistor Q9 is connected to the input terminal T1,
The emitter is connected to the base of npn transistor Q4. The base receives the output voltage of the differential amplifier circuit OP1. The resistor R3 and the resistor R4 are connected in series. One end of the series connection of the resistor R3 is connected to the ground terminal T4, and the other end is connected to the output terminal T3. In the differential amplifier circuit OP1, the voltage V1 from the constant voltage circuit CV1 is input to the positive input terminal +, and the voltage V2 at the connection point between the resistors R3 and R4 is input to the negative input terminal-. An output voltage corresponding to the voltage difference between the positive input terminal + and the negative input terminal-is output to the npn-type transistor Q
9 to the base. The ground terminal T4 is connected to the ground terminal T2.

In the differential amplifier circuit OP1, the constant voltage circuit C
The voltage V1 based on V1 is compared with the voltage V2 at the connection midpoint between the resistors R3 and R4. When the voltage V2 rises due to the rise of the output voltage Vout, the differential amplifier OP
1 decreases, and the base voltage of the npn transistor Q9 decreases. As a result, the emitter voltage of the npn transistor Q9 decreases, so that the collector current of the npn transistor Q4 decreases, the collector current of the pnp transistor Q1 decreases, and a rise in the output voltage Vout is suppressed. When the output voltage Vout decreases and the voltage V2 decreases, the differential amplifier circuit O
The output voltage of P1 rises, and the base voltage of npn transistor Q9 rises. As a result, the emitter voltage of npn transistor Q9 increases, so that the collector current of npn transistor Q4 increases, the collector current of pnp transistor Q1 increases, and output voltage Vout
Is suppressed. By such negative feedback control, the output voltage Vout is controlled to a constant voltage according to the voltage V1.

Incidentally, the amplification factor of the collector current with respect to the base current of the bipolar transistor (hereinafter, amplification factor hfe
Has a substantially constant value in the active region where the collector-emitter voltage is sufficiently large, irrespective of the collector-emitter voltage. When the voltage reaches the saturation region where a forward voltage is applied to the collector junction, the value thereof sharply decreases. In the voltage control circuit shown in FIG. 1, such a sharp decrease in the amplification factor hfe occurs when, for example, the input voltage Vin decreases due to the load current.

When the amplification factor hfe decreases, the base current required to flow the same collector current increases, so that the current consumption of the control circuit increases. In addition, when the current capacity of the base driving transistor (npn transistor Q4 in FIG. 5) is smaller than the current capacity of the output transistor (pnp transistor Q1 in FIG. 5), the base driving transistor is damaged. There is a risk of getting it.

In order to prevent such an increase in the base current due to the saturation of the bipolar transistor, the following several circuits are used in the conventional voltage control circuit.

FIG. 6 is a circuit diagram showing a first conventional voltage control circuit having a circuit for preventing an increase in base current. 6 and 5 indicate the same components. The first voltage control circuit shown in FIG. 6 includes a comparator CP1, an npn transistor Q8, a constant voltage circuit CV2, and a constant current circuit CC in addition to the same components as those in FIG.
1, constant current circuit CC2, resistor R5, resistor R11, resistor R
12.

The constant voltage circuit CV2 has a positive side connected to an input terminal T1 via a resistor R12 and a negative side connected to a ground terminal T2 via a constant current circuit CC2. The constant current circuit CC1 has one terminal connected to the resistor R11.
, And the other terminal is connected to the ground terminal T2. A constant current equal in magnitude to the current of the constant current circuit CC2 flows from the output terminal T3 to the ground terminal T2. The constant current circuit CC2 is
One terminal is connected to the negative side of the constant voltage circuit CV2, and the other terminal is connected to the ground terminal T2. From the input terminal T1 to the ground terminal T2, a constant current circuit CC1
A constant current having a magnitude equal to that of the current is flowing. The resistors R11 and R12 have the same resistance value. The comparator CP1 has a positive input terminal + connected to the connection point between the resistor R11 and the constant current circuit C1, and a negative input terminal-connected to the constant voltage circuit CV2 and the constant current circuit C1.
It is connected to the midpoint of connection with C2. The output voltage corresponding to the magnitude relationship between the potentials of the positive input terminal + and the negative input terminal-is output to the base of the npn transistor Q8. The output voltage of the comparator CP1 is input to the base of the npn transistor Q8, the collector is connected to the base of the npn transistor Q9, and the source is connected to the ground terminal T2 via the resistor R5.

[0010] Since the resistance values of the resistors R11 and R12 are equal and the current values of the constant current circuit CC1 and the constant current circuit CC2 are equal, the voltage drop by the resistors R11 and R12 is equal. Therefore, the constant voltage circuit C is provided between the positive input terminal + and the negative input terminal-of the comparator CP1.
V2 and the emitter of the pnp transistor Q1.
A voltage different from the voltage between the collectors is applied. When the voltage between the emitter and the collector of the pnp transistor Q1 is higher than the voltage of the constant voltage circuit CV2, the comparator CP1
Becomes low level, the npn transistor Q8 is turned off, and all the current output from the differential amplifier circuit OP1 is input to the base of the npn transistor Q9.

When the voltage between the emitter and the collector of the pnp transistor Q1 decreases and becomes lower than the voltage of the constant voltage circuit CV2, the output voltage of the comparator CP1 becomes high level, and the npn transistor Q8 is turned on. Therefore, the current output from the differential amplifier circuit OP1 is shunted to the resistor R5 according to the output resistance value of the differential amplifier circuit OP1 and the resistance value of the resistor R5. For this reason, np
The current input to the base of the n-type transistor Q9 decreases, and the increase in the base current of the npn-type transistor Q1 is suppressed.

As described above, in the voltage control circuit shown in FIG. 6, the voltage between the emitter and the collector of the pnp transistor Q1 is compared with the constant voltage by the constant voltage circuit CV2, and the voltage between the emitter and the collector is made constant. When the voltage becomes lower than the voltage, a circuit for suppressing the base current is operated.

In addition to the above-mentioned method, for example, in Japanese Patent Laid-Open Publication No. Hei 8-44441, a collector current and a base current are detected at a fixed magnification, and the difference between the detected values is negatively fed back to obtain the base current. A method for suppressing the increase is disclosed.

FIG. 7 is a circuit diagram showing a second conventional voltage control circuit having a circuit for preventing an increase in base current. The same reference numerals in FIGS. 5 and 7 indicate the same components. The second voltage control circuit shown in FIG. 7 includes a pnp transistor Q11, a pnp transistor Q11a,
pnp transistor Q13, pnp transistor Q
13a, npn transistor Q12, npn transistor Q12a, npn transistor Q14, npn
It comprises a type transistor Q14a, a differential amplifier circuit OP1, a constant voltage circuit CV1, a diode D2, a resistor R1, a resistor R3, a resistor R4, and terminals T1 to T4.

The pnp transistor Q11 has an emitter connected to the input terminal T1, a collector connected to the output terminal T3, a base connected to the collector of the npn transistor Q12, and a transistor connected between the emitter and the base. Is connected to a resistor R1. The pnp transistor Q11a has an emitter and a base connected to the emitter and base of the pnp transistor Q11, respectively, and a collector connected to the collector of the npn transistor Q14. The emitter junction area of the pnp transistor Q11 is formed to be N11 times the emitter junction area of the pnp transistor Q11a. Therefore, the base current of the pnp transistor Q11 has a magnitude N11 times the base current of the pnp transistor Q11a receiving the same voltage between the base and the emitter.

The pnp transistor Q13 has an emitter connected to the input terminal T1, a collector connected to the collector of the npn transistor Q12a, and a base receiving the output voltage of the differential amplifier OP1. pn
The p-type transistor Q13a has an emitter and a base connected to the emitter and the base of the pnp-type transistor Q13, respectively, and a collector connected to the collector of the npn-type transistor Q14a. p
The emitter junction area of np transistor Q13 is pn
The p-type transistor Q13a is formed to have a magnification N13 times the emitter junction area. Therefore,
The base current of the pnp transistor Q13 has a magnitude N13 times the base current of the pnp transistor Q13a receiving the same voltage between the base and the emitter.

The npn transistor Q12 has a collector connected to the base of the pnp transistor Q11, a base connected to the base of the npn transistor Q12a, and an emitter connected to the ground terminal T2. The npn transistor Q12a has an emitter and a base connected to the emitter and base of the npn transistor Q12, respectively, and a collector connected to the collector of the pnp transistor Q13. The collector and the base are connected. The emitter junction area of npn transistor Q12 is formed to have a magnification N12 times the emitter junction area of npn transistor Q12a. Therefore, the base current of npn transistor Q12 is
It has a magnitude N12 times the base current of the npn transistor Q12a receiving the same voltage between the base and the emitter.

The npn transistor Q14 has a collector connected to the collector of the pnp transistor Q11a, a base connected to the base of the npn transistor Q14a, and an emitter connected to the ground terminal T2.
It is connected to the. The collector and the base are connected. The npn transistor Q14a has an emitter and a base connected to the emitter and base of the npn transistor Q14, respectively, and a collector connected to the collector of the pnp transistor Q13a. The emitter junction area of npn transistor Q14 is formed to have a magnification N14 times the emitter junction area of npn transistor Q14a. Therefore, the base current of npn transistor Q14 is equal to n
It has a magnitude N14 times the base current of the pn-type transistor Q14a.

The resistor R3 and the resistor R4 are connected in series, and one end of this series connection on the resistor R3 side is connected to the ground terminal T.
4 and the other end is connected to the output terminal T3.
The differential amplifier OP1 has a constant voltage circuit C connected to the positive input terminal +.
A voltage V1 based on V1 is input, and a voltage V2 at a connection point between the resistors R3 and R4 is input to the negative input terminal-. An output voltage corresponding to the voltage difference between the positive input terminal + and the negative input terminal-is output to the pnp transistor Q1.
3 output to the base. The ground terminal T4 is connected to the ground terminal T2.

In the voltage control circuit shown in FIG.
When the type transistor Q11 saturates and the current amplification rate decreases, the current for driving the base increases.
The collector current Ic13a of the pnp transistor Q13a also increases. When the collector current Ic13a of the pnp transistor Q13a becomes larger than the collector current Ic14a of the npn transistor Q14a, the diode D2 is turned on, and the current of the difference between the current Ic13a and the current Ic14a flows through the diode R2 to the resistors R3 and R4. Flows into the connection point. As a result, the voltage of the positive input terminal + of the differential amplifier circuit OP1 increases, the output voltage of the differential amplifier circuit OP1 increases, and the collector current I of the pnp transistor Q13 increases.
c13 decreases, and the base current Ib11 of the pnp transistor Q11 decreases. Thus, an increase in the base current due to the saturation of the pnp transistor Q11 is suppressed.

A pnp transistor Q11 and a pnp transistor Q11a, and a pnp transistor Q13 and a p
npn transistor Q13a, npn transistor Q
12 and npn transistor Q12a, and npn transistor Q14 and npn transistor Q14a
Respectively constitute a current mirror circuit. The ratio of the collector current of each current mirror circuit is equal to the ratio of the respective emitter junction areas. Therefore, when each transistor is not saturated, the collector current Ic1 of the pnp transistor Q13a
The collector current Ic14a of the 3a and npn-type transistors Q14a is represented by the following equation by the collector current Ic11 and the base current Ib11 of the pnp-type transistor Q11.

[0022]

Ic13a = Ib11 / (N12 × N13) (1) Ic14a = Ic11 / (N11 × N14) (2)

However, in the above equation, the magnification N11 is a sufficiently large value, and the base current Ib11a of the pnp transistor Q11a is sufficiently smaller than the base current Ib11 of the pnp transistor Q11.

From the equations (1) and (2), the amplification factor hfel of the pnp transistor Q11 in the state where the current starts flowing through the diode D2 is expressed by the following equation.

[0025]

Ic11 / (N11 × N14) = Ib11 / (N12 × N13) hfel = Ic11 / Ib11 = (N11 × N14) / (N12 × N13) (3)

That is, when the amplification factor hfe is larger than the amplification factor hfel shown in the equation (3), the diode D2
Does not conduct, and the base current of the pnp transistor Q11 is not suppressed. When the pnp transistor Q11 becomes saturated and the amplification factor hfe decreases and becomes smaller than the amplification factor hfel, the diode D2 conducts and the base current is suppressed.

[0027]

By the way, in the voltage control circuit shown in FIG. 6, the pnp transistor Q1
Is set in advance in the constant voltage circuit CV2, and the base current is suppressed based on the result of comparing this voltage with the actual emitter-collector voltage. Yes, pn
This does not mean that the saturation state of the p-type transistor Q11 is directly detected. Therefore, it is necessary to have a margin against variations in circuit constants due to temperature, variations in circuit constants depending on products, and variations in collector current, and it is necessary to set a voltage higher than the actual saturation voltage in the constant voltage circuit CV2. There is. That is, the emitter for suppressing the base current
There is a problem that the minimum voltage of the collector-to-collector voltage must be increased excessively, and the extra voltage increases the power consumption of the circuit. Further, there is a problem that the output voltage variable range for a predetermined input voltage is narrowed.

In the voltage control circuit shown in FIG. 7, the ratio of the emitter junction area and the amplification factor hfe are compared as shown in the equation (3). The base current is suppressed. However, the ratio of the emitter junction area can be set with high accuracy, for example, by forming each transistor inside the same IC. On the other hand, the amplification factor hfe indicates the variation of the circuit constant due to temperature, the variation between products, the collector Since the parameter is likely to fluctuate due to fluctuations in current or the like, the amplification factor hfel may not be set appropriately for the fluctuation factor hfe.

For example, when the amplification factor hfe in the unsaturated state is 200
The amplification factor hfe is given by
Even if the magnifications N11 to N14 are set so that l becomes 100,
The set amplification factor hfel may not be appropriate for a transistor whose amplification factor hfe in the unsaturated state is 150 due to variation. That is, the amplification factor h
There is a problem that the amplification factor hfel of the threshold value for suppressing the base current cannot be set appropriately with respect to the temperature variation of fe and the variation among individuals.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a saturation detection circuit and a saturation detection circuit capable of reliably detecting a saturation state of a transistor, and reducing a decrease in detection accuracy due to temperature fluctuation and individual variation. An object of the present invention is to provide an output control circuit.

[0031]

To achieve the above object, a saturation detection circuit according to the present invention is a saturation detection circuit for detecting a saturation state of a transistor in which a current amplification factor of a collector current with respect to a base current decreases. A collector current detecting means for outputting a collector detection current corresponding to a magnitude of a collector current of the transistor, a base current driving means for driving a base current of the transistor, and a base corresponding to a magnitude of a base current of the transistor. Base current detection means for outputting a detection current, a duplication transistor for inputting the base detection current to the base and outputting a collector duplication current from the collector, and saturation detection according to a difference between the collector detection current and the collector duplication current Signal output means for outputting a signal.

The collector current detecting means includes a first transistor which receives a voltage between the base and the emitter of the transistor and outputs the collector detection current from a collector between the base and the emitter. I have.
Preferably, in the first transistor, a junction area between the emitter and the base has a predetermined ratio with respect to the junction area of the transistor.

Further, the base current driving means includes a second transistor which receives a predetermined voltage between the base and the emitter and inputs a base current of the transistor to a collector, and the base current detecting means includes a base transistor. And a third transistor receiving the predetermined voltage between the transistor and the emitter and outputting the base detection current from the collector. Preferably, in the third transistor, a junction area between the emitter and the base has a predetermined ratio with respect to the junction area in the second transistor.

According to the saturation detection circuit of the present invention, the collector current detection means outputs a collector detection current corresponding to the magnitude of the collector current of the transistor. Further, the base current driving means drives a base current of the transistor, and a base detection current corresponding to the magnitude of the base current is output from the base current detection means. The base detection current is input to the base of the duplication transistor, and a collector duplication current corresponding to the base detection current is output from the collector of the duplication transistor. Then, a saturation detection signal corresponding to a difference between the collector detection current and the collector copy current is generated and output by the saturation detection signal output means. Since the first transistor of the collector current detecting means receives a voltage between the base and the emitter of the transistor between the base and the emitter, the collector detection current output from the collector is:
It has a size corresponding to the collector current of the transistor. When the junction area between the emitter and the base of the first transistor has a predetermined ratio with respect to the junction area of the transistor, the collector detection current is equal to the collector current of the transistor. The predetermined ratio. . Further, the second transistor of the base current drive means and the third transistor of the base current detection means receive the same predetermined voltage between the base and the emitter, so that the base detection current is Has a magnitude corresponding to the base current. When the junction area between the emitter and the base of the third transistor has a predetermined ratio with respect to the junction area of the second transistor, the base detection current is equal to the base current of the transistor. The current has the predetermined ratio.

An output control circuit according to the present invention is an output control circuit for controlling a voltage or a current of a load which receives an output current from an output transistor, and detects a collector detection current corresponding to a collector current of the output transistor. Collector current detection means for outputting, base current detection means for outputting a base detection current corresponding to the magnitude of the base current of the output transistor, inputting the base detection current to the base, and outputting a collector duplicate current from the collector A duplication transistor, a saturation detection signal output unit that outputs a saturation detection signal according to a difference between the collector detection current and the collector duplication current, and a base that drives a base current of the output transistor according to the saturation detection signal. Current driving means.

The collector current detecting means includes a first transistor which receives a voltage between the base and the emitter of the transistor and outputs the collector detection current from a collector between the base and the emitter. I have.
Preferably, in the first transistor, a junction area between the emitter and the base has a predetermined ratio with respect to the junction area of the transistor.

The base current driving means detects a voltage or a current of the load, and drives a base current of the output transistor according to an error between the detected value and a predetermined reference value and the saturation detection signal. And a second transistor between the base and the emitter that receives a base drive voltage according to the error and the saturation detection signal and inputs a base current of the transistor to a collector. The base current detection means includes a third transistor which receives the base drive voltage between a base and an emitter and outputs the base detection current from a collector. Preferably, in the third transistor, a junction area between the emitter and the base has a predetermined ratio with respect to the junction area in the second transistor.

Further, the base current driving means includes an output detecting means for detecting a voltage or a current of the load, and an error between a value detected by the output detecting means and a predetermined reference value in accordance with the saturation detection signal. Error amplifying means for generating the base drive voltage amplified by a gain.

According to the output control circuit of the present invention, the collector current detecting means outputs a collector detection current corresponding to the magnitude of the collector current of the transistor. Further, the base current driving means drives the base current of the transistor in accordance with the saturation detection signal, and the base current detection means outputs a base detection current corresponding to the magnitude of the base current. The base detection current is input to the base of the duplication transistor, and a collector duplication current corresponding to the base detection current is output from the collector of the duplication transistor. Then, a saturation detection signal corresponding to a difference between the collector detection current and the collector copy current is generated and output by the saturation detection signal output means. Since the first transistor of the collector current detecting means receives a voltage between the base and the emitter of the transistor between the base and the emitter, the collector detection current output from the collector is Has a magnitude corresponding to the collector current of Of the first transistor,
When the junction area between the emitter and the base has a predetermined ratio with respect to the junction area of the transistor, the collector detection current has the predetermined ratio with respect to the collector current of the transistor. are doing. . Since the second transistor of the base current driver and the third transistor of the base current detector receive the base drive voltage between the base and the emitter, the base detection current is equal to the base of the transistor. It has a size corresponding to the current. Of the third transistor,
When the junction area between the emitter and the base has a predetermined ratio with respect to the junction area of the second transistor, the base detection current is equal to the predetermined ratio with respect to the base current of the transistor. Have a ratio. The voltage or current of the load detected by the output detection means of the base current driving means is detected by the error amplification means from an error with a predetermined reference value. This error is amplified with a gain corresponding to the saturation detection signal, and is input as the base drive voltage between the base and the emitter of the second transistor.

Further, the base current driving means detects the voltage or current of the load, variably outputs the detected value according to the saturation detection signal, and outputs the detected value by the output detecting means. Error amplification means for generating the base drive voltage obtained by amplifying an error between the base drive voltage and a predetermined reference value.

According to the output control circuit of the present invention having the above configuration, the detected value of the voltage or current of the load detected by the output detecting means of the base current driving means depends on the saturation detection signal. It is changed and output. Then, the error amplifying means detects an error between the value detected by the output detecting means and a predetermined reference value. This error is amplified with a predetermined gain, and is input as the base drive voltage between the base and the emitter of the second transistor.

Further, the base current driving means includes an output detecting means for detecting a voltage or a current of the load, a detection value by the output detecting means, and a predetermined reference value which is varied according to the saturation detection signal. Error amplifying means for generating the base drive voltage obtained by amplifying the above error.

According to the output control circuit of the present invention having the above configuration, the voltage or current of the load detected by the output detection means of the base current driving means is supplied to the error amplification means by the error detection means. An error from a predetermined reference value that is changed according to the signal is detected. This error is amplified with a predetermined gain, and is input as the base drive voltage between the base and the emitter of the second transistor.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Four embodiments in which the present invention is applied to a voltage control circuit will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing a first embodiment of a voltage control circuit according to the present invention. The voltage control circuit shown in FIG.
Q3, npn transistors Q4 to Q9, differential amplifier OP1, constant voltage circuit CV1, resistors R1 to R5, terminal T1
To T4. pnp type transistor Q
Reference numeral 1 denotes an embodiment of a transistor according to the present invention and an embodiment of an output transistor. pn
The p-type transistor Q2 is one embodiment of the collector current detecting means of the present invention, and is one embodiment of the first transistor of the present invention. The pnp transistor Q3 is one embodiment of the duplication transistor in the present invention. npn transistor Q4, npn transistor Q8, npn transistor Q9, differential amplifier OP1, constant voltage circuit CV1, resistor R2, resistor R
The circuit composed of the resistor R4 and the resistor R5 is an embodiment of the base current driving means in the present invention. npn
The type transistor Q4 is one embodiment of the second transistor in the present invention. The circuit composed of the resistor R3 and the resistor R4 is one embodiment of the output detecting means in the present invention. Differential amplifier circuit OP1, constant voltage circuit CV1, np
The circuit including the n-type transistor Q8 and the resistor R5
5 is an embodiment of an error amplifying unit according to the present invention. np
The n-type transistor Q5 is an embodiment of the base current detecting means of the present invention, and is an embodiment of the third transistor of the present invention. The circuit including the npn-type transistor Q6 and the npn-type transistor Q7 is one embodiment of the saturation detection signal output means of the present invention, and is one embodiment of the current mirror circuit of the present invention.

The pnp transistor Q1 has an emitter connected to the input terminal T1, a collector connected to the output terminal T3, and a base connected to the collector of the npn transistor Q4. Further, a resistor R1 is connected between the base and the emitter. The pnp transistor Q2 has an emitter and a base connected to the emitter and the base of the pnp transistor Q1, respectively, and has a collector connected to the npn transistor Q1.
6 are connected to the collector. The emitter junction area of the pnp transistor Q1 is equal to the pnp transistor Q2.
Is formed so as to have a magnification n times as large as the emitter junction area. Therefore, the base current of the pnp transistor Q1 has a magnitude n times that of the base current of the pnp transistor Q2 receiving the same voltage between the base and the emitter.

The npn transistor Q4 has a collector connected to the base of the pnp transistor Q1, an emitter connected to the ground terminal T2, and a base connected to the emitter of the npn transistor Q9. Further, a resistor R2 is connected between the base and the emitter. The npn transistor Q5 has an emitter and a base connected to the emitter and base of the npn transistor Q4, respectively, and a collector connected to the base of the pnp transistor Q3. The emitter junction area of npn transistor Q4 is
It is formed to have a magnification of m times the emitter junction area of npn transistor Q5. Therefore, n
The base current of the pn transistor Q4 is the same as that of the npn transistor Q4 receiving the same voltage between the base and the emitter.
5 has a magnitude of m times the base current.

The pnp transistor Q3 has an emitter connected to the input terminal T1, a base connected to the collector of the npn transistor Q5, and a collector connected to the collector of the npn transistor Q7 and the base of the npn transistor Q8. Have been.

The npn transistor Q6 has a collector connected to the collector of the pnp transistor Q2, a base connected to the base of the npn transistor Q7, and an emitter connected to the ground terminal T2. The collector and the base are connected. n
The pn transistor Q7 has an emitter and a base of n.
The collector is connected to the emitter and the base of the pn transistor Q6, and the collector is connected to the collector of the pn transistor Q3.

The npn-type transistor Q9 has a collector connected to the input terminal T1, and an emitter connected to the base of the npn-type transistor Q4. In addition, the base receives the output voltage of the differential amplifier OP1 and n
The collector of the pn transistor Q8 is connected.
The npn transistor Q8 has a collector connected to the base of the npn transistor Q9, a base connected to a connection point of the collectors of the pnp transistor Q3 and the npn transistor Q7, and an emitter connected to the resistor R.
5 is connected to the ground terminal T2.

The resistor R3 and the resistor R4 are connected in series, and one end on the resistor R3 side of the series connection is connected to the ground terminal T.
4 and the other end is connected to the output terminal T3.
The differential amplifier OP1 has a constant voltage circuit C connected to the positive input terminal +.
A voltage V1 based on V1 is input, and a voltage V2 at a connection point between the resistors R3 and R4 is input to the negative input terminal-. An output voltage corresponding to the voltage difference between the positive input terminal + and the negative input terminal-is output to the npn transistor Q9.
Output to the base. The ground terminal T4 is connected to the ground terminal T2.

In the voltage control circuit shown in FIG.
The base current of the pn transistor Q8 flows and the base current of the npn transistor Q9 is shunted to the resistor R5, thereby suppressing the base current of the npn transistor Q1. First, a normal operation state in which a base current does not flow through npn transistor Q8 will be described.

In the differential amplifier circuit OP1, the constant voltage circuit C
The voltage V1 based on V1 is compared with the voltage V2 at the connection midpoint between the resistors R3 and R4. When the voltage V2 rises due to the rise of the output voltage Vout, the differential amplifier OP
1 decreases, and the base voltage of the npn transistor Q9 decreases. As a result, the emitter voltage of the npn transistor Q9 decreases, so that the collector current of the npn transistor Q4 decreases, the collector current of the pnp transistor Q1 decreases, and a rise in the output voltage Vout is suppressed. When the output voltage Vout decreases and the voltage V2 decreases, the differential amplifier circuit O
The output voltage of P1 rises, and the base voltage of npn transistor Q9 rises. As a result, the emitter voltage of npn transistor Q9 increases, so that the collector current of npn transistor Q4 increases, the collector current of pnp transistor Q1 increases, and output voltage Vout
Is suppressed. By such negative feedback control, the output voltage Vout is controlled to a constant voltage according to the voltage V1.

Next, the operation when a base current flows through npn-type transistor Q8 will be described.

When the emitter-collector voltage of the pnp transistor Q1 decreases and reaches the saturation region, the feedback is performed so as to output a constant voltage corresponding to the voltage V1, so that the base current Ib1 of the pnp transistor Q1 is output. And the current flowing through the collector of npn transistor Q4 also increases. The base current Ib1 of the pnp transistor Q1 is equal to the collector current Ib1 of the pnp transistor Q1.
It is represented by the following equation by c1 and amplification factor hfe1.

[0056]

## EQU3 ## Ib1 = Ic1 / hfe1 (4)

The magnification n is set to be sufficiently large, and pn
When the base current Ib1 of the p-type transistor Q1 is sufficiently larger than the base current (Ib1 / n) of the pnp-type transistor Q, the collector current of the npn-type transistor Q4 becomes substantially equal to the base current Ib1. Therefore, np
The base current Ib3 of the pnp transistor Q3 flowing through the collector of the n-type transistor Q5 is expressed by the following equation using the equation (4).

[0058]

Ib3 = Ib1 / m = (Ic1 / hfe1) / m (5)

Therefore, the collector current Ic3 of the pnp transistor Q3 is represented by the following equation by the amplification factor hfe3 of the pnp transistor Q3.

[0060]

Ic3 = Ib3 × hfe3 = (Ic1 / m) × (hfe3 / hfe1) (6)

On the other hand, a collector current (Ic1 / n) based on the ratio of the emitter junction area of the pnp transistor Q1 and the pnp transistor Q2 flows through the collector of the pnp transistor Q2. The signal is input to a current mirror circuit including an npn transistor Q7. Collector current Ic7 of npn transistor Q7, which is the output of the current mirror circuit
Is represented by the following equation.

[0062]

Ic7 = Ic1 / n (7)

Therefore, according to equations (6) and (7), the current I flowing through the base of npn-type transistor Q8 is
s is represented by the following equation.

[0064]

Is = Ic3−Ic7 = (Ic1 / m) × (hfe3 / hfe1) −Ic1 / n = (Ic1 / m) × {(hfe3 / hfe1) −m / n} (8)

In the saturation region, the pnp transistor Q
When the amplification factor hfe1 decreases, p
Base current Ib3 of np transistor Q3 increases.
On the other hand, the collector current of the pnp transistor Q3 is np
Since the current flows to the collector of the n-type transistor Q7 and the base of the npn-type transistor Q8, the voltage between the emitter and the collector of the pnp-type transistor Q3 does not drop and becomes saturated, and the amplification factor hfe3 of the pnp-type transistor Q1 does not decrease. . Therefore, according to equation (6), pn
The collector current Ic3 of the p-type transistor Q3 increases and n
The current Is flowing into the base of the pn transistor Q8 also increases. As a result, the base current of npn transistor Q9 decreases and the collector current decreases, and accordingly the base current of npn transistor Q4 decreases and the collector current decreases. Therefore, base current Ib1 of pnp transistor Q1 becomes Decrease. Thus, the base current of the pnp transistor Q1 is suppressed, and the saturation of the pnp transistor Q1 is prevented.

In the voltage control circuit shown in FIG. 1, the current Is changes according to the saturation state of the transistor.
The output resistance of the differential amplifier circuit OP1, the resistances R5 and np
By varying the voltage dividing ratio of the n-type transistor Q8 to the series circuit, the circuit can be considered as a circuit that varies the loop gain of negative feedback. That is, when the amplification factor hfe1 of the pnp transistor Q1 decreases in the saturation region, the current Is increases according to equation (8), and the emitter-collector resistance of the npn transistor Q8 decreases,
By reducing the loop gain of the negative feedback, the increase of the base current Ib1 is suppressed.

In equation (8), the collector current Ic3
Is smaller than the collector current Ic7 and the polarity of the current Is becomes negative, the reverse current hardly flows through the base of the npn transistor Q8, so that the collector voltage of the npn transistor Q7 decreases and the npn transistor Q7 decreases. The transistor Q7 becomes saturated. At this time, the npn transistor Q8 is in the off state, and the voltage control circuit is in the normal operation state described above. Therefore, by appropriately setting the amplification factor hfe1, the amplification factor hfe3, the magnification n and the magnification m, the npn transistor Q8 is turned off in the non-saturated state of the pnp transistor Q1, and the npn transistor Q8 in the saturated state. And the base current can be suppressed.

For example, the amplification factor hfe1 in the unsaturated state
And amplification factor hfe3 is 200, magnification n is 100, magnification m
Is set to 200, when the pnp transistor Q1 is in an unsaturated state, the current Is according to the equation (8)
Is negative, the npn transistor Q8 is in the off state, and no control for suppressing the base current is performed. When the pnp transistor Q1 saturates and the amplification factor hfe1 drops below 50% of the amplification factor hfe3, the polarity of the current Is according to equation (8) becomes positive and npn
The current Is is supplied to the base of the type transistor Q8,
The base current Ib1 is suppressed.

As described above, according to the first embodiment of the present invention, the saturation of the transistor to be detected can be directly detected as a decrease in the current amplification factor hfe. Therefore, the saturation of the transistor can be reliably detected. Further, the current Is corresponding to the saturation of the transistor is negatively fed back to the base current of the output transistor, so that the saturation of the output transistor in the voltage control circuit can be reliably prevented. Further, unlike the voltage control circuit shown in FIG. 6, it is not necessary to set a voltage having an excessive margin for the voltage between the emitter and the collector, so that the power consumption of the circuit can be reduced. Further, the variable range of the output voltage with respect to the predetermined input voltage can be widened.

In the voltage control circuit shown in FIG. 7, the absolute value of the current amplification factor is compared with a predetermined threshold value determined by the ratio of the emitter junction area as shown in equation (3). On the other hand, in the voltage control circuit of the present invention, the relative value of the current amplification factor is compared with a predetermined threshold value determined by the ratio of the emitter junction area as shown in Expression (8). ing. The absolute value of the current amplification factor is
As described above, it is likely to fluctuate due to temperature fluctuations and individual variations, but for example, the ratio of the current amplification factors of the transistors formed in the same IC is hardly affected by temperature variations and individual variations. Therefore, pn
A pnp transistor Q1 is used as the p-type transistor Q3.
Amplification factor hfe1 and amplification factor hfe3
By matching the temperature fluctuations and the individual fluctuations, it is possible to detect the saturation state of the transistor without being affected by these fluctuation factors. That is, according to the first embodiment of the present invention, the influence of temperature fluctuation and individual variation on the detection accuracy of the saturation state of the transistor is reduced as compared with the conventional method, and the saturation state can be detected with high accuracy. it can.

As can be seen from equation (8), the current Is
Is not affected by the collector current Ic1, and the amplification factor hfe1
, Amplification factor hfe3, scaling factor n and scaling factor m, the control start condition for suppressing base current Ib1 does not depend on the collector current. That is, the first of the present invention
According to the embodiment, it is possible to reduce the variation in the accuracy of detecting the saturation state due to the variation in the collector current.

The output control circuit using the saturation detection circuit of the present invention is not limited to the above-described voltage control circuit, but may be, for example, a current control circuit. For example, the voltage control circuit in FIG. 1 changes the output voltage detection circuit using the resistors R3 and R4 to an output current detection circuit that detects the voltage of a shunt resistor connected in series between the terminal T4 and the load. Thereby, it can be changed to a current control circuit.

In the present invention, the transistor in which a saturated state is detected is not limited to a pnp transistor, but may be an npn transistor. For example, by replacing the type of each transistor in FIG. 1 with npn type or pnp type, respectively, inverting the voltage polarity of the constant voltage circuit CV1, and making the input voltage to the input terminal T1 a negative voltage, Can be changed from the positive voltage output to the negative voltage output.

<Second Embodiment> FIG. 2 is a circuit diagram showing a second embodiment of the voltage control circuit according to the present invention. 1 and 2 represent the same components. The voltage control circuit shown in FIG. 2 has a configuration in which the npn transistor Q8 and the resistor R5 in the configuration of the voltage control circuit shown in FIG. 1 are deleted, and a diode D1 is added instead of these. The circuit including the diode D1, the resistor R3, and the resistor R4 is one embodiment of the output detecting means in the present invention.

The diode D1 has an anode connected to the connection point of the collectors of the pnp transistor Q3 and the npn transistor Q7, and a cathode connected to the resistor R3 and the resistor R3.
4 are connected.

In the second embodiment of the present invention, the method of negatively feeding back the current Is that changes according to the saturation state of the pnp transistor Q1 is modified from that of the first embodiment. . That is, the voltage of the negative input terminal-of the differential amplifier circuit OP1 increases and the base voltage of the npn transistor Q9 decreases in accordance with the increase of the current Is input to the connection point between the resistors R3 and R4. , Pnp
The base current Ib1 of the type transistor Q1 changes in a decreasing direction.

As described above, the increase in the base current of the pnp transistor Q1 can be suppressed by feeding back the current Is that changes according to the saturation state to the detected value of the output voltage. The same effect as the embodiment can be obtained.

<Third Embodiment> FIG. 3 is a circuit diagram showing a third embodiment of the voltage control circuit according to the present invention. 1 and 3 indicate the same components. In the voltage control circuit shown in FIG. 3, the npn transistor Q8 and the resistor R5 in the configuration of the voltage control circuit shown in FIG. 1 are eliminated, and instead of these, the npn transistor Q
10, a configuration in which a resistor R8 and a resistor R9 are added. Differential amplifier circuit OP1, constant voltage circuit CV1, np
A circuit including the n-type transistor Q10, the resistor R8, and the resistor R9 is one embodiment of the error amplifying unit in the present invention.

The voltage of the constant voltage circuit CV1 is input to the positive input terminal + of the differential amplifier circuit OP1 via the resistor R8, and the collector of the npn transistor Q10 is connected to the positive input terminal + of the differential amplifier circuit OP1. npn transistor Q10
Has a collector connected to the positive input terminal + of the differential amplifier circuit OP1, and an emitter connected to the ground terminal T via a resistor R9.
2, and the base is connected to the connection point of the collectors of the pnp transistor Q3 and the npn transistor Q7.

The third embodiment of the present invention is the same as the second embodiment, and the method of negatively feeding back the current Is that changes according to the saturation state of the pnp transistor Q1 is described in the first embodiment. Has been changed. That is, according to the increase of the current Is input to the base of the npn transistor Q10, the npn transistor Q10
Of the differential amplifier circuit OP1, the voltage of the positive input terminal + of the differential amplifier circuit OP1 decreases, and
Since the base voltage of the pn transistor Q9 decreases,
The base current Ib1 of the pnp transistor Q1 changes in a decreasing direction.

As described above, by feeding back the current Is that changes according to the saturation state to the reference voltage value, pn
An increase in the base current of the p-type transistor Q1 can be suppressed, and the same effect as in the first embodiment can be obtained.

<Fourth Embodiment> FIG. 4 is a circuit diagram showing a fourth embodiment of the voltage control circuit according to the present invention. 1 and 4 indicate the same components. In the voltage control circuit shown in FIG. 4, the current mirror circuit including the npn-type transistor Q6 and the npn-type transistor Q7 in the configuration of the voltage control circuit shown in FIG. 1 is eliminated, and instead, a differential amplifier circuit OP2, a resistor R6
And a resistor R7 is added. A circuit including the differential amplifier OP2, the resistor R6, and the resistor R7 is one embodiment of the saturation detection signal output unit of the present invention.

The resistor R6 is connected between the collector of the pnp transistor Q3 and the ground terminal T2.
The resistor R7 is connected between the collector of the pnp transistor Q2 and the ground terminal T2. The differential amplifier circuit OP2 connects the positive input terminal + to a pnp transistor Q3.
And the negative input terminal-is connected to the midpoint between the collector of the pnp transistor Q2 and the resistor R7, and the positive input terminal + and the negative input terminal are connected. A voltage corresponding to the voltage between-is output to the base of the npn transistor Q8.

According to the fourth embodiment of the present invention, the circuit for outputting a signal (current Is) corresponding to the difference between the collector current Ic2 of the pnp transistor Q2 and the collector current Ic3 of the pnp transistor Q3 comprises the first circuit. This is a modification of the third embodiment. That is, the collector current Ic3 and the collector current Ic2 are converted into voltages from the ground terminal T2 by the resistors R6 and R7, respectively, and a voltage corresponding to the voltage difference is applied to the base of the npn transistor Q8. The saturation of the pnp transistor Q1 causes the collector current Ic3 to change to the collector current Ic2.
When it becomes larger, the output voltage of the differential amplifier circuit OP2 rises, the base current is supplied to the npn transistor Q8, the collector-emitter conducts, and the base current of the npn transistor Q9 decreases.
The base current of the type transistor Q1 decreases.

As described above, the same effect as in the first embodiment can be obtained by converting the difference between the collector current Ic3 and the collector current Ic2 into a differential voltage of the voltage generated by the resistor and performing negative feedback. it can. Further, the fourth embodiment can be applied to the above-described second and third embodiments.

[0086]

According to the present invention, with a simple circuit,
The saturation of the transistor to be detected can be directly detected as a decrease in the current amplification factor. Thereby, the saturation of the transistor can be reliably detected. In addition, since the influence of temperature fluctuation and individual variation on the detection accuracy of the saturated state can be reduced, the saturated state can be detected with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage control circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the voltage control circuit according to the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the voltage control circuit according to the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the voltage control circuit according to the present invention.

FIG. 5 is a circuit diagram of a general voltage control circuit using bipolar transistors.

FIG. 6 is a circuit diagram showing a first conventional voltage control circuit having a circuit for preventing an increase in base current.

FIG. 7 is a circuit diagram showing a second conventional voltage control circuit having a circuit for preventing an increase in base current.

[Explanation of symbols]

Q1 to Q3 ... pnp transistors, Q4 to Q10 ... n
pn-type transistors, OP1, OP2 ... differential amplifier circuits,
CV1 constant voltage circuit, D1 diode, R1 to R9 ...
Resistance, T1 to T4 ... terminals.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H420 BB02 BB12 BB13 CC02 DD02 EA11 EA18 EA23 EA24 EA39 EA43 EA47 EB15 EB37 FF03 FF04 FF23 FF25 HJ09 LL05 NA32 NB02 NB12 NB24 NB28 NB15 NC26 NC23 NC23

Claims (16)

[Claims] 1. A saturation detection circuit for detecting a saturation state of a transistor in which a current amplification factor of a collector current with respect to a base current decreases, the collector current outputting a collector detection current corresponding to the magnitude of the collector current of the transistor Detecting means; base current driving means for driving the base current of the transistor; base current detecting means for outputting a base detection current according to the magnitude of the base current of the transistor; and inputting the base detection current to the base. A saturation transistor including: a replication transistor that outputs a collector replication current from a collector; and a saturation detection signal output unit that outputs a saturation detection signal according to a difference between the collector detection current and the collector replication current. 2. The collector current detecting means includes a first transistor which receives a voltage between a base and an emitter of the transistor between a base and an emitter and outputs the collector detection current from a collector. The saturation detection circuit according to claim 1. 3. The saturation detection circuit according to claim 2, wherein a junction area between the emitter and the base of the first transistor has a predetermined ratio with respect to the junction area of the transistor. 4. The base current driving means includes a second transistor which receives a predetermined voltage between a base and an emitter and inputs a base current of the transistor to a collector. The saturation detection circuit according to claim 1, further comprising a third transistor that receives the predetermined voltage between the first transistor and the emitter and outputs the base detection current from a collector. 5. The saturation detection circuit according to claim 4, wherein a junction area between the emitter and the base of the third transistor has a predetermined ratio with respect to the junction area of the second transistor. 6. The saturation detection signal output means receives the collector detection current, generates a current having a predetermined ratio with respect to the input current, and responds to a difference between the current and the collector duplicate current. The saturation detection circuit according to claim 1, further comprising a current mirror circuit that outputs the saturation detection signal. 7. An output control circuit for controlling a voltage or a current of a load receiving an output current from an output transistor, wherein a collector current detection means for outputting a collector detection current corresponding to a magnitude of a collector current of the output transistor. A base current detection means for outputting a base detection current according to the magnitude of the base current of the output transistor; a duplication transistor for inputting the base detection current to a base and outputting a collector duplication current from a collector; A saturation detection signal output unit that outputs a saturation detection signal according to a difference between the detection current and the collector duplication current; and a base current driving unit that drives a base current of the output transistor according to the saturation detection signal. Output control circuit. 8. The collector current detecting means includes a first transistor which receives a voltage between a base and an emitter of the transistor between a base and an emitter and outputs the collector detection current from a collector. The output control circuit according to claim 7. 9. The output control circuit according to claim 8, wherein a junction area between the emitter and the base of the first transistor has a predetermined ratio with respect to the junction area of the transistor. 10. The base current driving means detects a voltage or a current of the load and drives a base current of the output transistor according to an error between the detected value and a predetermined reference value and the saturation detection signal. The output control circuit according to claim 7, wherein 11. A second transistor for receiving a base drive voltage between a base and an emitter according to the error and the saturation detection signal and inputting a base current of the transistor to a collector. Wherein the base current detecting means receives the base drive voltage between a base and an emitter,
The output control circuit according to claim 10, further comprising a third transistor that outputs the base detection current from a collector. 12. The output control circuit according to claim 11, wherein a junction area between the emitter and the base of the third transistor has a predetermined ratio with respect to the junction area of the second transistor. 13. The base current driving means, comprising: an output detection means for detecting a voltage or a current of the load; and an error between a value detected by the output detection means and a predetermined reference value, wherein the error is determined in accordance with the saturation detection signal. The output control circuit according to claim 11, further comprising: an error amplifying unit configured to generate the base drive voltage amplified by a gain. 14. The base current drive means detects output voltage or current of the load, variably outputs the detected value according to the saturation detection signal, and outputs the detected value. 12. The output control circuit according to claim 11, further comprising: an error amplifier configured to generate the base drive voltage obtained by amplifying an error between the output and a predetermined reference value. 15. The base current driving means, comprising: an output detection means for detecting a voltage or a current of the load; a detection value by the output detection means; 12. The output control circuit according to claim 11, further comprising: an error amplifying unit that generates the base drive voltage obtained by amplifying the error of (a). 16. The saturation detection signal output means receives the collector detection current, generates a current having a predetermined ratio with respect to the input current, and responds to a difference between the current and the collector duplicate current. The output control circuit according to claim 7, further comprising a current mirror circuit that outputs the saturation detection signal.