JP2002057373A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JP2002057373A
JP2002057373A JP2000239707A JP2000239707A JP2002057373A JP 2002057373 A JP2002057373 A JP 2002057373A JP 2000239707 A JP2000239707 A JP 2000239707A JP 2000239707 A JP2000239707 A JP 2000239707A JP 2002057373 A JP2002057373 A JP 2002057373A
Authority
JP
Japan
Prior art keywords
semiconductor light
light emitting
emitting device
light
short
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000239707A
Other languages
Japanese (ja)
Inventor
Hiroshi Murata
博志 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000239707A priority Critical patent/JP2002057373A/en
Publication of JP2002057373A publication Critical patent/JP2002057373A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device where a flip chip light-emitting element is easily mounted and fixed on its mounting surface while the light leaking toward the mounting surface is effectively recovered on a main light take-out surface for improved luminosity. SOLUTION: A flip chip light-emitting device is provided where a transmissive substrate 1 side of a semiconductor light-emitting element A is taken as the main light take-out surface while the surface on the opposite side faces the mounting surface and electrode pads 2a and 3a on an n-side and a p-side are connected together for continuity. A short preventive band is formed on the mounting surface so that conductive bonds 14 which fix the electrode pads 2a and 3a to the mounting surface for continuity, do not contact each other. A reflective film 13 is formed on the surface of the short preventive band, over which the semiconductor light-emitting element A is mounted while the surface of a p-type layer 3 is directly contacted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、たとえば青色発光
のGaN系化合物半導体を利用したフリップチップ型の
発光素子を備える半導体発光装置に係り、特に導電性接
着剤による導通固定を有効に利用して実装面側へ漏れる
光を回収して発光輝度を改善した半導体発光装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light-emitting device having a flip-chip type light-emitting element using a GaN-based compound semiconductor emitting blue light, for example, in particular, by effectively utilizing conduction fixation with a conductive adhesive. The present invention relates to a semiconductor light emitting device in which light leaking to a mounting surface side is recovered to improve light emission luminance.

【0002】[0002]

【従来の技術】GaN,GaAlN,InGaN及びI
nAlGaN等のGaN系化合物半導体を利用した青色
発光の発光素子は、結晶成長のための基板として現在で
はサファイアが最も一般的なものとして利用されてい
る。図6にサファイアを基板とするGaN系化合物半導
体による発光素子の概略斜視図を示す。
2. Description of the Related Art GaN, GaAlN, InGaN and I
In a blue light emitting device using a GaN-based compound semiconductor such as nAlGaN, sapphire is currently most commonly used as a substrate for crystal growth. FIG. 6 is a schematic perspective view of a GaN-based compound semiconductor light emitting device using sapphire as a substrate.

【0003】図6において、サファイアの基板1の上に
GaNのn型層2及びp型層3を順に積層し、p型層3
の一部をエッチングしてn型層2の表面にn側電極パッ
ド2aを形成している。また、p型層3の表面にはp側
電極パッド3aを設け、図示の例ではこのp側電極パッ
ド3aを除いた部分にp側透光性電極3bを形成してい
る。
In FIG. 6, an n-type layer 2 and a p-type layer 3 of GaN are sequentially laminated on a sapphire substrate 1, and a p-type layer 3 is formed.
Is etched to form an n-side electrode pad 2a on the surface of the n-type layer 2. Further, a p-side electrode pad 3a is provided on the surface of the p-type layer 3, and in the illustrated example, a p-side translucent electrode 3b is formed in a portion other than the p-side electrode pad 3a.

【0004】このような半導体発光素子では、n型層2
とp型層3との間の発光層からの光は、図においてp側
透光性電極3bを抜けて上に向かうものと、基板1のサ
ファイアが光透過性であることからこの基板1を抜けて
下に向かうものとが含まれる。そして、このことを利用
して、ワイヤによるボンディングに代えて、図7に示す
ようにバンプ電極によるリードフレーム側への導通固定
としたフリップチップ型のアセンブリとすることができ
る。
In such a semiconductor light emitting device, the n-type layer 2
The light from the light emitting layer between the substrate 1 and the p-type layer 3 passes through the p-side light-transmissive electrode 3b in the figure and goes upward, and because the sapphire of the substrate 1 is light-transmissive, And those that go down. By utilizing this fact, a flip-chip type assembly in which conduction is fixed to the lead frame side by bump electrodes as shown in FIG.

【0005】図7において、n側電極パッド2a及びp
側電極パッド3aのそれぞれにはバンプ電極51,52
が予め形成され、リードフレームの一対のリード53,
54のマウント部53a,54aにこれらのバンプ電極
51,52を超音波及び加熱を利用した圧着法によって
接合している。このようなフリップチップ型のアセンブ
リでは、図7において基板1の上面を主光取出し面とし
た発光が得られる。そして、発光層から側方及びp側透
光性電極3bから下方に抜ける光の成分は、マウント部
53a,54aの表面をメッキ処理等によって反射面と
することによって、主光取出し面側に回収した発光が可
能となる。
In FIG. 7, n-side electrode pads 2a and p
The bump electrodes 51 and 52 are respectively provided on the side electrode pads 3a.
Are formed in advance, and a pair of leads 53,
The bump electrodes 51 and 52 are bonded to the mount portions 53a and 54a of the 54 by a pressure bonding method using ultrasonic waves and heating. In such a flip-chip type assembly, light emission with the upper surface of the substrate 1 as a main light extraction surface in FIG. 7 can be obtained. The components of light that escape from the light-emitting layer to the side and downward from the p-side translucent electrode 3b are collected on the main light extraction surface side by making the surfaces of the mount portions 53a and 54a reflection surfaces by plating or the like. Light emission is possible.

【0006】[0006]

【発明が解決しようとする課題】ところが、リード5
3,54は二股状に分かれたものなので、p側透光性電
極3bが対向する面にはギャップGがあり、このギャッ
プGを抜ける光については主光取出し面側への回収はで
きない。
However, the lead 5
3, 54 are bifurcated, there is a gap G on the surface facing the p-side translucent electrode 3b, and light passing through this gap G cannot be collected on the main light extraction surface side.

【0007】一方、バンプ電極51,52は、n側及び
p側の電極パッド2a,3aの厚さが薄くてマウント部
53a,54aに搭載したときの短絡防止のためのスペ
ーサを兼ねる。このためバンプ電極51,52は或る程
度の肉厚を持たせたものとなるので、p側透光性電極3
bとマウント部53a,54aとの間に隙間ができ、こ
の部分は封止樹脂の層となる。したがって、マウント部
53a,54aの搭載面を反射面としていても、p側透
光性電極3bから抜けて封止樹脂層に入りマウント部5
3a,54aの反射面で反射されて再び入射する光路と
なるので、光の有効な回収はできない。
On the other hand, the bump electrodes 51 and 52 also serve as spacers for preventing short circuit when the n-side and p-side electrode pads 2a and 3a are mounted on the mount portions 53a and 54a because of their small thickness. Therefore, the bump electrodes 51 and 52 have a certain thickness, so that the p-side translucent electrode 3
A gap is formed between b and the mounting portions 53a and 54a, and this portion becomes a layer of sealing resin. Therefore, even if the mounting surfaces of the mount portions 53a and 54a are used as reflection surfaces, the mount portions 53a and 54a enter the sealing resin layer through the p-side translucent electrode 3b and enter the mount portion 5a.
Since the light path is reflected by the reflecting surfaces 3a and 54a and re-enters the light path, the light cannot be effectively collected.

【0008】また、発光素子の静電気による破壊を防止
するため、静電気保護素子等と複合化したアセンブリと
することが既に提案されている。これは図8に示すよう
に、ツェナーダイオードを利用した静電気保護素子61
の上に図6に示した発光素子を搭載して複合化素子と
し、静電気保護素子61をリードフレームのリード62
にマウントしたものである。
Further, in order to prevent the light emitting element from being destroyed by static electricity, it has already been proposed to make an assembly combined with an electrostatic protection element or the like. As shown in FIG. 8, this is a static electricity protection element 61 using a Zener diode.
The light emitting element shown in FIG. 6 is mounted thereon to form a composite element, and the electrostatic protection element 61 is replaced by a lead 62 of a lead frame.
It is mounted on.

【0009】静電気保護素子61はたとえばn型シリコ
ン基板を用いたものでその底面に形成したn電極61c
を介してリード62に導通させるとともに、上面にn電
極61a及びn型シリコン基板の一部に形成したp型半
導体領域に対応させてp電極61bを形成したものであ
る。そして、n電極61aにp側電極パッド3a及びp
電極61bにn側電極パッド2aをバンプ51,52に
より接合して逆極性として導通させることで、高電圧に
より過電流が印加されたときには静電気保護素子61へ
電流が流され、発光素子の静電破壊を防止する。
The electrostatic protection element 61 uses, for example, an n-type silicon substrate, and has an n-electrode 61c formed on the bottom surface thereof.
The lead 62 is electrically connected to the lead 62, and an n-electrode 61a is formed on the upper surface and a p-electrode 61b is formed corresponding to a p-type semiconductor region formed in a part of the n-type silicon substrate. The p-side electrode pads 3a and p
By bonding the n-side electrode pad 2a to the electrode 61b by the bumps 51 and 52 and conducting it with the opposite polarity, when an overcurrent is applied by a high voltage, a current flows to the electrostatic protection element 61, and the static electricity of the light emitting element Prevent destruction.

【0010】このように静電気保護素子61の上に半導
体発光素子を搭載すると、p側透光性電極3bは静電気
保護素子61の上に被さるので、この静電気保護素子6
1の表面を反射面として利用すれば、主光取出し面側へ
の光の回収が可能である。
When the semiconductor light emitting element is mounted on the electrostatic protection element 61 in this way, the p-side translucent electrode 3b covers the electrostatic protection element 61, so that the electrostatic protection element 6
If the surface 1 is used as a reflection surface, light can be collected on the main light extraction surface side.

【0011】しかしながら、静電気保護素子61の表面
とp側透光性電極3bとの間にはバンプ電極51,52
によって隙間ができるので、この隙間の空気層または封
止樹脂層により図7の例と同様に光の回収が十分にでき
なくなる。
However, the bump electrodes 51 and 52 are provided between the surface of the electrostatic protection element 61 and the p-side translucent electrode 3b.
As a result, a gap is formed, so that the air layer or the sealing resin layer in the gap makes it impossible to sufficiently collect light as in the example of FIG.

【0012】このように、バンプ電極51,52による
リードフレーム側との接合では、発光素子とその搭載面
との間に隙間ができることから、フリップチップ型のア
センブリとした場合に反射光の回収効率が低下する傾向
にある。また、搭載面への接合の際には超音波等を利用
した加圧振動を加えたり溶着のための加熱を必要とする
ため、発光素子の半導体積層膜に対してダメージを与え
る恐れもあり、製品歩留りへの影響も無視できない。
As described above, when the bump electrodes 51 and 52 are joined to the lead frame side, a gap is formed between the light emitting element and the mounting surface thereof. Tends to decrease. Also, when bonding to the mounting surface, it is necessary to apply pressure vibration using ultrasonic waves or the like or to heat for welding, which may cause damage to the semiconductor laminated film of the light emitting element, The impact on product yield cannot be ignored.

【0013】本発明において解決すべき課題は、フリッ
プチップ型の発光素子をその実装面に簡単に搭載固定で
きるとともに実装面方向に漏れる光を有効に主光取出し
面側に回収して発光輝度の向上が図れる半導体発光装置
を提供することにある。
The problem to be solved in the present invention is that a flip-chip type light emitting element can be easily mounted and fixed on its mounting surface, and light leaking in the direction of the mounting surface can be effectively collected on the main light extraction surface side to reduce the emission luminance. An object of the present invention is to provide a semiconductor light emitting device that can be improved.

【0014】[0014]

【課題を解決するための手段】本発明は、光透過性の基
板の上に化合物半導体を積層するとともにこの積層体の
表面側にp側及びn側の電極をそれぞれ形成した半導体
発光素子と、前記p側及びn側の電極を実装面に導通搭
載して前記基板側を主光取出し面とする半導体発光装置
であって、前記実装面には、前記n側及びp側の電極の
間を抜ける位置関係として短絡防止帯を設け、前記n側
及びp側の電極と前記実装面の導通接続部との間を、前
記短絡防止帯によって区画されたそれぞれの領域におい
て導電性接着剤により接合してなることを特徴とする。
According to the present invention, there is provided a semiconductor light emitting device in which a compound semiconductor is laminated on a light-transmitting substrate and p-side and n-side electrodes are formed on the surface of the laminate, respectively. A semiconductor light emitting device in which the p-side and n-side electrodes are conductively mounted on a mounting surface and the substrate side is a main light extraction surface, wherein the mounting surface has a space between the n-side and p-side electrodes. A short-circuit prevention band is provided as a positional relationship to be removed, and the n-side and p-side electrodes and the conductive connection portion of the mounting surface are joined by a conductive adhesive in respective regions partitioned by the short-circuit prevention band. It is characterized by becoming.

【0015】このような構成では、導電性接着剤を使用
しても半導体発光素子のp側及びn側の間に介在する短
絡防止帯によって、p側及びn側のそれぞれを搭載面側
に接合する導電性接着剤が接触することがなく、短絡が
防止される。そして、導電性接着剤の厚さを適切にする
ことによって、半導体発光素子の積層膜の表面を短絡防
止帯の表面に近づけるとができ、この短絡防止帯の表面
を光反射性としておけば主光取出し面側への光の反射効
率を上げることができる。
In such a configuration, even when a conductive adhesive is used, the p-side and the n-side are respectively joined to the mounting surface by the short-circuit prevention band interposed between the p-side and the n-side of the semiconductor light emitting device. The conductive adhesive does not come into contact with the conductive adhesive, thereby preventing a short circuit. By appropriately setting the thickness of the conductive adhesive, the surface of the laminated film of the semiconductor light emitting element can be brought closer to the surface of the short-circuit prevention band. The efficiency of light reflection on the light extraction surface side can be increased.

【0016】[0016]

【発明の実施の形態】請求項1に記載の発明は、光透過
性の基板の上に化合物半導体を積層するとともにこの積
層体の表面側にp側及びn側の電極をそれぞれ形成した
半導体発光素子と、前記p側及びn側の電極を実装面に
導通搭載して前記基板側を主光取出し面とする半導体発
光装置であって、前記実装面には、前記n側及びp側の
電極の間を抜ける位置関係として短絡防止帯を設け、前
記n側及びp側の電極と前記実装面の導通接続部との間
を、前記短絡防止帯によって区画されたそれぞれの領域
において導電性接着剤により接合してなる半導体発光装
置であり、短絡防止帯によって、p側及びn側のそれぞ
れを搭載面側に接合する導電性接着剤が接触することが
なく、短絡を防止できるという作用を有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, there is provided a semiconductor light emitting device in which a compound semiconductor is laminated on a light-transmitting substrate and p-side and n-side electrodes are formed on the surface side of the laminated body. An element and a semiconductor light emitting device in which the p-side and n-side electrodes are conductively mounted on a mounting surface and the substrate side is a main light extraction surface, and the mounting surface includes the n-side and p-side electrodes. A short-circuit prevention band is provided as a positional relationship between the n-side and p-side electrodes and the conductive connection portion of the mounting surface, and a conductive adhesive is provided in each region partitioned by the short-circuit prevention band. The short-circuit prevention band has the effect of preventing the conductive adhesive bonding the p-side and the n-side from each other to the mounting surface, thereby preventing a short circuit.

【0017】請求項2に記載の発明は、前記短絡防止帯
の表面を、前記化合物半導体の積層膜の表面からの光を
前記主光取出し面方向に反射させる反射面とし、前記積
層膜の表面を前記反射面に密着させてなる請求項1記載
の半導体発光装置であり、積層膜の表面から抜ける光を
短絡防止帯の表面に形成した反射面から直接反射させる
ので、主光取出し面側への光の回収効率を上げるという
作用を有する。
According to a second aspect of the present invention, the surface of the short-circuit prevention band is a reflecting surface for reflecting light from the surface of the compound semiconductor laminated film in the direction of the main light extraction surface. 2. The semiconductor light emitting device according to claim 1, wherein the light exiting from the surface of the laminated film is directly reflected from the reflection surface formed on the surface of the short-circuit prevention band, so that the light exits toward the main light extraction surface. Has the effect of increasing the light collection efficiency.

【0018】請求項3に記載の発明は、前記反射面を前
記短絡防止帯の表面に形成した光反射性の膜としてなる
請求項2記載の半導体発光装置であり、実装面が光反射
性のない素材であっても反射性の膜を形成するだけでよ
く、多様な実装面の種類に対応できるという作用を有す
る。
According to a third aspect of the present invention, there is provided the semiconductor light emitting device according to the second aspect, wherein the reflection surface is formed as a light-reflective film formed on the surface of the short-circuit prevention band. Even if there is no material, it is only necessary to form a reflective film, and it has an effect that it can cope with various types of mounting surfaces.

【0019】以下に、本発明の実施の形態の具体例を図
面を参照しながら説明する。
A specific example of the embodiment of the present invention will be described below with reference to the drawings.

【0020】図1は本発明の半導体発光装置の要部を示
す縦断面図、図2は半導体発光素子を除いて示す平面図
である。
FIG. 1 is a longitudinal sectional view showing a main part of a semiconductor light emitting device of the present invention, and FIG. 2 is a plan view showing the semiconductor light emitting device excluding a semiconductor light emitting element.

【0021】なお、本実施の形態は、最終工程において
レンズ機能を兼ねる樹脂によって樹脂封止されるLED
ランプの例であり、また半導体発光素子は図6の例で示
したものと同様なので、同じ構成部材については共通の
符号で指示する。
In this embodiment, an LED resin-sealed with a resin also having a lens function in the final step
This is an example of a lamp, and the semiconductor light emitting element is the same as that shown in the example of FIG.

【0022】図1において、プリント配線基板(図示せ
ず)等に導通固定される二股状のリードフレームの一対
のリード4,5の上端にそれぞれ半円形状の平面形状で
あってその内周壁をすり鉢状に傾斜させたマウント部4
a,5aが形成され、これらのマウント部4a,5aに
跨がせて半導体発光素子Aを導通固定している。
In FIG. 1, the upper ends of a pair of leads 4 and 5 of a bifurcated lead frame conductively fixed to a printed wiring board (not shown) or the like are respectively formed in a semicircular planar shape and the inner peripheral wall thereof is formed. Mount part 4 inclined in a mortar shape
a, 5a are formed, and the semiconductor light emitting element A is conductively fixed across the mount portions 4a, 5a.

【0023】リード4,5のマウント部4a,5aの底
面及び内周面は素材の金属光沢またはメッキを施すこと
によって半導体発光素子Aから下方向及び側方に抜ける
光の反射面とする。
The bottom surfaces and the inner peripheral surfaces of the mounting portions 4a and 5a of the leads 4 and 5 are made to have a metallic reflecting surface or a metal reflecting surface, and are formed as a reflecting surface for the light emitted downward and laterally from the semiconductor light emitting element A.

【0024】半導体発光素子Aは、図6の例と同様に、
サファイアを利用した基板1、GaNのn型層2とp型
層3、n側電極パッド2aとp側電極パッド3aを備え
たものである。そして、基板1のサファイアは透明であ
ることから、n型層2とp型層3との間の発光層からの
光はこの基板1の表面(図1においては上面)を主光取
出し面として放出される。また、金属蒸着法によって形
成されるp側電極パッド3aを除いたp型層3の表面の
全体が発光面となり、この発光面からマウント部4a,
5aへ光が放出される。なお、図6の例に示したよう
に、p型層3の表面に透光性の電極を形成したものとし
てもよい。
The semiconductor light emitting element A is similar to the example shown in FIG.
A substrate 1 using sapphire, an n-type layer 2 and a p-type layer 3 of GaN, an n-side electrode pad 2a and a p-side electrode pad 3a are provided. Since the sapphire of the substrate 1 is transparent, the light from the light emitting layer between the n-type layer 2 and the p-type layer 3 uses the surface of the substrate 1 (the upper surface in FIG. 1) as the main light extraction surface. Released. In addition, the entire surface of the p-type layer 3 excluding the p-side electrode pad 3a formed by the metal deposition method becomes a light emitting surface.
Light is emitted to 5a. In addition, as shown in the example of FIG. 6, a light-transmitting electrode may be formed on the surface of the p-type layer 3.

【0025】マウント部4a,5aの間には絶縁パッド
6を本実施の形態における短絡防止帯として架け渡して
固定するとともに、この絶縁パッド6の表面には反射膜
7を一体に形成する。絶縁パッド6は半導体発光素子A
の搭載荷重に耐える機械的強度を持つ樹脂プレート等を
素材として予めマウント部4a,5aの表面に溶着法等
によって固定されたものである。また、反射膜7は絶縁
性であってたとえばAg,Al,Pt等の銀白色系金属
膜をSiOXやSiNX等の絶縁膜で覆ったものが利用で
き、絶縁パッド6の表面に予め一体に積層されたもので
ある。
An insulating pad 6 is stretched and fixed between the mount portions 4a and 5a as a short-circuit prevention band in the present embodiment, and a reflective film 7 is integrally formed on the surface of the insulating pad 6. The insulating pad 6 is a semiconductor light emitting element A
Is fixed in advance to the surfaces of the mount portions 4a and 5a by a welding method or the like using a resin plate or the like having mechanical strength to withstand the mounting load of the above. The reflection film 7 is insulative. For example, a film in which a silver-white metal film such as Ag, Al, or Pt is covered with an insulation film such as SiO X or SiN X can be used. Are laminated.

【0026】絶縁パッド6は図2に示すように、半導体
発光素子Aのn側及びp側の電極のパッド2a,3aが
重なる部分を切り欠いた平面形状を持つ。そして、反射
膜7はp側電極パッド3aを除くp型層3の表面の全体
に一致するように形成することが好ましいが、加工上の
点から絶縁パッド6の表面の全体に形成しても何ら支障
はない。
As shown in FIG. 2, the insulating pad 6 has a planar shape in which a portion where the pads 2a and 3a of the n-side and p-side electrodes of the semiconductor light emitting element A overlap is cut out. The reflection film 7 is preferably formed so as to correspond to the entire surface of the p-type layer 3 except for the p-side electrode pad 3a. No problem.

【0027】このような、反射膜7を形成した絶縁パッ
ド6をマウント部4a,5aの間に備えたリードフレー
ムに対し、半導体発光素子Aは図1に示すようにp型層
3の表面を反射膜7に接触させてAgペースト等の導電
性接着剤8によって固定される。このとき、導電性接着
剤8はn側及びp側の電極パッド2a,3aに対応する
ようにマウント部4a,5aの表面に予め塗布してお
き、半導体発光装置Aの姿勢を決めて図示のように搭載
する。
In contrast to such a lead frame having the insulating pad 6 on which the reflective film 7 is formed between the mount portions 4a and 5a, the semiconductor light emitting element A has the surface of the p-type layer 3 as shown in FIG. It is fixed by a conductive adhesive 8 such as an Ag paste in contact with the reflection film 7. At this time, the conductive adhesive 8 is applied in advance to the surfaces of the mount portions 4a and 5a so as to correspond to the n-side and p-side electrode pads 2a and 3a, and the posture of the semiconductor light emitting device A is determined in FIG. To be mounted.

【0028】以上の構成において、半導体発光装置Aの
n側及びp側の電極パッド2a,3aは導電性接着剤8
によってリード4,5に導通して固定される。この場
合、バンプ電極を利用するときのような超音波圧着や加
熱溶着の必要がないので、n型層2やp型層3等の積層
膜に対する機械的な負荷が小さくて済み、そのダメージ
の発生が抑えられる。そして、マウント部4a,5a側
のそれぞれに別けて塗布された導電性接着剤8どうしの
間には絶縁パッド6が介在しているので、これらの導電
性接着剤8の流れ出しによる短絡の発生も防止される。
In the above configuration, the n-side and p-side electrode pads 2a and 3a of the semiconductor light emitting device A are electrically conductive adhesive 8
Thus, the leads 4 and 5 are electrically connected and fixed. In this case, since there is no need to perform ultrasonic pressure bonding or heat welding as when using a bump electrode, the mechanical load on the stacked films such as the n-type layer 2 and the p-type layer 3 can be reduced, and the damage can be reduced. Generation is suppressed. Since the insulating pads 6 are interposed between the conductive adhesives 8 separately applied to the mount portions 4a and 5a, a short circuit due to the outflow of the conductive adhesives 8 may occur. Is prevented.

【0029】また、p型層3の表面は絶縁パッド6の表
面の反射膜7に密着させることで、発光面となるp型層
3の表面と反射膜7との間には隙間がない。すなわち、
p型層3の表面と反射膜7とは密着しているので、p型
層3の表面が殆ど反射面そのものとなり、発光層からの
光がp型層3から外に出ない条件とほぼ同じとして反射
させることができる。したがって、従来のようにp型層
3から出た光が封止樹脂の層からマウント部へ向かって
再び戻るような光路とはならないので、主光取出し面側
への反射効率が高くなり、その結果発光輝度も向上す
る。
The surface of the p-type layer 3 is adhered to the reflection film 7 on the surface of the insulating pad 6, so that there is no gap between the surface of the p-type layer 3 serving as a light emitting surface and the reflection film 7. That is,
Since the surface of the p-type layer 3 and the reflective film 7 are in close contact with each other, the surface of the p-type layer 3 becomes almost the reflection surface itself, which is almost the same as the condition in which light from the light emitting layer does not go out of the p-type layer 3. Can be reflected as Therefore, the light emitted from the p-type layer 3 does not have an optical path that returns from the sealing resin layer toward the mount portion as in the related art, so that the reflection efficiency to the main light extraction surface side is increased, and As a result, the light emission luminance is also improved.

【0030】図3は半導体発光素子を静電気保護素子と
ともに複合化素子としたLEDランプの縦断面図であ
る。
FIG. 3 is a longitudinal sectional view of an LED lamp in which a semiconductor light emitting device is combined with an electrostatic protection device together with an electrostatic protection device.

【0031】図3において、リードフレーム9のリード
9a,9bの一方に形成したマウント部9cに静電気保
護素子としてSiダイオード10が導通搭載され、この
Siダイオード10に半導体発光素子Aが搭載されてい
る。そして、Siダイオード10とリード9bとの間を
ワイヤ11でボンディングするとともに、このワイヤ1
1を含んでエポキシ樹脂12によって封止されている。
In FIG. 3, a Si diode 10 is conductively mounted as an electrostatic protection element on a mount 9c formed on one of the leads 9a and 9b of the lead frame 9, and a semiconductor light emitting element A is mounted on the Si diode 10. . Then, the wire 11 is bonded between the Si diode 10 and the lead 9 b with a wire 11.
1 is sealed by the epoxy resin 12.

【0032】図4は半導体発光素子AとSiダイオード
10の導通搭載構造を示す概略縦断面図、図5はSiダ
イオード10の表面の外郭形状を示す斜視図である。
FIG. 4 is a schematic longitudinal sectional view showing a conductive mounting structure of the semiconductor light emitting element A and the Si diode 10, and FIG. 5 is a perspective view showing an outer shape of the surface of the Si diode 10.

【0033】Siダイオード10はn型シリコン基板1
0aの底面にn電極10bを備えるとともに上面側から
p型不純物を部分的に注入してp型半導体領域10cを
形成したものである。そして、このp型半導体領域10
cに接合したp側電極10dを設け、これと対角線方向
に離れた位置にn側電極10eを形成し、p側電極10
dの表面にワイヤ11がボンディングされている。
The Si diode 10 is an n-type silicon substrate 1
An n-electrode 10b is provided on the bottom surface of Oa, and a p-type impurity is partially implanted from the upper surface to form a p-type semiconductor region 10c. Then, the p-type semiconductor region 10
c, a p-side electrode 10d is provided, and an n-side electrode 10e is formed at a position diagonally away from the p-side electrode 10d.
The wire 11 is bonded to the surface of d.

【0034】Siダイオード10のn型シリコン基板1
0aは、図5に示すように、2か所に接合用の凹部10
f,10gを設け、これらの凹部10f,10gの間を
本実施の形態における短絡防止帯としての隔壁10hと
するとともに、その表面に反射膜13を一体に接合して
いる。一方の凹部10fにはワイヤ11のボンディング
部から連ねて先に説明したp側電極10dを積層形成
し、他方の凹部10gにはn側電極10eが位置してい
る。
The n-type silicon substrate 1 of the Si diode 10
0a has two concave portions 10 for joining as shown in FIG.
f, 10g are provided, the space between these recesses 10f, 10g is a partition wall 10h as a short-circuit prevention band in the present embodiment, and a reflective film 13 is integrally bonded to the surface thereof. In the one concave portion 10f, the p-side electrode 10d described above is formed by lamination from the bonding portion of the wire 11, and in the other concave portion 10g, the n-side electrode 10e is located.

【0035】このようなSiダイオード10に対し、半
導体発光素子Aは図4に示すように、n側電極パッド2
aを一方の凹部10fに対応させるとともにp側電極パ
ッド3aを他方の凹部10gに対応させて搭載する。そ
して、n側電極パッド2aとp側電極10d及びp側電
極パッド3aとn側電極10eそれぞれを先の例と同様
にAgペースト等の導電性接着剤14によって接合す
る。このとき、p型層3の表面がSiダイオード10の
隔壁10hの上面に形成した反射膜13に密着するよう
に各部の寸法関係を決める。
In contrast to such a Si diode 10, the semiconductor light emitting element A has an n-side electrode pad 2 as shown in FIG.
a is made to correspond to one recess 10f, and the p-side electrode pad 3a is mounted to correspond to the other recess 10g. Then, each of the n-side electrode pad 2a and the p-side electrode 10d and the p-side electrode pad 3a and the n-side electrode 10e are joined by a conductive adhesive 14 such as an Ag paste in the same manner as in the previous example. At this time, the dimensional relationship of each part is determined so that the surface of the p-type layer 3 is in close contact with the reflective film 13 formed on the upper surface of the partition 10h of the Si diode 10.

【0036】このようにSiダイオード10とともに複
合素子化する構成でも、p型層3の表面を反射膜13に
密着させることで、Siダイオード10側に抜ける光を
主光取出し面側へ効率的に反射させることができ、発光
輝度の向上が可能となる。また、導電性接着剤14は凹
部10f,10gの中に塗布されて互いを隔壁10hに
より分断しているので、相互の短絡の発生がないアセン
ブリが可能となる。
As described above, even in a configuration in which a composite element is formed together with the Si diode 10, the surface of the p-type layer 3 is brought into close contact with the reflective film 13 so that light that escapes toward the Si diode 10 is efficiently directed to the main light extraction surface. The light can be reflected, and the emission luminance can be improved. In addition, since the conductive adhesive 14 is applied in the recesses 10f and 10g and is separated from each other by the partition 10h, an assembly that does not cause a mutual short circuit can be realized.

【0037】[0037]

【発明の効果】請求項1の発明では、導電性接着剤を用
いても短絡防止帯によって短絡が防止できるので、バン
プ電極を用いる接合に比べると半導体発光素子とその実
装面との間の間隔を短くできるアセンブリが可能とな
り、また加熱圧着等の負荷を伴わないので半導体積層膜
にダメージを与えることがなく、製品歩留りの向上が図
られる。
According to the first aspect of the present invention, even if a conductive adhesive is used, a short circuit can be prevented by the short prevention band, so that the gap between the semiconductor light emitting element and its mounting surface can be reduced as compared with bonding using a bump electrode. In this case, the assembly can be shortened, and no load such as heat compression is applied, so that the semiconductor laminated film is not damaged and the product yield is improved.

【0038】請求項2の発明では、積層膜の表面から抜
ける光を短絡防止帯の表面に形成した反射面から直接反
射させるので、封止樹脂層等による干渉がなく、主光取
出し面からの発光輝度を上げることができる。
According to the second aspect of the present invention, light that escapes from the surface of the laminated film is directly reflected from the reflection surface formed on the surface of the short-circuit prevention band. Light emission luminance can be increased.

【0039】請求項3の発明では、実装面が光反射性の
ない素材であっても反射性の膜を形成するだけでよいの
で、実装面が金属光沢を持たないものでも対応でき、設
計の自由度を高めることができる。
According to the third aspect of the present invention, it is only necessary to form a reflective film even if the mounting surface is made of a material having no light reflectivity. The degree of freedom can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態による半導体発光装置の
要部を示す概略縦断面図
FIG. 1 is a schematic longitudinal sectional view showing a main part of a semiconductor light emitting device according to an embodiment of the present invention.

【図2】図1の半導体発光装置の半導体発光素子を除い
て示す平面図
FIG. 2 is a plan view showing the semiconductor light emitting device of FIG. 1 except for a semiconductor light emitting element;

【図3】半導体発光素子を静電気保護用のSiダイオー
ドとともに複合素子化したものを含むLEDランプの縦
断面図
FIG. 3 is a vertical cross-sectional view of an LED lamp including a semiconductor light-emitting element formed into a composite element together with a Si diode for electrostatic protection.

【図4】図3の例におけるSiダイオードと半導体発光
素子の導通搭載構造を示す縦断面図
FIG. 4 is a longitudinal sectional view showing a conductive mounting structure of a Si diode and a semiconductor light emitting element in the example of FIG. 3;

【図5】Siダイオードの外郭形状を示す概略斜視図FIG. 5 is a schematic perspective view showing the outer shape of a Si diode.

【図6】GaN系化合物半導体発光素子の概略斜視図FIG. 6 is a schematic perspective view of a GaN-based compound semiconductor light emitting device.

【図7】バンプ電極による半導体発光素子のリードフレ
ームへの従来の搭載構造を示す縦断面図
FIG. 7 is a longitudinal sectional view showing a conventional mounting structure of a semiconductor light emitting element on a lead frame using bump electrodes.

【図8】静電気保護素子の上に半導体発光素子をバンプ
電極によって接合して複合素子化した従来例を示す概略
FIG. 8 is a schematic view showing a conventional example in which a semiconductor light emitting element is joined to an electrostatic protection element by a bump electrode to form a composite element.

【符号の説明】[Explanation of symbols]

1 基板 2 n型層 2a n側電極パッド 3 p型層 3a p側電極パッド 3b p側透光性電極 4,5 リード 4a,5a マウント部 6 絶縁パッド 7 反射膜 8 導電性接着剤 9 リードフレーム 9a,9b リード 9c マウント部 10 Siダイオード 10a n型シリコン基板 10b n電極 10c p型半導体領域 10d p側電極 10e n側電極 10f,10g 凹部 10h 隔壁 11 ワイヤ 12 エポキシ樹脂 13 反射膜 14 導電性接着剤 Reference Signs List 1 substrate 2 n-type layer 2a n-side electrode pad 3 p-type layer 3a p-side electrode pad 3b p-side translucent electrode 4,5 lead 4a, 5a mount 6 insulating pad 7 reflective film 8 conductive adhesive 9 lead frame 9a, 9b Lead 9c Mount 10 Si diode 10a n-type silicon substrate 10b n-electrode 10c p-type semiconductor region 10d p-side electrode 10en n-side electrode 10f, 10g recess 10h partition 11 wire 12 epoxy resin 13 reflective film 14 conductive adhesive

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 光透過性の基板の上に化合物半導体を積
層するとともにこの積層体の表面側にp側及びn側の電
極をそれぞれ形成した半導体発光素子と、前記p側及び
n側の電極を実装面に導通搭載して前記基板側を主光取
出し面とする半導体発光装置であって、 前記実装面には、前記n側及びp側の電極の間を抜ける
位置関係として短絡防止帯を設け、 前記n側及びp側の電極と前記実装面の導通接続部との
間を、前記短絡防止帯によって区画されたそれぞれの領
域において導電性接着剤により接合してなる半導体発光
装置。
1. A semiconductor light emitting device comprising: a compound semiconductor layered on a light-transmitting substrate; and a p-side electrode and an n-side electrode formed on the surface of the layered body, respectively; A semiconductor light emitting device having the substrate side as a main light extraction surface by conductively mounting the substrate on a mounting surface, wherein the mounting surface has a short-circuit prevention band as a positional relationship passing between the n-side and p-side electrodes. A semiconductor light-emitting device comprising: an n-side electrode and a p-side electrode; and a conductive connection portion of the mounting surface, which is joined by a conductive adhesive in respective regions defined by the short-circuit prevention band.
【請求項2】 前記短絡防止帯の表面を、前記化合物半
導体の積層膜の表面からの光を前記主光取出し面方向に
反射させる反射面とし、前記積層膜の表面を前記反射面
に密着させてなる請求項1記載の半導体発光装置。
2. The surface of the short-circuit prevention band is a reflecting surface for reflecting light from the surface of the compound semiconductor laminated film in the direction of the main light extraction surface, and the surface of the laminated film is brought into close contact with the reflecting surface. The semiconductor light emitting device according to claim 1, wherein:
【請求項3】 前記反射面を前記短絡防止帯の表面に形
成した光反射性の膜としてなる請求項2記載の半導体発
光装置。
3. The semiconductor light emitting device according to claim 2, wherein said reflection surface is a light-reflective film formed on a surface of said short-circuit prevention band.
JP2000239707A 2000-08-08 2000-08-08 Semiconductor light-emitting device Withdrawn JP2002057373A (en)

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
JP2005150386A (en) * 2003-11-14 2005-06-09 Stanley Electric Co Ltd Semiconductor device and its manufacturing method
JP2008016583A (en) * 2006-07-05 2008-01-24 Nichia Chem Ind Ltd Light emitting device
CN100375300C (en) * 2003-11-25 2008-03-12 葛世潮 High power LED
CN100423298C (en) * 2004-02-27 2008-10-01 沈育浓 Encapsulation body for packaging LED wafer
JP2011258801A (en) * 2010-06-10 2011-12-22 Citizen Electronics Co Ltd Light-emitting diode
WO2015133705A1 (en) * 2014-03-05 2015-09-11 주식회사 루멘스 Light emitting device package, backlight unit, lighting device, and method for manufacturing light emitting device package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150386A (en) * 2003-11-14 2005-06-09 Stanley Electric Co Ltd Semiconductor device and its manufacturing method
JP4580633B2 (en) * 2003-11-14 2010-11-17 スタンレー電気株式会社 Semiconductor device and manufacturing method thereof
CN100375300C (en) * 2003-11-25 2008-03-12 葛世潮 High power LED
CN100423298C (en) * 2004-02-27 2008-10-01 沈育浓 Encapsulation body for packaging LED wafer
JP2008016583A (en) * 2006-07-05 2008-01-24 Nichia Chem Ind Ltd Light emitting device
JP2011258801A (en) * 2010-06-10 2011-12-22 Citizen Electronics Co Ltd Light-emitting diode
WO2015133705A1 (en) * 2014-03-05 2015-09-11 주식회사 루멘스 Light emitting device package, backlight unit, lighting device, and method for manufacturing light emitting device package
JP2016515310A (en) * 2014-03-05 2016-05-26 ルーメンス カンパニー リミテッド LIGHT EMITTING ELEMENT PACKAGE, BACKLIGHT UNIT, LIGHTING DEVICE, AND LIGHT EMITTING ELEMENT PACKAGE MANUFACTURING METHOD
US9397278B2 (en) 2014-03-05 2016-07-19 Lumens Co., Ltd. Light emitting device package, backlight unit, lighting device and its manufacturing method
US9570664B2 (en) 2014-03-05 2017-02-14 Lumens Co., Ltd. Light emitting device package, backlight unit, lighting device and its manufacturing method

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