JPH11214747A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JPH11214747A
JPH11214747A JP1247698A JP1247698A JPH11214747A JP H11214747 A JPH11214747 A JP H11214747A JP 1247698 A JP1247698 A JP 1247698A JP 1247698 A JP1247698 A JP 1247698A JP H11214747 A JPH11214747 A JP H11214747A
Authority
JP
Japan
Prior art keywords
light emitting
emitting element
emitting device
light
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1247698A
Other languages
Japanese (ja)
Inventor
Kenichi Koya
賢一 小屋
研一 ▲真▼田
Kenichi Sanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1247698A priority Critical patent/JPH11214747A/en
Publication of JPH11214747A publication Critical patent/JPH11214747A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device which is compact, low in height, and capable of protecting a light-emitting element against damages due to static electricity. SOLUTION: A semiconductor light-emitting device equipped with a a Zener diode 6 for protecting a flip chip-type light-emitting element 1 against static electricity is mounted on a board 10, the light-emitting element 1 is mounted on the Zener diode 6 making its electrode electrically connected opposite in polarity to that of the Zener diode 6, and the side of the light-emitting device 1 opposite to its mounting side is made to serve as a main light extracting surface. In this case, the Zener diode 6 is possessed of a main surface which is composed of an element-mounting plane where the light-emitting element 1 is mounted and a bonding plane which is lower in level than the element mounting plane and where a wire 12 is bonded, and provided that the Zener diode 6 is of n-type silicon board, a p-type semiconductor region is provided at a prescribed position by diffusion, whereby the Zener diode 6 is connected electrically to the light-emitting element 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、フリップチップ型
の発光素子を静電気保護素子とともに複合素子化した半
導体発光装置に係り、特に複合素子の高さ方向の嵩を小
さくして薄型化を可能とした半導体発光装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light-emitting device in which a flip-chip type light-emitting element is combined with an electrostatic protection element as a composite element. And a semiconductor light emitting device.

【０００２】[0002]

【従来の技術】ＧａＮ，ＧａＡｌＮ，ＩｎＧａＮ及びＩ
ｎＡｌＧａＮ等の窒化ガリウム系化合物の半導体の製造
では、その表面において半導体膜を成長させるための結
晶基板として、一般的には絶縁性のサファイアが利用さ
れる。このサファイアのような絶縁性の結晶基板を用い
る場合では、結晶基板側から電極を出すことができない
ので、半導体層に設けるｐ，ｎの電極は結晶基板と対向
する側の一面に形成されることになる。2. Description of the Related Art GaN, GaAlN, InGaN and I
In the production of gallium nitride based semiconductors such as nAlGaN, insulating sapphire is generally used as a crystal substrate for growing a semiconductor film on the surface. When an insulating crystal substrate such as sapphire is used, electrodes cannot be provided from the crystal substrate side, so that the p and n electrodes provided on the semiconductor layer are formed on one surface facing the crystal substrate. become.

【０００３】たとえば、ＧａＮ系化合物半導体を利用し
た発光素子は、絶縁性の基板としてサファイア基板を用
いてその上面にｎ型層及びｐ型層を有機金属気相成長法
によって積層形成し、ｐ型層の一部をエッチングしてｎ
型層を露出させ、これらのｎ型層とｐ型層のそれぞれに
ｎ側電極及びｐ側電極を形成するというものがその基本
的な構成である。そして、ｐ側電極を透明電極とした場
合であれば、これらのｐ側及びｎ側の電極にそれぞれボ
ンディングパッド部を形成して、リードフレームや基板
にそれぞれワイヤボンディングされる。For example, a light-emitting device using a GaN-based compound semiconductor uses a sapphire substrate as an insulating substrate, and forms an n-type layer and a p-type layer on the upper surface thereof by metal organic chemical vapor deposition to form a p-type layer. Etch part of the layer to n
The basic configuration is that the mold layer is exposed and an n-side electrode and a p-side electrode are formed on each of the n-type layer and the p-type layer. If the p-side electrode is a transparent electrode, bonding pads are formed on these p-side and n-side electrodes, respectively, and wire-bonded to a lead frame or a substrate.

【０００４】一方、サファイア基板側から光を取り出す
ようにしたフリップチップ型の半導体発光素子では、ｐ
側電極を透明電極としないままでこのｐ側及びｎ側の電
極のそれぞれにマイクロバンプを形成し、これらのマイ
クロバンプを基板またはリードフレームのｐ側及びｎ側
に接続する。On the other hand, in a flip-chip type semiconductor light emitting device in which light is extracted from the sapphire substrate,
Micro-bumps are formed on each of the p-side and n-side electrodes without using the side electrodes as transparent electrodes, and these micro-bumps are connected to the p-side and n-side of the substrate or lead frame.

【０００５】図５はフリップチップ型の半導体発光素子
を利用した基板タイプのチップＬＥＤの概略を示す縦断
面図である。FIG. 5 is a longitudinal sectional view schematically showing a substrate type chip LED using a flip-chip type semiconductor light emitting device.

【０００６】図において、発光素子５１は、絶縁性の透
明なサファイア基板５１ａの表面に半導体化合物層を積
層して、たとえばその中の一つの層として形成されるＩ
ｎＧａＮ活性層を発光層としたものである。そして、ｎ
型層の上面にｎ側電極５２が、及びｐ型層の上面にはｐ
側電極５３がそれぞれ蒸着法によって形成され、これら
のｎ側電極５２及びｐ側電極５３の上にはそれぞれマイ
クロバンプ５４，５５を形成している。そして、発光素
子５１には外部から静電気等の過電流が印加されないよ
うにしてその破壊を防止するため、静電気保護素子とし
てツェナーダイオード５７を設け、発光素子５１ととも
に複合素子化している。In FIG. 1, a light emitting element 51 is formed by laminating a semiconductor compound layer on the surface of an insulating transparent sapphire substrate 51a and forming, for example, one of the layers therein.
The nGaN active layer is a light emitting layer. And n
An n-side electrode 52 is provided on the upper surface of the p-type layer, and a p-type electrode 52 is provided on the upper surface of the p-type layer.
Side electrodes 53 are formed by vapor deposition, and micro bumps 54 and 55 are formed on the n-side electrode 52 and the p-side electrode 53, respectively. The light emitting element 51 is provided with a Zener diode 57 as an electrostatic protection element in order to prevent an overcurrent such as static electricity from being applied from the outside and prevent its destruction.

【０００７】一方、基板５６は、前記複合素子化した発
光素子５１を搭載する側及び発光素子５１のｎ側とをワ
イヤでボンディング接続する側に配線パターン５６ａ，
５６ｂをそれぞれ設けたものである。On the other hand, the substrate 56 has a wiring pattern 56a on the side on which the light emitting element 51 as the composite element is mounted and the side on which the n side of the light emitting element 51 is connected by bonding with a wire.
56b are provided.

【０００８】配線パターン５６ａの上には、前記複合素
子化した発光素子５１とツェナーダイオード５７が搭載
される。The light emitting element 51 and the zener diode 57 are mounted on the wiring pattern 56a.

【０００９】このツェナーダイオード５７は、導電性の
Ａｇペースト５８によって配線パターン５６ａに接着固
定されるもので、ｎ型シリコン基板５７ｃを基材とした
ものであり、その底面に配線パターン５６ａと導通させ
るためのｎ電極５７ｄを設けるとともに、上面にはその
表面の一部を除いて被覆する絶縁膜５７ｅを形成してい
る。そしてｎ型シリコン基板５７ｃの上面の一部がｐ型
半導体領域５７ｆとして拡散形成され、このｐ型半導体
領域５７ｆに対応する位置にｐ側電極５７ａを形成する
とともにｎ側電極５７ｂはｎ型半導体領域に接合されて
いる。なお、ｐ型半導体領域５７ｆは、ｎ型シリコン基
板５７ｃの上面の一部のみからｐ型不純物イオンを注入
して形成されるもので、その拡散領域はイオン注入量及
び注入領域によって一義的に決められる。The Zener diode 57 is adhered and fixed to the wiring pattern 56a by a conductive Ag paste 58, has an n-type silicon substrate 57c as a base material, and is electrically connected to the wiring pattern 56a on its bottom surface. And an insulating film 57e covering the top surface except for a part of the surface. A part of the upper surface of the n-type silicon substrate 57c is diffused and formed as a p-type semiconductor region 57f. A p-side electrode 57a is formed at a position corresponding to the p-type semiconductor region 57f, and the n-side electrode 57b is Is joined to. The p-type semiconductor region 57f is formed by implanting p-type impurity ions only from a part of the upper surface of the n-type silicon substrate 57c, and the diffusion region is uniquely determined by the ion implantation amount and the implantation region. Can be

【００１０】発光素子５１は、サファイア基板５１ａが
上面を向く姿勢としてツェナーダイオード５７の上に搭
載され、ｎ側及びｐ側のマイクロバンプ５４，５５をそ
れぞれツェナーダイオード５７の電極５７ａ，５７ｂに
接合することによって電気的に導通させる。また、ツェ
ナーダイオード５７のｐ側電極５７ａと配線パターン５
６ｂとの間をワイヤ５９によってボンディングするとと
もに、このワイヤ５９を含めて全体をエポキシ樹脂６０
によって封止することにより、図示の形状のチップＬＥ
Ｄが構成される。The light emitting element 51 is mounted on a Zener diode 57 with the sapphire substrate 51a facing upward, and the n-side and p-side micro bumps 54, 55 are joined to the electrodes 57a, 57b of the Zener diode 57, respectively. In this way, electrical conduction is achieved. The p-side electrode 57a of the Zener diode 57 and the wiring pattern 5
6b is bonded with a wire 59, and the entirety including the wire 59 is epoxy resin 60.
The chip LE having the shape shown in the figure is sealed by sealing.
D is configured.

【００１１】発光素子５１への通電があるときには、半
導体積層膜中のＩｎＧａＮ活性層が発光層となり、この
発光層からの光がサファイア基板５１ａ及びｐ側電極５
３の両方向へ向かう。そして、ｐ側電極５３を光透過し
ない反射型の積層膜としておくことにより、サファイア
基板５１ａの上面からの発光輝度を最大としてこの面を
主光取出し面とすることができる。When the light-emitting element 51 is energized, the InGaN active layer in the semiconductor laminated film becomes a light-emitting layer, and light from this light-emitting layer is transmitted to the sapphire substrate 51 a and the p-side electrode 5.
Go in both directions. By forming the p-side electrode 53 as a reflective laminated film that does not transmit light, this surface can be used as a main light extraction surface by maximizing light emission luminance from the upper surface of the sapphire substrate 51a.

【００１２】[0012]

【発明が解決しようとする課題】ところが、基板５６の
配線パターン５６ａの上にツェナーダイオード５７を搭
載してさらにその上に発光素子５１を載せるアセンブリ
となるので、静電気保護素子を含まない従来のチップＬ
ＥＤに比べると、発光素子５１の上端までの高さ寸法が
大きくなる。特に、ｐ側電極５７ａにボンディングする
ワイヤ５９は、このｐ側電極５７ａの側方に位置してい
る配線パターン５６ｂとの間で上向きに弓なりの形状と
して配線することになるので、このワイヤ５９の上向き
への突き出し長さによっても高さ方向の嵩が大きくなっ
てしまう。However, since a Zener diode 57 is mounted on the wiring pattern 56a of the substrate 56 and the light emitting element 51 is further mounted thereon, a conventional chip which does not include an electrostatic protection element is provided. L
The height dimension up to the upper end of the light emitting element 51 is larger than that of the ED. In particular, the wire 59 to be bonded to the p-side electrode 57a is wired upward in an arcuate shape with the wiring pattern 56b located on the side of the p-side electrode 57a. The bulk in the height direction also increases depending on the length of the upward projection.

【００１３】このように、ツェナーダイオード５７のよ
うな静電気保護素子を備えることで、静電気等の過電流
の印加による発光素子５１の破壊を確実に防止できると
いう新たな機能を活用できる。ところが、その反面で、
複合素子化したことによる基板５６の搭載面から発光素
子５１の上端面までの高さと、ツェナーダイオード５７
にボンディングするワイヤ５９の配線の高さとがどちら
も大きくなる。By providing an electrostatic protection element such as the Zener diode 57, a new function of reliably preventing the light emitting element 51 from being damaged by the application of an overcurrent such as static electricity can be utilized. However, on the other hand,
The height from the mounting surface of the substrate 56 to the upper end surface of the light emitting element 51 due to the composite element, and the Zener diode 57
And the height of the wire of the wire 59 to be bonded to both becomes large.

【００１４】したがって、発光素子５１及びワイヤ５９
を含めてエポキシ樹脂６０によって封止することによっ
て得られるチップＬＥＤの厚さにも制約を受けることに
なり、発光装置の薄型化の大きな障害となる。Therefore, the light emitting element 51 and the wire 59
And the thickness of the chip LED obtained by sealing with the epoxy resin 60 is also restricted, which is a major obstacle to thinning the light emitting device.

【００１５】本発明において解決すべき課題は、静電気
による発光素子の破壊を防止するとともに高さ方向の嵩
を小さくしたコンパクトな半導体発光装置を提供するこ
とにある。It is an object of the present invention to provide a compact semiconductor light emitting device that prevents a light emitting element from being damaged by static electricity and has a reduced height.

【００１６】[0016]

【課題を解決するための手段】本発明は、静電気保護素
子をリードフレームまたは基板等の基材の搭載面に搭載
し、フリップチップ型の半導体発光素子を前記静電気保
護素子の上面にｐ側及びｎ側の電極を逆極性で、マイク
ロバンプ等により電気的に接続した形で搭載し、前記半
導体発光素子の搭載面側と反対側を主光取出し面とした
半導体発光装置において、前記静電気保護素子は、前記
発光素子を搭載する素子搭載面と、この素子搭載面より
も低く段差状に形成した前記基材とワイヤ接合するため
のボンディング面と、前記素子搭載面とボンディング面
までにかけて配線した電極と、前記素子搭載面からボン
ディング面までにかけて拡散形成もしくは素子搭載面の
み拡散形成した拡散領域を含むことを特徴とする。According to the present invention, an electrostatic protection element is mounted on a mounting surface of a base material such as a lead frame or a substrate, and a flip-chip type semiconductor light emitting element is mounted on the p-side and the upper surface of the electrostatic protection element. In the semiconductor light emitting device, the n-side electrode is mounted in a reverse polarity and electrically connected by a microbump or the like, and the side opposite to the mounting surface side of the semiconductor light emitting element is a main light extraction surface. Is an element mounting surface on which the light emitting element is mounted, a bonding surface for wire bonding with the base formed in a stepped lower shape than the element mounting surface, and an electrode wired up to the element mounting surface and the bonding surface. And a diffusion region formed by diffusion from the element mounting surface to the bonding surface or by diffusion only on the element mounting surface.

【００１７】この構成では、ワイヤボンディングするボ
ンディング面が発光素子の搭載面よりも低い位置にある
ので、ワイヤを上に向けて凸の円弧を描くようにボンデ
ィングする場合でもワイヤの最大高さを抑えることがで
きる。In this configuration, since the bonding surface for wire bonding is located at a position lower than the mounting surface of the light emitting element, the maximum height of the wire is suppressed even when bonding the wire upward so as to draw a convex arc. be able to.

【００１８】[0018]

【発明の実施の形態】請求項１に記載の発明は、静電気
保護素子をリードフレームまたは基板等の基材の搭載面
に搭載し、フリップチップ型の半導体発光素子を前記静
電気保護素子の上面にｐ側及びｎ側の電極を逆極性で、
マイクロバンプ等により電気的に接続した形で搭載し、
前記半導体発光素子の搭載面側と反対側を主光取出し面
とした半導体発光装置において、前記静電気保護素子
は、前記発光素子を搭載する素子搭載面と、この素子搭
載面よりも低く段差状に形成した前記基材とワイヤ接合
するためのボンディング面と、前記素子搭載面とボンデ
ィング面までにかけて配線した電極と、前記素子搭載面
からボンディング面までにかけて拡散形成もしくは素子
搭載面のみ、拡散形成した拡散領域を含むものであり、
ワイヤを上に向けて凸の円弧を描くようにボンディング
する場合でもワイヤの最大高さを抑えて嵩を小さくする
という作用を有する。According to the first aspect of the present invention, an electrostatic protection element is mounted on a mounting surface of a base material such as a lead frame or a substrate, and a flip-chip type semiconductor light emitting element is mounted on an upper surface of the electrostatic protection element. The p-side and n-side electrodes are of opposite polarity,
Mounted in a form electrically connected by micro bumps, etc.,
In a semiconductor light emitting device having a main light extraction surface on the side opposite to the mounting surface side of the semiconductor light emitting element, the electrostatic protection element has an element mounting surface on which the light emitting element is mounted, and a step lower than the element mounting surface. A bonding surface for wire bonding to the formed base material, an electrode wired from the element mounting surface to the bonding surface, and a diffusion formed from the element mounting surface to the bonding surface or a diffusion formed only from the element mounting surface. Including the area,
Even when the wire is bonded so as to draw a convex arc with the wire facing upward, there is an effect that the maximum height of the wire is suppressed and the bulk is reduced.

【００１９】請求項２に記載の発明は、前記静電気保護
素子は、Ｓｉを用いたダイオードとしてなる請求項１記
載の半導体発光装置であり、Ｓｉを用いたダイオードを
部材とすることで、電気配線を容易に行えるとともに、
発光素子の静電耐圧が弱い場合においては、発光装置が
静電気保護機能を備えているため、発光装置として静電
耐圧の向上が実現できる。According to a second aspect of the present invention, there is provided the semiconductor light emitting device according to the first aspect, wherein the electrostatic protection element is a diode using Si. Can be easily performed,
When the light-emitting element has a low electrostatic withstand voltage, the light-emitting device has an electrostatic protection function, so that the light-emitting device can have an improved electrostatic withstand voltage.

【００２０】請求項３に記載の発明は、前記発光素子
は、窒化物を含む化合物半導体としてなる請求項１また
は２記載の半導体発光装置であり、特に静電耐圧が低い
窒化化合物半導体を用いた発光素子に対して静電耐圧を
格段に向上させることができ、発光装置としての信頼性
が向上する。According to a third aspect of the present invention, there is provided the semiconductor light emitting device according to the first or second aspect, wherein the light emitting element is a compound semiconductor containing a nitride. The electrostatic breakdown voltage of the light emitting element can be remarkably improved, and the reliability of the light emitting device is improved.

【００２１】請求項４に記載の発明は、前記静電気保護
素子に形成された段差状のボンディング面は、静電気保
護素子のリードフレームまたは基板等への搭載面に対す
る高さを５０〜１５０μｍの範囲としてなる請求項１か
ら３のいずれかに記載の半導体発光装置であり、ボンデ
ィング面の位置を規制することで、ウェーハ製造プロセ
ス並びにダイスボンド工程等で生じる割れ等の対策を図
ることができるという作用を有する。According to a fourth aspect of the present invention, the step-like bonding surface formed on the electrostatic protection element has a height of 50 to 150 μm with respect to a mounting surface of the electrostatic protection element on a lead frame or a substrate. 4. The semiconductor light emitting device according to claim 1, wherein by controlling the position of the bonding surface, it is possible to take measures such as cracks generated in a wafer manufacturing process and a die bonding process. Have.

【００２２】以下に、本発明の実施の形態の具体例を図
面を参照しながら説明する。図１は本発明の一実施の形
態による半導体発光装置であって、チップＬＥＤを例示
する概略縦断面図である。Hereinafter, specific examples of the embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic longitudinal sectional view illustrating a semiconductor light emitting device according to an embodiment of the present invention, which illustrates a chip LED.

【００２３】図において、従来例で示したものと同様に
基板１０の配線パターン１０ａにＡｇペースト１１を介
して静電気保護素子としてのツェナーダイオード６が搭
載され、このツェナーダイオード６の上に発光素子１が
相互の電極を逆極性として電気的に導通接続されて搭載
されている。In the drawing, a zener diode 6 as an electrostatic protection element is mounted on a wiring pattern 10a of a substrate 10 via an Ag paste 11 in the same manner as in the conventional example, and the light emitting element 1 is mounted on the zener diode 6. Are mounted so as to be electrically conductively connected with the electrodes having opposite polarities.

【００２４】発光素子１は、絶縁性の透明なサファイア
基板１ａの表面に、たとえばＧａＮバッファ層，ｎ型Ｇ
ａＮ層，ＩｎＧａＮ活性層，ｐ型ＡｌＧａＮ層及びｐ型
ＧａＮ層を順に積層し、ＩｎＧａＮ活性層を発光層とし
たものである。そして、ｎ型ＧａＮ層の上面にｎ側電極
２が、及びｐ型ＧａＮ層の上面にはｐ側電極３がそれぞ
れ蒸着法によって形成され、更にこれらのｎ側電極２及
びｐ側電極３の上にはそれぞれマイクロバンプ４，５を
形成している。The light emitting element 1 is provided on a surface of an insulating transparent sapphire substrate 1a, for example, with a GaN buffer layer, an n-type G
An aN layer, an InGaN active layer, a p-type AlGaN layer, and a p-type GaN layer are sequentially stacked, and the InGaN active layer is used as a light emitting layer. Then, an n-side electrode 2 is formed on the upper surface of the n-type GaN layer, and a p-side electrode 3 is formed on the upper surface of the p-type GaN layer by a vapor deposition method. Have micro bumps 4 and 5, respectively.

【００２５】ツェナーダイオード６は、ｎ型シリコン基
板６ｃを利用したものであり、その底面にはｎ電極６ｃ
−１を形成するとともに、上面にはｐ側及びｎ側の電極
６ａ，６ｂをそれぞれ形成している。また、ｎ型シリコ
ン基板６ｃは、図示のように右端部側の上面の肉を盗ん
だ断面形状の段差状として形成され、左側の高い部分を
発光素子１の搭載面としている。The Zener diode 6 utilizes an n-type silicon substrate 6c, and has an n-electrode 6c
In addition to forming −1, p-side and n-side electrodes 6a and 6b are formed on the upper surface, respectively. Further, the n-type silicon substrate 6c is formed as a step having a cross-sectional shape in which the upper surface on the right end portion is stolen, as shown in the figure, and a high portion on the left side is a mounting surface of the light emitting element 1.

【００２６】ｎ型シリコン基板６ｃには、発光素子１の
素子搭載面からその右側方の段差部及びこの段差部に連
なって搭載面よりも低くしたボンディング面までにかけ
て、ｐ型半導体領域６ｄを拡散形成する。このｐ型半導
体領域６ｄは、製造工程において酸化膜等で被膜した後
に拡散窓をエッチング等によって開け、この拡散窓から
ｐ型不純物イオンを注入することで形成されるものであ
る。そして、このｐ型半導体領域６ｄに対応してｐ側電
極６ａが接合されるとともに、素子搭載面側のｎ型半導
体領域すなわちｎ型シリコン基板６ｃに接触してｎ側電
極６ｂが形成されている。また、これらのｐ側及びｎ側
の電極６ａ，６ｂ下には絶縁膜６ｅを設けている。In the n-type silicon substrate 6c, the p-type semiconductor region 6d is diffused from the element mounting surface of the light emitting element 1 to the step portion on the right side thereof and the bonding surface connected to the step portion and lower than the mounting surface. Form. The p-type semiconductor region 6d is formed by coating the substrate with an oxide film or the like in a manufacturing process, opening a diffusion window by etching or the like, and implanting p-type impurity ions from the diffusion window. The p-side electrode 6a is joined to the p-type semiconductor region 6d, and the n-side electrode 6b is formed in contact with the n-type semiconductor region on the element mounting surface side, that is, the n-type silicon substrate 6c. . An insulating film 6e is provided under the p-side and n-side electrodes 6a and 6b.

【００２７】発光素子１は、ｎ側及びｐ側の電極２，３
に設けたマイクロバンプ４，５をそれぞれｐ側電極６ａ
及びｎ側電極６ｂに載せて搭載接合される。この場合、
発光素子１はツェナーダイオード６のほぼ左側半分を占
める領域の素子搭載面に被さるように位置させる。そし
て、配線パターン１０ｂとの間のボンディング用のワイ
ヤ１２は、段差部分の低い側まで延びている部分のｐ側
電極６ａにボンディングすることによって、ツェナーダ
イオード６を配線パターン１０ｂ側と導通させる。The light emitting element 1 has n-side and p-side electrodes 2 and 3
Micro bumps 4 and 5 provided on the p-side electrode 6a, respectively.
And mounted and joined on the n-side electrode 6b. in this case,
The light emitting element 1 is positioned so as to cover the element mounting surface in a region occupying substantially the left half of the Zener diode 6. The bonding wire 12 between the wiring pattern 10b and the p-side electrode 6a extending to the lower side of the step portion makes the Zener diode 6 conductive with the wiring pattern 10b.

【００２８】このようなアセンブリにより、発光素子１
とツェナーダイオード６のそれぞれのｐ側及びｎ側の電
極２，３，６ａ，６ｂが逆極性として接続され、基板１
０側からの高電圧が印加されないようにして発光素子１
の破壊を防止することができる。そして、基板１０の上
面から発光素子１及びワイヤ１２を含めて全体をエポキ
シ樹脂１３によって封止することで、図１に示すチップ
ＬＥＤが得られる。With such an assembly, the light emitting device 1
And the p-side and n-side electrodes 2, 3, 6a, and 6b of the Zener diode 6 are connected with opposite polarities, and the substrate 1
The light emitting element 1 is set so that no high voltage is applied from the 0 side.
Can be prevented from being destroyed. Then, the entire chip including the light emitting element 1 and the wire 12 is sealed with the epoxy resin 13 from the upper surface of the substrate 10, whereby the chip LED shown in FIG. 1 is obtained.

【００２９】以上の構成において、発光素子１への通電
があるときには、半導体積層膜中のＩｎＧａＮ活性層が
発光層となり、この発光層からの光がサファイア基板１
ａ及びｐ側電極３の両方向へ向かう。そして、ｐ側電極
３を光透過しない反射型の積層膜としておくことによ
り、サファイア基板１ａの上面からの発光輝度を最大と
してこの面を主光取出し面とすることができる。In the above configuration, when the light emitting element 1 is energized, the InGaN active layer in the semiconductor laminated film becomes a light emitting layer, and light from this light emitting layer is transmitted to the sapphire substrate 1.
It proceeds in both directions of the a and p-side electrodes 3. By forming the p-side electrode 3 as a reflection type laminated film that does not transmit light, this surface can be used as a main light extraction surface with maximum light emission luminance from the upper surface of the sapphire substrate 1a.

【００３０】本発明においては、ツェナーダイオード６
のｎ型シリコン基板６ｃは、配線パターン１０ｂとの間
のワイヤ１２のボンディング面を段差状にしてツェナー
ダイオード６の素子搭載面よりも低くしているので、ｐ
側電極６ａに接合するワイヤ１２のボンディングポイン
トも低くなる。In the present invention, the Zener diode 6
Since the bonding surface of the wire 12 between the n-type silicon substrate 6c and the wiring pattern 10b is stepped and lower than the element mounting surface of the Zener diode 6,
The bonding point of the wire 12 bonded to the side electrode 6a also becomes lower.

【００３１】すなわち、図５に示した従来構造では、発
光素子５１を搭載する面と同じ高さのｐ側電極５７ａに
ワイヤ５９をボンディングしているので、ワイヤ５９が
上に凸の向きに張られて基板５６に接続されるときに
は、ワイヤ５９の弓なり状の弧も高くなる。これに対
し、図１に示すように、ボンディング面に被さっている
ｐ側電極６ａはツェナーダイオード６の素子搭載面より
も低いので、このｐ側電極６ａにボンディングするワイ
ヤ１２の最大高さは小さく抑えられる。That is, in the conventional structure shown in FIG. 5, since the wire 59 is bonded to the p-side electrode 57a having the same height as the surface on which the light emitting element 51 is mounted, the wire 59 is stretched upward. When the wire 59 is connected to the substrate 56, the arc of the wire 59 becomes higher. On the other hand, as shown in FIG. 1, since the p-side electrode 6a covering the bonding surface is lower than the element mounting surface of the Zener diode 6, the maximum height of the wire 12 bonded to the p-side electrode 6a is small. Can be suppressed.

【００３２】したがって、ツェナーダイオード６の上に
発光素子１を搭載し複合素子化してても、ワイヤ１２の
弓なりの弧の上端を発光素子１の上端面よりも低くする
ことができる。これにより、図５の従来構造に比べる
と、基板１０からのワイヤ１２の高さ方向の嵩を格段に
小さくできるとともに、エポキシ樹脂１３の封止高さも
小さくなるので、発光装置の小型化が可能となる。Therefore, even when the light emitting element 1 is mounted on the Zener diode 6 to form a composite element, the upper end of the arc of the wire 12 can be made lower than the upper end surface of the light emitting element 1. As a result, compared to the conventional structure of FIG. 5, the bulk of the wire 12 from the substrate 10 in the height direction can be significantly reduced, and the sealing height of the epoxy resin 13 is also reduced, so that the light emitting device can be downsized. Becomes

【００３３】また、ｐ側電極６ａのうちワイヤ１２をボ
ンディングする部分を接合している段差のボンディング
面は、ツェナーダイオード６の底面から５０〜１５０μ
ｍ程度の高さとなるように形成することが好ましい。こ
のような高さに相当する肉厚であれば、ｎ型シリコン基
板６ｃの素材からボンディング面を切除するウェーハ製
造プロセスにおいても、ウェーハの割れやクラックの発
生を防止することができ、製品の歩留りに影響すること
もない。The bonding surface of the step connecting the portion of the p-side electrode 6a to which the wire 12 is bonded is 50 to 150 μm from the bottom of the Zener diode 6.
It is preferable that the height is about m. With a thickness corresponding to such a height, cracks and cracks in the wafer can be prevented from occurring even in a wafer manufacturing process in which the bonding surface is cut from the material of the n-type silicon substrate 6c, and the product yield Does not affect

【００３４】図２はｐ型半導体領域を素子搭載面に含ま
れる部分にのみ拡散形成した例である。なお、図１で示
したものと同じ部材については共通の符号で指示し、そ
の詳細な説明は省略する。FIG. 2 shows an example in which a p-type semiconductor region is formed by diffusion only in a portion included in the element mounting surface. The same members as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

【００３５】ツェナーダイオード６のｎ型シリコン基板
６ｃは図１のものと同様の外郭形状であり、ｐ型半導体
領域６ｄは発光素子１を搭載したときにそのｎ側電極２
と対向する部分に拡散形成されている。そして、ｐ側電
極６ａはこのｐ型半導体領域６ｄの上面に被さる位置か
ら段差部及びボンディング面までにかけて接合形成さ
れ、絶縁膜６ｅはボンディング面からｐ型半導体領域６
ｄの一部を被覆して形成されている。The n-type silicon substrate 6c of the Zener diode 6 has the same outer shape as that of FIG. 1, and the p-type semiconductor region 6d has the n-side electrode 2 when the light emitting element 1 is mounted.
Is diffused at a portion opposed to. Then, the p-side electrode 6a is formed by bonding from a position covering the upper surface of the p-type semiconductor region 6d to the step portion and the bonding surface, and the insulating film 6e is formed from the bonding surface to the p-type semiconductor region 6d.
It is formed by covering a part of d.

【００３６】ツェナーダイオード６は、図１の例と同様
に、基板１０の配線パターン１０ａの上にＡｇペースト
によって固定され、他方の配線パターン１０ｂとｐ側電
極６ａとの間にワイヤ１２をボンディングしたものであ
る。そして、この例においても、ワイヤ１２をｐ側電極
６ａにボンディングする位置は発光素子１の搭載面より
も低いので、図１の例と同様にワイヤ１２の高さ方向の
嵩を小さくすることがきる。The zener diode 6 is fixed on the wiring pattern 10a of the substrate 10 with an Ag paste, and the wire 12 is bonded between the other wiring pattern 10b and the p-side electrode 6a, as in the example of FIG. Things. Also in this example, since the position where the wire 12 is bonded to the p-side electrode 6a is lower than the mounting surface of the light emitting element 1, the height of the wire 12 in the height direction can be reduced as in the example of FIG. Wear.

【００３７】以上の例では、ｎ型シリコン基板のツェナ
ーダイオードとしているが、これに代えてｐ型シリコン
基板とすることもでき、ツェナーダイオード及びこれに
搭載した発光素子の要部を図３及び図４に示す。In the above example, a Zener diode of an n-type silicon substrate is used. However, a p-type silicon substrate may be used instead. A main part of the Zener diode and the light emitting element mounted thereon is shown in FIGS. It is shown in FIG.

【００３８】図３において、底面にｐ電極７ａ−１を形
成したｐ型シリコン基板７ａを利用したツェナーダイオ
ード７は、左端側の上面の肉を盗んだ段差状に形成さ
れ、右側の高い部分を発光素子１の搭載面とするととも
に左側の低い部分をワイヤ１２のボンディング面とした
ものである。そして、素子搭載面の左端側からボンディ
ング面までにかけてｎ型半導体領域７ｂをｎ型不純物イ
オンの注入によって形成し、このｎ型半導体領域７ｂに
ｎ側電極７ｃを接合するとともに、素子搭載面側にはｐ
型半導体領域すなわちｐ型シリコン基板７ａに接触する
ｐ側電極７ｄを接合している。また、ｐ型シリコン基板
７ａの上面には、絶縁膜７ｅが所定の領域に形成されて
いる。In FIG. 3, a Zener diode 7 using a p-type silicon substrate 7a having a p-electrode 7a-1 formed on the bottom surface is formed in a stepped shape stealing the upper surface on the left end side, and a high portion on the right side is formed. The lower part on the left side is used as the bonding surface of the wire 12 as well as the mounting surface of the light emitting element 1. Then, an n-type semiconductor region 7b is formed by implanting n-type impurity ions from the left end side of the element mounting surface to the bonding surface, and an n-side electrode 7c is joined to the n-type semiconductor region 7b and the n-type semiconductor region 7b is formed on the element mounting surface side. Is p
The p-side electrode 7d that contacts the type semiconductor region, that is, the p-type silicon substrate 7a, is joined. An insulating film 7e is formed in a predetermined region on the upper surface of the p-type silicon substrate 7a.

【００３９】このようにｐ型シリコン基板７ａを利用す
る場合であっても、ワイヤ１２のボンディング面を発光
素子１の搭載面よりも低くすることによって、ワイヤ１
２の高さ方向の嵩を小さくするアセンブリが可能とな
る。As described above, even when the p-type silicon substrate 7a is used, by setting the bonding surface of the wire 12 lower than the mounting surface of the light emitting element 1, the wire 1
2 enables an assembly to reduce the bulk in the height direction.

【００４０】図４は、発光素子１の搭載面に含まれる位
置であって発光素子１のｐ側電極３に対応する部分にの
みｎ型半導体領域７ｂを形成した例である。これは、ｎ
型シリコン基板６ｃを用いた図２の例で説明したものと
同様の構成であり、ワイヤ１２のボンディング面が素子
搭載面よりも低くできることは図３の例と同じであり、
したがってワイヤ１２の高さ方向の嵩を小さくすること
ができる。FIG. 4 shows an example in which the n-type semiconductor region 7b is formed only at a position included in the mounting surface of the light emitting element 1 and corresponding to the p-side electrode 3 of the light emitting element 1. This is n
The configuration is the same as that described in the example of FIG. 2 using the die-shaped silicon substrate 6c, and the bonding surface of the wire 12 can be lower than the element mounting surface, as in the example of FIG.
Therefore, the bulk of the wire 12 in the height direction can be reduced.

【００４１】[0041]

【発明の効果】請求項１の発明では、静電気保護素子に
は、ワイヤボンディングするボンディング面を発光素子
の搭載面よりも低い位置に形成してｐ型またはｎ型の半
導体領域により発光素子とボンディング部側とを導通さ
せるので、ボンディング面に接続するワイヤの高さ方向
の突き出しを抑えることができ、発光装置の小型及び薄
型化が可能となる。According to the first aspect of the present invention, the bonding surface for wire bonding is formed at a position lower than the mounting surface of the light emitting element in the electrostatic protection element, and the electrostatic protection element is bonded to the light emitting element by a p-type or n-type semiconductor region. Since the electrical connection with the unit side is made, the protrusion of the wire connected to the bonding surface in the height direction can be suppressed, and the light emitting device can be reduced in size and thickness.

【００４２】請求項２の発明では、Ｓｉを用いたダイオ
ードを静電保護素子の部材とすることで、発光素子の静
電耐圧が弱くても、静電気保護機能によって発光装置の
静電耐圧を向上させることができ、耐久性が向上する。According to the second aspect of the present invention, by using a diode using Si as a member of the electrostatic protection element, the electrostatic protection function of the light emitting device can be improved even if the light emitting element has a low electrostatic withstand voltage. And the durability is improved.

【００４３】請求項３の発明では、特に静電耐圧が低い
窒化化合物半導体を用いた発光素子に対して静電耐圧を
格段に向上させることができ、発光装置としての信頼性
が更に向上する。According to the third aspect of the invention, the electrostatic breakdown voltage of a light emitting element using a nitride compound semiconductor having a particularly low electrostatic breakdown voltage can be remarkably improved, and the reliability as a light emitting device is further improved.

【００４４】請求項４の発明では、ボンディング面の高
さを規定することによって、ウェーハ製造プロセス及び
ダイスボンド工程での割れの発生を抑えることができ、
歩留りの向上及び割れやクラックによる特性劣化を防止
できるので、発光装置としての信頼性が更に向上する。According to the fourth aspect of the invention, by defining the height of the bonding surface, it is possible to suppress the occurrence of cracks in the wafer manufacturing process and the die bonding process.
Since the yield can be improved and the characteristic deterioration due to cracks and cracks can be prevented, the reliability of the light emitting device can be further improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態によるフリップチップ型
の半導体発光素子を備えたチップＬＥＤの概略縦断面図FIG. 1 is a schematic longitudinal sectional view of a chip LED having a flip-chip type semiconductor light emitting device according to an embodiment of the present invention.

【図２】ｐ型半導体領域を発光素子の搭載面のみに拡散
形成した例の発光装置の要部を示す拡大図FIG. 2 is an enlarged view showing a main part of a light emitting device in which a p-type semiconductor region is formed only by diffusion on a light emitting element mounting surface;

【図３】ｐ型シリコン基板を用いた場合の発光装置の要
部を示す拡大図FIG. 3 is an enlarged view showing a main part of a light emitting device using a p-type silicon substrate.

【図４】ｐ型シリコン基板を用いる例であってｎ型半導
体領域を発光素子の搭載面に含まれる位置に設けた発光
装置の要部を示す拡大図FIG. 4 is an enlarged view showing a main part of a light-emitting device in which an n-type semiconductor region is provided at a position included in a mounting surface of a light-emitting element, using a p-type silicon substrate.

【図５】従来の静電気保護素子を備えたチップＬＥＤの
概略図FIG. 5 is a schematic view of a conventional chip LED having an electrostatic protection element.

【符号の説明】[Explanation of symbols]

１ 発光素子 １ａ サファイア基板 ２ ｎ側電極 ３ ｐ側電極 ４ マイクロバンプ ５ マイクロバンプ ６ ツェナーダイオード ６ａ ｐ側電極 ６ｂ ｎ側電極 ６ｃ ｎ型シリコン基板 ６ｃ−１ ｎ電極 ６ｄ ｐ型半導体領域 ６ｅ 絶縁膜 ７ ツェナーダイオード ７ａ ｐ型シリコン基板 ７ａ−１ ｐ電極 ７ｂ ｎ型半導体領域 ７ｃ ｎ側電極 ７ｄ ｐ側電極 ７ｅ 絶縁膜 １０ 基板 １０ａ，１０ｂ 配線パターン １１ Ａｇペースト １２ ワイヤ １３ エポキシ樹脂 ５１ 発光素子 ５１ａ サファイア基板 ５２ ｎ側電極 ５３ ｐ側電極 ５４ マイクロバンプ ５５ マイクロバンプ ５６ 基板 ５７ ツェナ−ダイオ−ド ５７ａ ｐ側電極 ５７ｂ ｎ側電極 ５７ｃ ｎ型シリコン基板 ５７ｄ ｎ電極 ５７ｅ 絶縁膜 ５７ｆ ｐ型半導体領域 ５８ Ａｇペースト ５９ ワイヤ ６０ エポキシ樹脂 Reference Signs List 1 light-emitting element 1a sapphire substrate 2 n-side electrode 3 p-side electrode 4 microbump 5 microbump 6 Zener diode 6a p-side electrode 6b n-side electrode 6c n-type silicon substrate 6c-1 n-electrode 6d p-type semiconductor region 6e insulating film 7 Zener diode 7a p-type silicon substrate 7a-1 p-electrode 7b n-type semiconductor region 7c n-side electrode 7d p-side electrode 7e insulating film 10 substrate 10a, 10b wiring pattern 11 Ag paste 12 wire 13 epoxy resin 51 light emitting element 51a sapphire substrate 52 n-side electrode 53 p-side electrode 54 micro-bump 55 micro-bump 56 substrate 57 zener diode 57a p-side electrode 57b n-side electrode 57c n-type silicon substrate 57d n-electrode 57e insulating film 57f p-type semiconductor region 58 Ag paste 59 wire 6 0 Epoxy resin

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 静電気保護素子をリードフレームまたは
基板等の基材の搭載面に搭載し、フリップチップ型の半
導体発光素子を前記静電気保護素子の上面にｐ側及びｎ
側の電極を逆極性で、マイクロバンプ等により電気的に
接続した形で搭載し、前記半導体発光素子の搭載面側と
反対側を主光取出し面とした半導体発光装置において、
前記静電気保護素子は、前記発光素子を搭載する素子搭
載面と、この素子搭載面よりも低く段差状に形成した前
記基材とワイヤ接合するためのボンディング面と、前記
素子搭載面とボンディング面までにかけて配線した電極
と、前記素子搭載面からボンディング面までにかけて拡
散形成もしくは素子搭載面のみ拡散形成した拡散領域を
含む半導体発光装置。An electrostatic protection device is mounted on a mounting surface of a base material such as a lead frame or a substrate, and a flip-chip type semiconductor light emitting device is mounted on an upper surface of the electrostatic protection device on a p-side and an n-side.
In the semiconductor light emitting device, the electrodes on the opposite side are mounted in a form electrically connected by micro bumps or the like, and the side opposite to the mounting surface side of the semiconductor light emitting element has a main light extraction surface.
The electrostatic protection element has an element mounting surface on which the light emitting element is mounted, a bonding surface for wire bonding to the base material formed in a stepped shape lower than the element mounting surface, and a bonding surface between the element mounting surface and the bonding surface. A semiconductor light emitting device comprising: an electrode wired over the diffusion region; and a diffusion region formed by diffusion from the element mounting surface to the bonding surface or by diffusion only on the element mounting surface. 【請求項２】 前記静電気保護素子は、Ｓｉを用いたダ
イオードとしてなる請求項１記載の半導体発光装置。2. The semiconductor light emitting device according to claim 1, wherein said electrostatic protection element is a diode using Si. 【請求項３】 前記発光素子は、窒化物を含む化合物半
導体としてなる請求項１または２記載の半導体発光装
置。3. The semiconductor light emitting device according to claim 1, wherein the light emitting element is a compound semiconductor containing a nitride. 【請求項４】 前記静電気保護素子に形成された段差状
のボンディング面は、静電気保護素子のリードフレーム
または基板等への搭載面に対する高さを５０〜１５０μ
ｍの範囲としてなる請求項１から３のいずれかに記載の
半導体発光装置。4. The step-like bonding surface formed on the electrostatic protection element has a height of 50 to 150 μm with respect to a mounting surface of the electrostatic protection element on a lead frame or a substrate.
The semiconductor light emitting device according to claim 1, wherein the range is m.
JP1247698A 1998-01-26 1998-01-26 Semiconductor light-emitting device Pending JPH11214747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1247698A JPH11214747A (en) 1998-01-26 1998-01-26 Semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1247698A JPH11214747A (en) 1998-01-26 1998-01-26 Semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JPH11214747A true JPH11214747A (en) 1999-08-06

Family

ID=11806444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1247698A Pending JPH11214747A (en) 1998-01-26 1998-01-26 Semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JPH11214747A (en)

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US8405304B2 (en) 2006-12-26 2013-03-26 Seoul Semiconductor Co., Ltd. Light emtting device
JP2009059745A (en) * 2007-08-30 2009-03-19 Kyocera Corp Light emitting device
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