JP2002057349A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small semiconductor device having a level-down circuit that hardly causes malfunction in operation. SOLUTION: In a high-voltage breakdown IC used for control drive in a power device and the like, an anti-breakdown structured part 86 for separating an upper arm reference circuit 82 and a grounding reference circuit 81 has a double-relief structure. In the anti-breakdown structured part 86, an n+ region 90 as a cathode is formed at a p-region 85, under a thermal oxide film LOCO on the side end of the upper arm reference circuit 8, and a p+ region as an anode is formed at the p-region 85 on the side of the ground reference circuit 81 to form high-voltage breakdown diode. In this case the high-voltage breakdown diode is not formed in the region of the round reference circuit 81, so that the chip size is reduced, and malfunctions caused by a variation in potential of the upper reference circuit 82 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a high breakdown voltage diode structure used for a high breakdown voltage IC for controlling and driving a power device.

[0002]

2. Description of the Related Art As a device for controlling and driving a three-phase AC motor, an inverter device for converting DC to three-phase AC is known. FIG. 4 shows an example of this power converter.

FIG. 4 is a diagram showing a configuration example of an inverter device. This inverter device converts a DC voltage applied to terminals P and N into a three-phase AC and supplies it to a three-phase AC motor 10, and performs a switching operation using a ground potential or a low potential close thereto as a reference potential. Lower arm reference circuit or ground reference circuit 20 and three-phase AC motor 1
At the terminals U, V, and W of 0, an upper arm reference for performing a switching operation using a fluctuating potential corresponding to the DC intermediate potential of the inverter device and fluctuating between a low potential and a high potential in accordance with the switching operation as a reference potential. And a circuit 30.

The ground reference circuit 20 is, for example, an IGB
Semiconductor switches 21 to 23 which are T (Insulated Gate Bipolar Transistor) and FWD (Free Wheel Diode)
24 to 26, and drive circuits 27 to 29.

The upper arm reference circuit 30 is also, for example, an IGB
T, semiconductor switches 31 to 33, and FWDs 34 to 3
6 and drive circuits 37 to 39. The drive circuits 27 to 29 and 37 to 39 of the ground reference circuit 20 and the upper arm reference circuit 30 are interface circuits (I /
F) is connected to the control unit 50 via 40.

The control unit 50 includes, for example, a CPU (Central
Processing Unit), ROM (ReadOnly Memory), RA
It is composed of M (Random Access Memory) and the like.
The control unit 50 controls the driving circuits 27 to 29 and 37 to 39 via the interface circuit 40 to perform switching operations of the semiconductor switches 21 to 23 and 31 to 33, and to convert the three-phase AC motor 10 from the DC voltage. To generate a three-phase alternating current to be supplied to the. When an alarm signal indicating the occurrence of a problem such as a power supply voltage abnormality, an overcurrent state, or an overheat state is sent from each of the drive circuits 27 to 29 and 37 to 39, the control unit 50 also controls the ground reference circuit 20 and the Control is performed to stop the operation of the upper arm reference circuit 30.

The interface circuit 40 mediates information between the ground reference circuit 20 and the control unit 50, and also has an upper arm reference circuit 30 and a control unit 5 having different reference potentials.
It is configured to mediate information even with 0.

FIG. 5 is a diagram showing a detailed configuration of a drive circuit for one phase and its peripheral portion. In this figure, a drive circuit 27 of the ground reference circuit 20 and a drive circuit 37 of the upper arm reference circuit 30 are shown as drive circuits. The drive circuit 27 of the ground reference circuit 20 includes a power monitor 27
a, an upper-arm reference circuit 3 comprising an abnormality detector 27b, an interface 27c, and a driver 27d.
Similarly, the 0 drive circuit 37 is also configured by a power supply monitoring unit 37a, an abnormality detection unit 37b, an interface unit 37c, and a driver 37d.

First, the driving circuit 2 of the ground reference circuit 20
7, the power supply monitoring unit 27a determines whether or not the power supply voltage supplied to the drive circuit 27 is within a normal range, and when it is determined that the power supply voltage is abnormal, the control unit 27a via the interface unit 27c and the interface circuit 40. Notify 50.

The abnormality detecting section 27b is provided with the semiconductor switch 21.
And the temperature of the semiconductor switch 21 are monitored. When an excessive current flows through the semiconductor switch 21 or when the semiconductor switch 21 is overheated, the control unit 50 is controlled via the interface unit 27c and the interface circuit 40. Notify to

The interface unit 27c exchanges an alarm signal and a control signal for driving the semiconductor switch 21 between the drive circuit 27 and the control unit 50 via the interface circuit 40.

The driver 27d includes an interface unit 27
The semiconductor switch 21 is driven in accordance with a control signal supplied from the control unit 50 via the switch c. Upper arm reference circuit 30
In the driving circuit 37, the power supply monitoring unit 37a determines whether or not the power supply voltage supplied to the driving circuit 37 is within a normal range.
7c and the control unit 50 via the interface circuit 40.
Notify to

The abnormality detecting section 37b includes the semiconductor switch 31
And the temperature of the semiconductor switch 31 are monitored. When an excessive current flows through the semiconductor switch 31 or when the semiconductor switch 31 is overheated, the control unit 50 is controlled via the interface unit 37c and the interface circuit 40. Notify to

The interface section 37c exchanges an alarm signal and a control signal for driving the semiconductor switch 31 between the drive circuit 37 and the control section 50 via the interface circuit 40. In this case, the drive circuit 37 having a non-constant reference potential and the control unit 5 using the ground level as the reference potential
The physical characteristics are matched in cooperation with the interface circuit 40 so that information can be transmitted and received between 0 and 0.

Since the reference potential of the ground reference circuit 20 is at the ground level, only one power supply monitor is required in the drive circuits 27 to 29. In this example, the drive circuit 2
7 is provided with a power supply monitoring unit 27a. On the other hand, the drive circuits 37 to 39 of the upper arm reference circuit 30 have different reference potentials.
The power supplied to the power supply 39 must be individually detected, and therefore, the other drive circuits 38 and 39 also have the same power supply monitoring unit.

FIG. 6 is a circuit diagram showing details of a portion for transmitting an alarm signal from the upper arm reference circuit. The interface unit 37c provided in the drive circuit 37 of the upper arm reference circuit 30 is, for example, an N-channel MOS type FET (Meta
l-Oxide Semiconductor Field Effect Transistor), a transistor 37ca, an inverter 37cb,
It comprises a power supply 37cc and a flip-flop 37cd. Further, the interface circuit 40 includes the power supply 4
0a, an inverter 40b, and a resistor 40c. Further, the interface unit 37c and the interface circuit 40 are connected by a diode 60.

In the interface section 37c, the power supply 3
The positive side of 7cc is connected to the inverter 37cb,
The negative side is the inverter 37cb, the transistor 37c
a and the reference potential portion (ground pattern) of the drive circuit 37. Flip-flop 3
An input terminal S of 7cd is connected to outputs of the power monitoring unit 37a and the abnormality detection unit 37b so as to receive an alarm signal, and an output terminal Q is connected to an input of the inverter 37cb. The output of the inverter 37cb is connected to the gate of the transistor 37ca.

The drain of the transistor 37ca is connected to the cathode of the diode 60, and the anode of the diode 60 is connected to the inverter 40b of the interface circuit 40.
And one end of the resistor 40c. The plus side of the power supply 40a is connected to the other end of the inverter 40b and the resistor 40c, and the minus side is connected to the inverter 40b and the reference potential portion (ground pattern) of the interface circuit 40.

In the above configuration, the transistor 37c
When the potential of the drain a is higher than the potential on the input side of the inverter 40b, the diode 60 is reverse-biased and is in a cutoff state. On the other hand, when the potential of the drain of the transistor 37ca is lower than the potential of the input side of the inverter 40b, the diode 60 becomes forward-biased and becomes conductive.

Here, it is assumed that the power supply monitoring unit 37a or the abnormality detection unit 37b detects an abnormality in the power supply voltage or an overcurrent state or an overheated state of the semiconductor switch 31 and issues an alarm signal. This alarm signal is output from the flip-flop 3
7cd latched and stored. Then, the output signal of the flip-flop 37cd becomes the inverter 37cb.
The transistor 37ca is driven through the switch to turn it on.

At this time, when the diode 60 is in the forward bias state or transitions from the reverse bias to the forward bias state, the inverter 40b which has been in the "H" state
Is in an "L" state, the output of the inverter 40b is in an "H" state, and an alarm signal is transmitted to the control unit 50. When receiving the alarm signal, the control unit 50 outputs a control signal to all the driving circuits 27 to 29 and 37 to 39 to turn off the semiconductor switches 21 to 23 and 31 to 33.

The structure for connecting the upper arm reference circuit 30 and the interface circuit 40 using this diode is as follows.
It was proposed by the present applicant (Japanese Patent Application No. 11-3).
03248), when the potential of the drain of the transistor 37ca is higher than the potential of the input side of the inverter 40b and the diode 60 is in a reverse bias state, all the potential difference between the drain and the input side of the inverter 40b is applied to the diode 60. Therefore, as the signal transmitting transistor 37ca, an N-channel MOS type FET having a low withstand voltage is used.
This has the advantage that it can be formed in a small size without having to have a high breakdown voltage.

In the inverter device as described above, the semiconductor switches 21 to 23 and 31 to 33 and the FWDs 24 to 2
The IPM (Intelligent Power Module) is a combination of the power section composed of 6, 34 to 36 and intelligent functions such as drive function, power supply voltage detection / protection, overcurrent detection / protection, and overheat detection / protection. Power modules are being constructed.

In recent years, in order to reduce the size, function, cost and current consumption of the IPM, a high-voltage integrated circuit (HVIC: High Voltage Integrated Circuit) has been developed.
t) is being used as an IC having a driver function for upper and lower arms, various protection functions, an interface function, and the like.

The high withstand voltage IC is 600 V or 1 V, which is the withstand voltage of the IGBT used as a semiconductor switch.
IC with structure that can control high voltage such as 200V
And a ground reference circuit 2 based on the ground potential.
The configuration is such that the portion of 0 and the portion of the upper arm reference circuit 30 based on the potential that fluctuates according to the switching operation coexist.

In general, a high withstand voltage IC has a structure in which a withstand voltage structure is formed to separate the potentials of the upper arm reference circuit and the ground reference circuit, and the upper arm reference circuit is surrounded by the withstand voltage structure. . FIG. 7 shows a schematic cross-sectional view of a double RESURF structure as an example of the pressure-resistant structure.

FIG. 7 is a schematic sectional view of a pressure-resistant structure using a double RESURF structure. This double RESURF structure is
An N-region 72 is formed on the surface of the substrate 71, and a P-region 73 is further formed on the surface. The structure is such that the reverse bias of the PN junction is used to separate the potentials of the upper arm reference circuit and the ground reference circuit. is there. In this figure, GND is a reference potential of the ground reference circuit, LOCOS is a thermal oxide film, VDD
P indicates a power supply of the upper arm reference circuit, and GNDP indicates a reference potential of the upper arm reference circuit.

The high withstand voltage IC has a high withstand voltage level shifter for transmitting an alarm signal between the ground reference circuit and the upper arm reference circuit. The level down function of the high withstand voltage level shifter will be described.

The level down circuit is a circuit for converting an alarm signal of the upper arm reference circuit and the like into a signal of the ground reference circuit. This level down circuit includes a high-breakdown-voltage P-channel MO as disclosed in, for example, JP-A-9-55498 and JP-A-10-27853.
A structure using an S-type FET is generally used. FIG. 8 shows a state in which this level down circuit is viewed from above the high breakdown voltage IC.

FIG. 8 shows a high breakdown voltage P-channel MOS FET.
FIG. 2 is a schematic diagram of a level down circuit of a high breakdown voltage IC using the same as viewed from above. In this figure, an upper arm reference circuit region 75 and a ground reference circuit region 76 are separated by a withstand voltage structure 77, and a high withstand voltage P-channel MOS FET 7 of a level down circuit is provided in the upper arm reference circuit region 75.
8 are formed. This example shows a case where two P-channel MOS FETs 78 are formed in the upper arm reference circuit region 75. P-channel MOS type FET7
The drain 8 constitutes the output 79 of the level down circuit.

Here, in the case where the above-mentioned diode for connecting the upper arm reference circuit 75 and the ground reference circuit 76 is to be formed in the above-described level down circuit instead of the P-channel MOS type FET having a high withstand voltage, Are formed in the ground reference circuit area 76 outside the upper arm reference circuit area 75. FIG. 9 shows an example of forming this diode.

FIG. 9 shows a high breakdown voltage I using a high breakdown voltage diode.
It is the schematic which looked at the level-down circuit of C from the upper surface. The high withstand voltage diode 80 connecting the upper arm reference circuit 75 and the ground reference circuit 76 is provided in the upper arm reference circuit area 75.
The cathode 80a and the anode 80b are formed separately from each other in the ground reference circuit region 76 outside by the breakdown voltage structure 80c.

[0033]

However, in the conventional high-withstand-voltage IC, a high-withstand-voltage P-channel MOS type FE is used.
Since the drain of T becomes the output of the ground reference signal,
Further, it is necessary to form the pressure-resistant structure 78a. Alternatively, if a high breakdown voltage diode is formed in the ground reference circuit region, an additional area is required for element formation, and the high breakdown voltage IC becomes large.

FIGS. 13 and 14 described in Japanese Patent Application Laid-Open No. 9-55498 and FIG. 10 described in Japanese Patent Application Laid-Open No. 10-27853 show a high breakdown voltage P-channel MOS type FE.
Although T is formed at the position of the breakdown voltage structure for separating the upper arm reference circuit, the breakdown voltage structure of the high breakdown voltage P-channel MOSFET is shared with the breakdown voltage structure for separating the upper arm reference circuit. Only in this case, the area of the high breakdown voltage IC also increases.

Further, the level down circuits disclosed in JP-A-9-55498 and JP-A-10-27853 perform signal transmission even when the potential of the upper arm reference circuit fluctuates. There is a possibility that noise generated due to a temporary voltage fluctuation may be erroneously detected as an alarm signal, causing a malfunction.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor device having a level down circuit which is smaller in size and in which a malfunction does not easily occur.

[0037]

According to the present invention, in order to solve the above problems, a first region of a first conductivity type and a second region of a second conductivity type selectively formed on a main surface of the first region are provided. A semiconductor device including a pressure-resistant structure portion composed of a third region of the first conductivity type selectively formed on a main surface of the region and the second region; A fourth region of the first conductivity type selectively formed on the surface and a fifth region of the second conductivity type selectively formed on the main surface of the third region of the breakdown voltage structure, There is provided a semiconductor device comprising: a diode.

According to such a semiconductor device, the diodes formed in the withstand voltage structure that separate the circuits having different reference potentials are separated from each other by interposing the withstand voltage structure of the level-down circuit. It is not necessary to form a diode for signal transmission in the circuit, and the chip area can be reduced. In addition, since the diode does not transmit signals when one circuit has a higher potential than the other circuit, the diode should not be affected by noise generated by instantaneous voltage fluctuation during switching. Will be possible.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example a case where a level down circuit using a high breakdown voltage diode shown in FIG. 6 is applied to a high breakdown voltage IC. I do.

FIG. 1 is a schematic sectional view of a high voltage IC having the structure of a semiconductor device according to the present invention. In this figure,
The ground reference circuit 81 and the upper arm reference circuit 82
An N-region 84 is formed on the surface of the substrate 83 and a P-region 84 is formed on the surface.
Forming a region 85 and further forming a thermal oxide film LOC on the surface thereof;
The OS is formed and separated by a pressure-resistant structure 86 having a double RESURF structure. Although not shown, the ground reference circuit 81 and the upper arm reference circuit 82 are formed with the above-described semiconductor switch, FWD, drive circuit, and the like.

The ground reference circuit 81 has a P + region 87 connected to the reference potential GND, and the upper arm reference circuit 82 has an N + region 88 connected to the power supply VDDP and a P + region connected to the reference potential GNDP. 89 are formed. Further, the P- region 8 of the breakdown voltage structure 86 is formed.
5, an N + region 90 is formed at the end on the side of the upper arm reference circuit 82, and the ground reference circuit 81 adjacent to the P-
+ Region 91 is formed. Here, a high breakdown voltage diode is formed in which the N + region 90 formed in the P− region 85 on the upper arm reference circuit 82 side is a cathode, and the P + region 91 on the ground reference circuit 81 side is an anode. This high voltage diode corresponds to the diode 60 of the level down circuit illustrated in FIG.

FIG. 2 is a schematic view of the periphery of the high breakdown voltage diode of the high breakdown voltage IC viewed from above. In this figure, the upper arm reference circuit region 82a and the ground reference circuit region 81a are separated by a withstand voltage structure 86 having a double RESURF structure. The high voltage diodes 92 to 95 are formed in the high voltage structure 86. In the illustrated example, the four high-withstand-voltage diodes 92 to 9 are connected to the withstand-voltage structure 86.
Although the case where 5 is formed is shown, this number can be increased or decreased as necessary. The high voltage diodes 92 to 95 are
The side in contact with the upper arm reference circuit area 82a is a cathode, and the side in contact with the ground reference circuit area 81a is an anode.

Although not shown, a low breakdown voltage N-channel MOS type FET of a level down circuit is formed in the upper arm reference circuit region 82a, and its drain is connected to the cathodes of the high breakdown voltage diodes 92 to 95. Constitute the outputs 96 to 99 of the level down circuit.

Next, the potential separation between the high breakdown voltage diodes and the potential separation between the high breakdown voltage diode and the breakdown voltage structure will be described. FIG. 3 is an explanatory diagram of the separation of the high breakdown voltage diode.

First, the potential separation between the high-breakdown-voltage diodes is achieved by the P + region 91 and P region 91a below the anode, the P- region 85 below the thermal oxide film LOCOS, and the N + forming the cathode shown in FIG. This is performed by separating the region 90. That is, in FIG.
94 are disposed adjacent to each other, and the P + region 9 below the anode is provided in the separation region 100 located therebetween.
1, the P region 91a, the P- region 85 under the thermal oxide film LOCOS, and the N + region 90 forming the cathode are not formed, and the high voltage diodes 93 and 94 are separated from each other.

The potential separation between the high breakdown voltage diode and the breakdown voltage structure portion is also achieved by separating the P + region 91 and P region 91a under the anode and the P- region 85 under the thermal oxide film LOCOS shown in FIG. It is done by doing. That is, in FIG. 3, the high-breakdown-voltage diode 94 and the withstand-voltage structure 86 are arranged adjacent to each other.
1, a P + region 91 under the anode shown in FIG.
The region 91a and the P + region and the P region below the reference potential GND of the ground reference circuit shown in FIG. 7 are not formed, and the P- region 85 below the thermal oxide film LOCOS is not formed. Thus, the high voltage diode 94 and the high voltage structure 86 can be separated. The N + region 90 forming the cathode of the high voltage diode 94 also terminates at the isolation region 101.

Although the breakdown voltage structure shown in FIG. 3 is formed at the curvature portion, it may be formed at a straight line portion. According to the present embodiment, the high withstand voltage diode can be built in the withstand voltage structure portion of the double RESURF structure formed for separating the upper arm reference circuit and the ground reference circuit shown in FIG. Since it is not necessary to form a high withstand voltage diode in a region of the ground reference circuit outside the upper arm reference circuit separated by the withstand voltage structure, the chip area can be significantly reduced.

When the high breakdown voltage diode is applied to the level down circuit as shown in FIG. 6, the semiconductor switch has a function of transmitting a signal only when the reference potential of the upper arm reference circuit drops. There is no fear that the inverter device malfunctions due to the noise generated by the voltage fluctuation according to the fluctuation of the potential of the upper arm reference circuit due to the switching.

Similarly, in a high breakdown voltage IC, when a resurf structure having no P- region in the breakdown voltage structure is used, the P- region 85 and the N + region 90 of the cathode as shown in FIG. , A high breakdown voltage diode can be formed.

[0050]

As described above, according to the present invention, in a high withstand voltage IC used for controlling and driving a power device, a withstand voltage structure for separating an upper arm reference circuit and a ground reference circuit has a double RESURF structure. Alternatively, a RESURF structure is used, and a high-breakdown-voltage diode is formed in the withstand-voltage structure. As a result, it is possible to reduce the cost by reducing the chip size and to prevent the malfunction due to the potential change of the upper arm reference circuit.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a high withstand voltage IC having the structure of a semiconductor device according to the present invention.

FIG. 2 is a schematic view of the periphery of a high breakdown voltage diode of a high breakdown voltage IC viewed from above.

FIG. 3 is an explanatory diagram of separation of a high breakdown voltage diode.

FIG. 4 is a diagram illustrating a configuration example of an inverter device.

FIG. 5 is a diagram showing a detailed configuration of a drive circuit for one phase and a peripheral portion thereof.

FIG. 6 is a circuit diagram showing details of a portion transmitting an alarm signal from an upper arm reference circuit.

FIG. 7 is a schematic sectional view of a pressure-resistant structure using a double RESURF structure.

FIG. 8 is a schematic view of a level down circuit of a high breakdown voltage IC using a high breakdown voltage P-channel MOS FET as viewed from above.

FIG. 9 is a schematic diagram of a level down circuit of a high breakdown voltage IC using a high breakdown voltage diode as viewed from above.

[Explanation of symbols]

 10-phase AC motor 20 Ground reference circuit 21 to 23 Semiconductor switch 24 to 26 FWD 27 to 29 Drive circuit 27a Power supply monitoring unit 27b Abnormality detection unit 27c Interface unit 27d Driver 30 Upper arm reference circuit 31 to 33 Semiconductor switch 34 to 36 FWD 37 Drive circuit 37a Power supply monitoring unit 37b Abnormality detection unit 37c Interface unit 37ca Transistor 37cb Inverter 37cc Power supply 37cd Flip-flop 37d Driver 40 Interface circuit 40a Power supply 40b Inverter 40c Resistance 50 Control unit 60 Diode 71 P substrate 72 N-region 73 P- Region 75 Upper arm reference circuit region 76 Ground reference circuit region 77 Breakdown voltage structure 78 P-channel MOS type FET 78a Breakdown voltage structure 79 Level down Circuit output 80 High voltage diode 80a Cathode 80b Anode 80c Voltage resistant structure 81 Ground reference circuit 81a Ground reference circuit area 82 Upper arm reference circuit 82a Upper arm reference circuit area 83 P substrate 84 N-region 85 P-region 86 Pressure resistant structure 87 P + region 88 N + region 89 P + region 90 N + region 91 P + region 91 a P region 92 to 95 High voltage diode 96 to 99 Output of level down circuit 100, 101 Isolation region LOCOS Thermal oxide film GND Reference potential of ground reference circuit GNDP Reference potential of arm reference circuit VDDP Power supply of upper arm reference circuit

Claims (5)

[Claims] 1. A first region of a first conductivity type, a second region of a second conductivity type selectively formed on a main surface of the first region, and a first region selectively formed on a main surface of the second region. A semiconductor device having a breakdown voltage structure configured by a third region of the first conductivity type, further comprising: a third region of the first conductivity type selectively formed on a main surface of the second region of the breakdown voltage structure. A semiconductor device comprising: a diode having four regions and a fifth region of the second conductivity type selectively formed on a main surface of the third region of the breakdown voltage structure portion. 2. The high withstand voltage diode according to claim 2, wherein the fourth region and the fifth region are arranged on two sides of the circuit separated by the withstand voltage structure. Item 2. The semiconductor device according to item 1. 3. The semiconductor device according to claim 2, wherein a plurality of circuits having different reference potentials separated by said breakdown voltage structure portion are provided to constitute a high breakdown voltage integrated circuit. 4. The semiconductor device according to claim 2, wherein the diode is used for signal transmission between circuits having different reference potentials separated by the withstand voltage structure. 5. A first region of a first conductivity type, a second region of a second conductivity type selectively formed on a main surface of the first region, and a first region of the second conductivity type selectively formed on a main surface of the second region. A withstand voltage structure portion including a third region of the first conductivity type, and the first conductivity type selectively formed on one side of the main surface of the second region sandwiching the withstand voltage structure portion. A fourth region, and a fifth region of the second conductivity type selectively formed on the other side of the main surface of the third region sandwiching the withstand voltage structure. High-voltage diode featuring.