JP2002057326A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MOS transistor having a high drain breakdown voltage, small capacitance between a drain-source region and a gate electrode, and a high junction breakdown voltage of a channel stop and a source-drain region formed under a field oxide film, which are impossible in a conventional MOS transistor having an LDD structure and having an intermediate breakdown voltage structure capable of controlling the drain breakdown voltage. SOLUTION: A high concentration diffused region is formed by ion implanting with a contact hole of the MOS transistor as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS transistor having a medium withstand voltage structure having a withstand voltage of 8 V to 30 V.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 6, a polycrystalline silicon gate electrode 104 having a gate oxide film 102 formed on a silicon semiconductor substrate 101 and side spacers 103 at both ends, and located immediately below the side spacers. An LDD structure including a low-concentration diffusion layer 105 formed on the surface of a silicon substrate, high-concentration diffusion layers 106 called source / drain formed on the surface of the silicon substrate at both ends of the gate electrode, and a channel region 107 therebetween is known. I was

[0003]

However, in the conventional MOS transistor having the LDD structure, the width of the side spacer is extremely small, and therefore, the width of the impurity concentration region is also small and a withstand voltage of 8 V to 30 V can be obtained. And the capacitance between the drain / source region and the gate electrode did not decrease. In addition, since the ends of the source / drain regions, which are high impurity concentration regions, terminate at the field oxide film, there is a problem that the junction breakdown voltage with the channel stop layer formed under the field oxide film is low. Had.

[0004] The present invention relates to an M0 having a conventional LDD structure.
The drain breakdown voltage, which was impossible with an S-type transistor, is large. The capacitance between the drain / source region and the gate electrode is small. The junction breakdown voltage between the channel stop formed under the field oxide film and the source / drain region is high. It is an object of the present invention to provide a medium-voltage MOS transistor having a withstand voltage of 10 V or more that can control a drain withstand voltage by a simple process.

[0005]

To achieve the above object, the present invention uses the following means. (1) A field oxide film formed on the one conductivity type semiconductor substrate, a gate electrode formed on the one conductivity type semiconductor substrate via the gate oxide film, and surrounded by the field oxide film and the gate electrode A low-concentration reverse-conductivity-type source / drain region, an interlayer film for electrically insulating the gate electrode, the low-concentration reverse-conductivity-type source / drain, and a wiring formed thereover; And a contact hole for electrically connecting the gate electrode and the low-concentration reverse-conductivity-type source / drain, and only the low-concentration reverse-conductivity-type source / drain region where the contact hole is opened. A semiconductor device characterized in that it is a high-concentration reverse conductivity type diffusion layer. (2) The semiconductor device, wherein the impurity concentration of the low-concentration reverse conductivity type source / drain region is 1E16 to 1E18 atoms / cm ³ . (3) The impurity concentration of the high concentration reverse conductivity type diffusion layer is 1E1
A semiconductor device characterized in that the density is 9 to 5E20 atoms / cm ³ . (4) In a MOS transistor having a medium withstand voltage structure, a step of forming a gate insulating film on a surface of a semiconductor substrate, a step of patterning and forming a gate electrode on the gate insulating film, and using the gate electrode as a mask Forming a low-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, forming an impurity-containing interlayer film on the front surface, and flattening the film by heat treatment; Forming a contact hole in the low-concentration diffusion region and the gate electrode, and forming a high-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate using the contact hole as a mask; A heat treatment process and a photolithographic process after forming a metal film over the entire surface by vacuum evaporation or sputtering. Patterning the metal material subjected Ficoll method and etching was characterized by comprising the step of covering the whole of the semiconductor substrate with the surface protective film. (5) The interlayer film containing impurities is a BPSG interlayer film. (6) The heat treatment after forming the oxide film containing the impurity is performed by 800
It is characterized in that it is formed at a temperature of ５０1050 ° C. within 3 minutes and activated. (7) In the method for manufacturing a MOS transistor, a step of forming a gate insulating film on the surface of a semiconductor substrate, a step of patterning and forming a gate electrode on the gate insulating film, and an impurity using the gate electrode as a mask Forming a low-concentration diffusion region by ion-implanting into the surface of the semiconductor substrate, forming an interlayer film containing impurities on the front surface, planarizing the film by heat treatment, and selectively etching the interlayer film. Forming a contact hole in the low-concentration diffusion region and the gate electrode; and forming a polysilicon film over the entire surface by a CVD method and then ion-implanting or implanting a high-concentration phosphorus as an impurity element using an impurity nucleic acid furnace. Patterning the polysilicon by photolithography and etching; and impurities in the polysilicon. Forming a high-concentration diffusion region by diffusing the metal material over the surface of the semiconductor substrate by applying heat treatment, and forming a metal material over the entire surface by vacuum evaporation or sputtering or the like, and then performing photolithography and etching on the metal material. And a step of covering the entirety of the semiconductor substrate with a surface protective film. (8) The interlayer film containing impurities is a BPSG interlayer film. (9) The heat treatment after the formation of the oxide film containing the impurity is performed by 800
It is characterized in that it is formed at a temperature of ５０1050 ° C. within 3 minutes and activated.

[0006]

According to the semiconductor device of the present invention, the drain withstand voltage is large, the capacitance between the drain / source region and the gate electrode is small, and the channel stop and the source / drain region formed below the field oxide film are formed. It is possible to provide a MOS transistor having a high junction breakdown voltage and capable of controlling the drain breakdown voltage thereof and suitable for an operation region of 8 V to 30 V.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. A first embodiment of the semiconductor device according to the present invention will be described in detail. FIG. 1 is a schematic sectional view of a P-channel MOS transistor having a medium breakdown voltage structure of a semiconductor device according to the present invention.

[0008] The P-channel MOS type transistor is composed of an N-type well region 2 formed on a P-type silicon semiconductor substrate 201.
02, and a high-concentration P-type diffusion layer 204 formed on the silicon substrate surface at both ends of the gate electrode and a high-concentration formed using the contact hole 210 as a mask. And a channel region 207 therebetween. A field oxide film 208 and a channel stop region 209 are formed between the elements for the purpose of isolation. It is not always necessary to form an N-type well region using a P-type silicon semiconductor substrate, and a P-channel MOS transistor may be formed on an N-type silicon semiconductor substrate.

When forming a reverse conductivity type N-channel MOS transistor, a P-type well region is formed on an N-type silicon semiconductor substrate, and a gate oxide film and a polycrystalline silicon gate electrode formed on the P-type well region are formed. And a low-concentration N- type diffusion layer and a high-concentration N + type diffusion layer formed on the surface of the silicon substrate at both ends of the gate electrode, and a channel region therebetween. A field oxide film and a channel stop region are formed between the devices for the purpose of isolation. Note that it is not necessary to use an N-type silicon semiconductor substrate, and an N-channel MOS transistor may be manufactured using a P-type silicon semiconductor substrate.

As is clear from FIG. 1, the distance (S1) between one end of the gate electrode and one end of the high concentration diffusion region can be easily changed by changing the formation position of the contact hole. . Further, by changing the position where the contact hole is formed, the distance (S2) between one end of the high concentration diffusion region and one end of the field oxide film can be easily changed. That is, the widths S1 and S2 of the low-concentration diffusion region and the low-concentration diffusion region depend on the required drain breakdown voltage, the junction breakdown voltage with the channel stop under the field oxide film, and the overlap capacitance between the drain / source region and the gate electrode. By controlling the concentration of the region, high integration and
A MOS transistor suitable for high speed operation can be obtained.
An example will be described with reference to FIGS.

FIG. 2 shows an ion implantation method for the low concentration diffusion region.
Dose is 2.5E12 atom / cm ²When formed with
Between one end of the gate electrode and the contact hole.
FIG. 6 is a diagram showing a relationship between a distance (S1) at one end and a drain withstand voltage.
You. According to FIG. 2, the drain voltage changes when S1 is changed.
You can see that it is. Further, the low concentration region and the high concentration region
Easy drain breakdown voltage by changing the concentration of the concentration region
Can be changed.

FIG. 3 shows the relationship between the distance (S2) between one end of the high concentration diffusion region and one end of the field oxide film and the junction breakdown voltage between the high concentration diffusion region and the channel stop below the oxide film. FIG.

FIG. 3 shows that the junction withstand voltage can be easily changed by changing S2. Also, the junction withstand voltage can be easily changed by changing the concentration of the channel stop, the low concentration diffusion region and the high concentration diffusion region.

FIG. 4 is a sectional view in the order of steps showing a method for manufacturing a P-channel MOS in a first embodiment of the semiconductor device according to the present invention.

First, in step a, an N-well layer 202 is formed on the surface of a P-type silicon semiconductor substrate 201. After a silicon nitride film patterned into a predetermined shape is formed as a mask on the substrate surface, N-type impurities, for example, phosphorus are ion-implanted at a dose of 2E12 atoms / cm ² . Thereafter, a so-called LOCOS process is performed to remove the silicon nitride film formed in the previous step. Next, a heat treatment is performed at 1150 ° C. for 6 hours to diffuse and activate the implanted impurity phosphorus, thereby forming an N well layer 202 as shown. A P-channel MOS transistor is formed in N well layer 202. Further, it is not always necessary to use a P-type silicon semiconductor substrate. An N-type silicon semiconductor substrate may be used to form an N-type well region, and a P-channel MOS transistor may be formed in the N-type well region. A P-channel MOS transistor may be formed in a silicon semiconductor substrate.

In step b, the channel stop region 20
9 is formed. For this purpose, first, a silicon nitride film 601 is formed so as to cover an active region where a transistor element is formed.
Is formed by patterning. A photoresist 602 is also formed on the N-well layer 202 so as to overlap the silicon nitride film 601. In this state, impurity boron is ion-implanted at an acceleration energy of 30 KeV and a dose of 2E13 atoms / cm 2 to form a channel stop region 209. As illustrated, a channel stop region 209 is formed in a portion including the element region.

Subsequently, in step c, a so-called LOCOS process is performed to form a field oxide film 206 so as to surround the element region. After that, sacrificial oxidation and removal treatment are performed to remove and clean foreign substances left on the surface of the substrate. In step d, thermal oxidation of the substrate surface forms a gate oxide film 211 in an H ₂ O atmosphere. In the present invention, the thermal oxidation treatment was performed at a temperature of 860 ° C. in an H ₂ O atmosphere to form an oxide film at about 300 °. Normally, the thickness of a gate insulating film formed of a thermal oxide film to guarantee the reliability of a semiconductor device is 3 MV / cm.
It is necessary to set the thickness to about the same. For example, when the MOS transistor has a power supply voltage of 30 V, an oxide film thickness of 1000 ° or more is required.

Next, in step e, a polysilicon 603 is deposited on the gate oxide film 211 by a CVD method. In the present invention, 4000 ° polysilicon is formed. MO
In order to form the gate electrode 205 for the S transistor,
The polysilicon 603 is made N-type. This polysilicon 6
03 is ion-implanted or an impurity nucleic acid furnace is used to implant a high concentration of phosphorus as an impurity element. The implantation concentration is set to ion implantation / polysilicon film thickness = 2E19 atoms / cm ³ or more. In addition, MO
The gate electrode for the S transistor does not necessarily need to be N-type, but may be P-type by implanting boron as an impurity element at a high concentration by ion implantation or an impurity diffusion furnace.

Next, after removing the photoresist formed in the previous step in step f, a low concentration diffusion layer 204 of the P-type MOS transistor is formed. In this state, the gate electrode 2
P by self-alignment using 05 as a mask
The BF ₂ or boron is type impurity dose of 1 × 1012~
1 × 10 13 atoms / cm ² ions are implanted. This is about 1 × 10 16 to 1 × 10 18 atoms / cm ³ in terms of density.

Subsequently, in step g, after forming the low-concentration diffusion layer 204 of the P-channel MOS transistor, the photoresist is removed and, for example, a BPSG interlayer film 213 is formed on the front surface. This interlayer film is formed, for example, by a CVD method or the like.
It is planarized by a heat treatment at 0 to 950 ° C. for about 30 minutes to 2 hours. Subsequently, the interlayer film 213 is selectively etched to form a contact hole 210 in the high concentration diffusion region 203 and the gate electrode 205. In the present invention, the contact hole is round-etched by wet etching after dry etching. In this state, self-alignment using contact hole 210 as a mask is performed.
Dose of P-type impurity ^{_{BF 2 3 × 10 15 ~5 ×}} 10 16 atoms / cm 2 is ion-implanted. This is 1 × 10 ^{19 to} 5 ×
It is about 10 ²⁰ atoms / cm ³ . Thereafter, heat treatment is performed to activate the ion-implanted impurities and improve the contact shape. In the present invention, heat treatment was performed at 800 to 1050 ° C. for 3 minutes or less.

Subsequently, in a step h, a metal material is entirely formed by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 212. Finally, the entire substrate is covered with a surface protection film 214. Although the embodiment of the P-channel MOS transistor has been described above, similar effects can be obtained by forming an N-channel MOS transistor using impurities of the opposite conductivity type.

FIG. 5 is a sectional view showing a method of manufacturing a P-channel MOS according to a first embodiment of the semiconductor device according to the present invention.

In the present invention, the steps of FIGS. 4A to 4F are the same. Thereafter, in step I, after forming a low-concentration diffusion layer 204 of a P-channel MOS transistor, the photoresist is removed and the front surface is removed. For example, a BPSG interlayer film 213 is formed.
This interlayer film is formed by, for example,
The surface is planarized by a heat treatment at 00 to 950 ° C. for about 30 minutes to 2 hours. Subsequently, the interlayer film 213 is selectively etched to form a contact hole 210 in the high concentration diffusion region 203 and the gate electrode 205. In the present invention, the contact hole is round-etched by wet etching after dry etching. In this state, for example, a polysilicon film is formed on the front surface by a CVD method to form a P-type. The polysilicon in the ion implantation or impurity nucleic furnace to a high concentration implanting boron or BF ₂ is an impurity element. The implantation concentration is ion implantation / polysilicon film thickness = 2E19atoms / c
m ³ or more. Thereafter, the polysilicon wiring 3 patterned by photolithography and etching is used.
01 is formed. Thereafter, heat treatment is performed to diffuse impurities from the polysilicon to the substrate surface and improve the contact shape. In the present invention, heat treatment was performed at 800 to 1050 ° C. for 3 minutes or less. A high concentration diffusion region is formed by self-alignment using contact hole 210 as a mask.

Subsequently, in a step II, a metal material is entirely formed by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 212. Finally, the entire substrate is covered with a surface protection film 214. Although the embodiment of the P-channel MOS transistor has been described above, similar effects can be obtained by forming an N-channel MOS transistor using impurities of the opposite conductivity type.

[0025]

As described above, according to the present invention, a high-concentration diffusion region is formed by ion-implanting a MOS transistor required to operate in a medium withstand voltage region of 8 V to 30 V using a contact hole as a mask. This makes it possible to easily change the distance between one end of the contact hole, one end of the gate electrode, one end of the contact hole, and one end of the field oxide film. The drain withstand voltage, which was impossible, is large, and the drain withstand voltage can be controlled. The overlap capacitance between the drain / source region and the gate electrode is small, and the channel stop and the source / drain formed under the field oxide film are formed. It is possible to provide a MOS transistor with a high junction breakdown voltage in the region by a simple process. That.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a P-channel MOS transistor showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a relationship between a distance (S1) between one end of a gate electrode and one end of a source / drain contact hole and a drain withstand voltage.

FIG. 3 is a diagram showing a relationship between a distance (S1) between one end of a channel stop below a field oxide film and one end of a source / drain contact hole and a junction withstand voltage.

FIG. 4 is a cross-sectional view in the order of steps showing a method for manufacturing the P-channel MOS transistor shown in the first embodiment of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing the P-channel MOS transistor shown in the first embodiment of the semiconductor device according to the present invention in the order of steps.

FIG. 6 is a final sectional view of a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Gate oxide film 103 Side spacer 104 Polycrystalline silicon gate electrode 105 Low concentration diffusion layer 106 High concentration diffusion layer 107 Channel dope layer 201 P− type silicon semiconductor substrate 202 N− type well layer 203 P + type diffusion layer 204 P-type diffusion layer 205 polycrystalline silicon gate electrode 207 channel region 208 field oxide film 209 channel stop 210 contact hole 211 gate oxide film 212 metal wiring 213 BPSG interlayer film 214 protective film 301 polysilicon wiring 601 silicon nitride film 602 photoresist 603 polysilicon

Claims (9)

[Claims] A field oxide film formed on the one conductivity type semiconductor substrate, a gate electrode formed on the one conductivity type semiconductor substrate via a gate oxide film, the field oxide film and the gate electrode, A low-concentration reverse-conductivity-type source / drain region surrounded by an interlayer film that electrically insulates the gate electrode, the low-concentration reverse-conductivity-type source / drain, and a wiring formed thereover; A contact hole for electrically connecting the wiring, the gate electrode, and the low-concentration reverse-conduction-type source / drain;
A semiconductor device characterized in that only a drain region is selectively formed as a high concentration reverse conductivity type diffusion layer. 2. The semiconductor device according to claim 1, wherein an impurity concentration of said low concentration reverse conductivity type source / drain region is 1E16 to 1E18 atoms / cm ³ . 3. The semiconductor device according to claim 1, wherein the impurity concentration of the high concentration reverse conductivity type diffusion layer is 1E19 to 5E20 atoms / cm ³ . 4. A method of manufacturing a MOS transistor, comprising: forming a gate insulating film on a surface of a semiconductor substrate; forming a gate electrode on the gate insulating film by patterning; and masking the gate electrode. Forming a low-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, forming an impurity-containing interlayer film on the front surface, and flattening the film by heat treatment; Forming a contact hole in the low-concentration diffusion region and the gate electrode, and forming a high-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate using the contact hole as a mask; A heat treatment process and a photolithographic process after forming a metal film over the entire surface by vacuum evaporation or sputtering. A method of manufacturing a MOS transistor, comprising: a step of patterning the metal material by performing a fi method and etching; and a step of covering the entire semiconductor substrate with a surface protective film. 5. The method according to claim 4, wherein said interlayer film containing impurities is a BPSG interlayer film. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the heat treatment after forming the oxide film containing the impurity is performed at a temperature of 800 to 1050 ° C. within 3 minutes and activated. 7. A method for manufacturing a MOS transistor, wherein a step of forming a gate insulating film on a surface of a semiconductor substrate, a step of patterning and forming a gate electrode on the gate insulating film, and masking the gate electrode Forming a low-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, forming an impurity-containing interlayer film on the front surface, and flattening the film by heat treatment; Forming a contact hole in the low-concentration diffusion region and the gate electrode, and then performing high-concentration implantation of phosphorus as an impurity element by ion implantation or an impurity nucleic acid furnace after forming polysilicon entirely by a CVD method. Performing a patterning process by photolithography and etching to pattern the polysilicon; A step of forming a high-concentration diffusion region by diffusing the impurities in the surface of the semiconductor substrate by applying a heat treatment, and performing a photolithography method and etching after forming a metal material over the entire surface by vacuum evaporation or sputtering. A method for manufacturing a MOS transistor, comprising: a step of patterning a metal material; and a step of covering the entire semiconductor substrate with a surface protective film. 8. The method of manufacturing a semiconductor device according to claim 7, wherein said interlayer film containing impurities is a BPSG interlayer film. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the heat treatment after forming the oxide film containing the impurity is performed at a temperature of 800 to 1050 ° C. within 3 minutes to activate the semiconductor device.