JP2002057328A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS transistor having an intermediate breakdown voltage structure capable of controlling a drain breakdown voltage with a high drain breakdown voltage impossible in a conventional MOS transistor having an LDD structure and forming a plurality of MOS transistors having different breakdown voltages on the same substrate without increasing masks. SOLUTION: The breakdown voltage can be easily changed by altering a distance between one end of a gate electrode and one end of a high concentration diffused region by forming a high concentration diffused region by ion implanting by using a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS transistor having a medium withstand voltage structure having a withstand voltage of 8 V to 30 V.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a polycrystalline silicon gate electrode 104 having a gate oxide film 102 formed on a silicon semiconductor substrate 101 and side spacers 103 at both ends, and located immediately below the side spacers. An LDD structure including a low-concentration diffusion layer 105 formed on the surface of a silicon substrate, high-concentration diffusion layers 106 called source / drain formed on the surface of the silicon substrate at both ends of the gate electrode, and a channel region 107 therebetween is known. I was

[0003]

However, in the conventional MOS transistor having the LDD structure, the width of the side spacer is extremely small, and therefore, the width of the impurity concentration region is also small and a withstand voltage of 8 V to 30 V can be obtained. In addition, there is a problem that a plurality of MOS transistors having a withstand voltage cannot be easily formed on the same substrate.

[0004] The present invention relates to an M0 having a conventional LDD structure.
The drain withstand voltage, which was impossible with an S-type transistor, is large, and the drain withstand voltage can be controlled.
8V to 30V that allows multiple MOS transistors with different breakdown voltages to be formed on the same substrate without increasing the mask
It is an object of the present invention to provide a medium-breakdown-voltage MOS transistor having a withstand voltage by a simple process.

[0005]

To achieve the above object, the present invention uses the following means. (1) A field oxide film formed on the one conductivity type semiconductor substrate, a gate electrode formed on the one conductivity type semiconductor substrate via the gate oxide film, and surrounded by the field oxide film and the gate electrode A source / drain region having a low concentration and having a low concentration, and a source / drain region for electrically connecting a wiring with the source / drain region having a low concentration.
A drain region only selectively having a high-concentration reverse conductivity type diffusion layer; and an interlayer film for electrically insulating the gate electrode, the reverse conductivity type source / drain, and the wiring formed thereon. And a contact hole for electrically connecting the wiring, the gate electrode, and the high-concentration reverse conductivity type source / drain. (2) The semiconductor device, wherein the impurity concentration of the low-concentration reverse conductivity type source / drain region is 1E16 to 1E18 atoms / cm ³ . (3) The impurity concentration of the high concentration reverse conductivity type diffusion layer is 1E1
A semiconductor device characterized in that the density is 9 to 5E20 atoms / cm ³ . (4) By changing the distance between one end of the gate electrode and one end of the high-concentration diffusion region, the width of the low-concentration diffusion region is changed, and a plurality of MOS transistors having different breakdown voltages are formed on the same substrate. A semiconductor device which can be provided without increasing the number of masks. (5) In a MOS transistor having a medium breakdown voltage structure, a step of forming a gate insulating film on a surface of a semiconductor substrate, a step of patterning and forming a gate electrode on the gate insulating film, and a step of masking the gate electrode. Forming a low-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate, selectively etching a resist, and ion-implanting impurities into the surface of the semiconductor substrate using the resist as a mask. Forming a high concentration diffusion region, forming an interlayer film containing impurities on the front surface, and planarizing the film by heat treatment, and selectively etching the interlayer film to contact the low concentration diffusion region and the gate electrode. Steps of forming holes, steps of heat treatment, and metallization by vacuum evaporation or sputtering. Patterning the metal material subjected to photolithography and etching after forming, it was characterized by comprising the step of covering the whole of the semiconductor substrate with the surface protective film. (6) The interlayer film containing impurities is a BPSG interlayer film. (7) The heat treatment after the formation of the oxide film containing the impurity is performed by 800
It is characterized in that it is formed at a temperature of ５０1050 ° C. within 3 minutes and activated.

[0006]

According to the semiconductor device of the present invention, a plurality of MOS transistors having different withstand voltage on the same substrate can be controlled with a large drain withstand voltage and the drain withstand voltage can be controlled.
It is possible to provide a MOS transistor suitable for an operation region of 8 V to 30 V in which the transistor can be formed without increasing the mask.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. A first embodiment of the semiconductor device according to the present invention will be described in detail. FIG. 1 is a schematic sectional view of a P-channel MOS transistor having a medium breakdown voltage structure of a semiconductor device according to the present invention.

[0008] The P-channel MOS type transistor is composed of an N-type well region 2 formed on a P-type silicon semiconductor substrate 201.
02, a gate oxide film 211 and a polycrystalline silicon gate electrode 205, a low-concentration P- type diffusion layer 204 formed on the silicon substrate surface at both ends of the gate electrode, and a high-concentration P + type selectively formed It comprises a diffusion layer 203 and a channel region 207 therebetween. A field oxide film 208 and a channel stop region 209 are formed between the elements for the purpose of isolation. It is not always necessary to form an N-type well region using a P-type silicon semiconductor substrate, and a P-channel MOS transistor may be formed on an N-type silicon semiconductor substrate.

When forming a reverse conductivity type N-channel MOS transistor, a P-type well region is formed on an N-type silicon semiconductor substrate, and a gate oxide film and a polycrystalline silicon gate electrode formed on the P-type well region are formed. And a low-concentration N- type diffusion layer and a high-concentration N + type diffusion layer formed on the surface of the silicon substrate at both ends of the gate electrode, and a channel region therebetween. A field oxide film and a channel stop region are formed between the devices for the purpose of isolation. Note that it is not necessary to use an N-type silicon semiconductor substrate, and an N-channel MOS transistor may be manufactured using a P-type silicon semiconductor substrate.

As is apparent from FIG. 1, the distance (S1) between one end of the gate electrode and one end of the high concentration diffusion region can be easily changed by changing the formation position of the high concentration diffusion layer. It is possible. In other words, by controlling the width S1 of the low-concentration diffusion region and the concentration of the low-concentration diffusion region according to the required drain breakdown voltage, a MOS transistor suitable for high integration and high speed can be obtained. . Also, S1
By changing the MOS, the MOS with different breakdown voltage can be easily mounted on the same substrate.
A plurality of type transistors can be formed. As an example,
This will be described with reference to FIGS.

FIG. 2 shows the distance (S1) between one end of the gate electrode and one end of the high-concentration diffusion layer when the low-concentration diffusion region is formed at a dose of 2.5E12 atom / cm 2 by ion implantation. FIG. 4 is a diagram showing the relationship between the parentheses and the drain withstand voltage.

FIG. 2 shows that the drain voltage changes when S1 is changed. Further, the drain withstand voltage can be easily changed by changing the concentrations of the low concentration region and the high concentration region. For example, S1 on the same substrate
By forming a MOS transistor of 1.0 μm and a MOS transistor of S1 = 2 μm, it is possible to form a 15 V MOS transistor and a 22 V MOS transistor having different breakdown voltages on the same substrate.

FIG. 3 is a sectional view in the order of steps showing a method for manufacturing a P-channel MOS of a first embodiment of a semiconductor device according to the present invention.

First, in step a, an N well layer 202 is formed on the surface of a P-type silicon semiconductor substrate 201. After a silicon nitride film patterned into a predetermined shape is formed as a mask on the substrate surface, N-type impurities, for example, phosphorus are ion-implanted at a dose of 2E12 atoms / cm ² . Thereafter, a so-called LOCOS process is performed to remove the silicon nitride film formed in the previous step. Next, a heat treatment is performed at 1150 ° C. for 6 hours to diffuse and activate the implanted impurity phosphorus, thereby forming an N well layer 202 as shown. A P-channel MOS transistor is formed in N well layer 202. Further, it is not always necessary to use a P-type silicon semiconductor substrate. An N-type silicon semiconductor substrate may be used to form an N-type well region, and a P-channel MOS transistor may be formed in the N-type well region. A P-channel MOS transistor may be formed in a silicon semiconductor substrate.

In step b, the channel stop region 20
9 is formed. For this purpose, first, a silicon nitride film 601 is formed so as to cover an active region where a transistor element is formed.
Is formed by patterning. A photoresist 602 is also formed on the N-well layer 202 so as to overlap the silicon nitride film 601. In this state, impurity boron is ion-implanted at an acceleration energy of 30 KeV and a dose of 2E13 atoms / cm ² to form a channel stop region 209. As illustrated, a channel stop region 209 is formed in a portion including the element region.

Subsequently, in step c, a so-called LOCOS process is performed to form a field oxide film 206 so as to surround the element region. After that, sacrificial oxidation and removal treatment are performed to remove and clean foreign substances left on the surface of the substrate.

In the step d, the thermal oxidation treatment of the substrate surface is H2
A gate oxide film 211 is formed in an O atmosphere. In the present invention, the thermal oxidation treatment was performed at a temperature of 860 ° C. in an H 2 O atmosphere to form an oxide film at about 300 °. Usually, in order to guarantee the reliability of a semiconductor device, it is necessary to set the thickness of a gate insulating film formed of a thermal oxide film to a thickness of about 3 MV / cm. For example, when the MOS transistor has a power supply voltage of 30 V, an oxide film thickness of 1000 ° or more is required.

Next, in step e, a polysilicon 603 is deposited on the gate oxide film 211 by a CVD method. In the present invention, 4000 ° polysilicon is formed. MO
In order to form the gate electrode 205 for the S transistor,
The polysilicon 603 is made N-type. This polysilicon 6
03 is ion-implanted or an impurity nucleic acid furnace is used to implant a high concentration of phosphorus as an impurity element. The implantation concentration is set to ion implantation / polysilicon film thickness = 2E19 atoms / cm ³ or more. In addition, MO
The gate electrode for the S transistor does not necessarily need to be N-type, but may be P-type by implanting boron as an impurity element at a high concentration by ion implantation or an impurity diffusion furnace.

Next, after removing the photoresist formed in the previous step in step f, a low concentration diffusion layer 204 of the P-type MOS transistor is formed. In this state, the gate electrode 2
P by self-alignment using 05 as a mask
The BF ₂ or boron is type impurity dose of 1 × 1012~
1 × 10 13 atoms / cm ² ions are implanted. This is about 1 × 10 16 to 1 × 10 18 atoms / cm ³ in terms of density.

Subsequently, in a step g, after forming the low concentration diffusion layer 204 of the P-channel MOS transistor, the photoresist is removed, and the high concentration diffusion layer 20 of the P-type MOS transistor is removed.
Form 3 After forming a photoresist patterned in a predetermined shape as a mask, a P-type impurity such as B
F ₂ ions are implanted at a dose of 3 × 10 ^{15 to} 5 × 10 ¹⁶ atoms / cm ² . This translates into a concentration of 1 × 10 ^{19 to} 5 × 10 ²⁰ atom
s / cm ³ . The formation position of the high concentration diffusion layer changes according to the required breakdown voltage.

Subsequently, in a step h, the photoresist is removed and, for example, a BPSG interlayer film 213 is formed on the front surface. This interlayer film is formed by, for example,
It is planarized by a heat treatment at 950 ° C. for about 30 minutes to 2 hours. Subsequently, the interlayer film 213 is selectively etched to form a contact hole 210 in the high concentration diffusion region 203 and the gate electrode 205. In the present invention, the contact hole is round-etched by wet etching after dry etching. Thereafter, heat treatment is performed to activate the ion-implanted impurities and improve the contact shape. In the present invention, heat treatment was performed at 800 to 1050 ° C. for 3 minutes or less. After that, a metal material is entirely formed by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 212. Finally, the entire substrate is covered with a surface protective film 21.
Cover with 4.

Although the embodiment of the P-channel MOS transistor has been described above, an N-channel MOS transistor is formed by using impurities of the opposite conductivity type.
A similar effect can be obtained by forming an OS type transistor.

[0023]

As described above, according to the present invention, a high-concentration diffusion region is formed by ion-implanting a MOS transistor required to operate in a medium withstand voltage region of 8 V to 30 V using a mask. As a result, the distance between one end of the high-concentration diffusion region and one end of the gate electrode can be easily changed. As a result, the drain withstand voltage, which is impossible with a MOS transistor having a conventional LDD structure, is large.
In addition, it is possible to provide a MOS transistor capable of controlling its drain withstand voltage and capable of forming a plurality of MOS transistors having different withstand voltages on the same substrate without increasing the number of masks by a simple process.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a P-channel MOS transistor showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a relationship between a distance (S1) between one end of a gate electrode and one end of a source / drain contact hole and a drain withstand voltage.

FIG. 3 is a cross-sectional view in the order of steps of the P-channel MOS transistor shown in the first embodiment of the semiconductor device of the present invention.

FIG. 4 is a final sectional view in a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Gate oxide film 103 Side spacer 104 Polycrystalline silicon gate electrode 105 Low concentration diffusion layer 106 High concentration diffusion layer 107 Channel dope layer 201 P− type silicon semiconductor substrate 202 N− type well layer 203 P + type diffusion layer 204 P-type diffusion layer 205 Polycrystalline silicon gate electrode 207 Channel region 208 Field oxide film 209 Channel stop 210 Contact hole 211 Gate oxide film 212 Metal wiring 213 BPSG interlayer film 214 Protective film 601 Silicon nitride film 602 Photoresist 603 Polysilicon

Claims (7)

[Claims] A field oxide film formed on the one conductivity type semiconductor substrate, a gate electrode formed on the one conductivity type semiconductor substrate via a gate oxide film, the field oxide film and the gate electrode, And a source / drain region having a low concentration and having a low concentration, and a source / drain region for electrically connecting a wiring and the source / drain region having a low concentration are selectively selectively subjected to a high concentration. The reverse conductivity type diffusion layer, an interlayer film that electrically insulates the gate electrode, the reverse conductivity type source / drain and the wiring formed thereon, and the wiring and the gate electrode. A semiconductor device comprising a contact hole for electrically connecting the high-concentration reverse conductivity type source / drain. 2. The semiconductor device according to claim 1, wherein an impurity concentration of said low concentration reverse conductivity type source / drain region is 1E16 to 1E18 atoms / cm ³ . 3. The semiconductor device according to claim 1, wherein the impurity concentration of the high concentration reverse conductivity type diffusion layer is 1E19 to 5E20 atoms / cm ³ . 4. A plurality of MOS transistors having different breakdown voltages on the same substrate by changing the distance between one end of the gate electrode and one end of the high concentration diffusion region to change the width of the low concentration diffusion region. 2. The semiconductor device according to claim 1, wherein a transistor is formed. 5. A MOS transistor having a medium breakdown voltage structure, a step of forming a gate insulating film on a surface of a semiconductor substrate, a step of patterning and forming a gate electrode on the gate insulating film, Forming a low-concentration diffusion region by ion-implanting impurities into the surface of the semiconductor substrate using the mask as a mask, selectively etching the resist, and ion-implanting impurities into the surface of the semiconductor substrate using the resist as a mask Forming a high-concentration diffusion region, forming an interlayer film containing impurities on the front surface, and flattening by heat treatment, selectively etching the interlayer film to form the low-concentration diffusion region and the gate electrode. Forming a contact hole, performing a heat treatment, and forming a metal material by vacuum evaporation or sputtering. A method of manufacturing a MOS transistor, comprising: a step of patterning the metal material by performing a photolithography method and an etching after forming the entire surface; and a step of covering the entire semiconductor substrate with a surface protective film. 6. The method according to claim 5, wherein the interlayer film containing impurities is a BPSG interlayer film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the heat treatment after forming the oxide film containing the impurities is performed at a temperature of 800 to 1050 ° C. within 3 minutes and activated.