JP2002044672A - Apparatus and method for reception of digital image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the degradation of the S/N ratio when a predictive coding operation is used and to reduce a block strain when DCT is used in a fallback model. SOLUTION: An error correction decoder 51 recieves image data which is transmitted from a digital-image transmitting apparatus, and it executes an error-correction processing operation to the received image data. A D/A conversion part 90 converts the image data from the decoder 51 into an image signal. A mode judgment circuit 60 detects a mode in the transmission on the basis of the received image data, and it controls a clock so as to agree with a sampling frequency in the transmission on the basis of a detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image receiving apparatus and a digital image receiving method.

[0002]

2. Description of the Related Art In a digital image transmission system in which a video signal is converted into a digital signal and transmitted as image data, an error correction code is added to image data or audio data in order to correct a data error in a transmission line. It is common to transmit.

[0003] When the quality of the transmission path is lower than the normal state, a fallback mode in which the amount of data for image data and audio data is reduced and the reduced amount of data is allocated to an error correction code to enhance error correction capability. And have been adopted in various digital image transmission systems.

Specifically, after a video signal is sampled (sampled) by a sampling clock having a predetermined frequency and converted into a digital signal, the obtained image data is subjected to, for example, predictive coding or discrete cosine transform (hereinafter, DCT: Discrete). cos
ine Transfom), variable-length coding such as Huffman coding and run-length coding, and data processing such as addition of an encoder correction code. In the fallback mode, the quantization width (quantization step) of quantization in high-efficiency coding is used.
And collect the quantized data in the vicinity of 0 to reduce the data amount per sample (one pixel) after variable length coding, and allocate the reduced data amount to the error correction code. It is designed to be transmitted.

[0005]

As described above, in the conventional digital image transmission system, since the quantization step of the high-efficiency coding is increased in the fallback mode and transmitted, for example, predictive coding is adopted. In such a system, there is a problem that a so-called S / N (Signal to Noise ratio) is deteriorated, and in a system adopting DCT, so-called block distortion becomes noticeable.

The present invention has been made in view of the above circumstances, and in the fallback mode, for example, a digital image that can reduce S / N degradation when using predictive coding and block distortion when using DCT is used. It is an object of the present invention to provide a receiving apparatus and a digital image receiving method.

[0007]

In order to achieve the above object, a digital image receiving apparatus according to the present invention receives image data transmitted from a digital image transmitting apparatus,
Error correction means for performing error correction processing on the received image data, digital / analog conversion means for converting the image data from the error correction means into a video signal, and a mode for transmission based on the received image data. Control means for detecting and controlling the clock so as to match the sampling frequency at the time of transmission based on the detection result.

A digital image receiving method according to the present invention receives image data transmitted from a digital image transmitting device, performs error correction processing on the received image data, and performs error correction processing on the image data. Is converted to a video signal, a mode at the time of transmission is detected based on the received image data, and a clock is controlled so as to match a sampling frequency at the time of transmission based on a detection result.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital image receiving apparatus and a digital image receiving method according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a digital image transmitting apparatus to which the present invention is applied, and FIG. 5 is a block diagram showing a circuit configuration of a digital image receiving apparatus to which the present invention is applied. That is, a digital image transmission system according to the present invention comprises the above digital image transmitting device and digital image receiving device.

First, a digital image transmitting apparatus will be described. As shown in FIG. 1, this digital image transmitting apparatus samples an image signal to generate image data, and an analog / digital (hereinafter referred to as A / D) conversion circuit 20; A time axis correction circuit (hereinafter, TBC: Time BaseCor) that corrects the time axis of data
rector) 11 and a sub-sampling circuit 1 for so-called sub-sampling of luminance data from the TBC 11
And 2 _Y, and the sub-sampling circuit 12 _C for sampling the color difference data from the TBC11, the changeover switch 13 to the chrominance data of two series from the subsampling circuit 12 _C line sequential, from the subsampling circuit 12 _Y A motion detection circuit 14 for detecting a motion based on the luminance data of the sub-sampling circuit 12 _Y
An encoding circuit 30 _Y for coding by the high efficiency coding the luminance data from the encoding circuit 30 for encoding by high efficiency encoding chrominance data from the changeover switch 13
And _C, and a multiplexer (hereinafter referred to as MUX 15) for multiplexing the encoded data, etc. to the luminance data and chrominance data from the encoding circuit ₃₀ Y, _{30 C,} the MUX
A variable length coding circuit (hereinafter referred to as V) which generates variable length code data by performing variable length coding on the multiplexed code data from
LC) 16, a buffer memory 17 for temporarily storing the variable length code data from the VLC 16, and an error correction encoder 18 for adding an error correction code to the variable length code data read from the buffer memory 17 and transmitting the same.
And

The digital image transmitting apparatus is
For example, video signals supplied as a luminance signal (Y) and a color difference signal (RY, BY) have different frequencies in two modes: a normal mode and a fallback mode when the quality of a transmission path is deteriorated. After converting to a digital signal using the sampling clock of, for example, sub-sampling,
So-called predictive coding and discrete cosine transform (hereinafter DCT: Discrete
Cosine Transfom) and data processing such as variable-length coding such as Huffman coding and run-length coding, and an error correction code is added for transmission.

More specifically, as shown in FIG. 2, for example, the A / D conversion circuit 20 is a low-pass filter (hereinafter referred to as an LPF) which is a pre-filter for converting a luminance signal and a color difference signal into digital signals. _21Y , _21R ,
21 and _B, the LPF 21 _{Y, 21} R, 21 filtered luminance signal at _B, and respectively sample the color difference signals, A / D converter 2 for generating luminance data, color difference data
2 _Y , 22 _R , 22 _B , an oscillator 23 for generating a sampling clock, a frequency divider 24 for dividing the clock from the oscillator 23 by two, and a divider for dividing the clock from the oscillator 23 by three Frequency divider 25 and the frequency dividers 24, 2
Switch 2 for switching and selecting each clock from 5
6 and a frequency divider 27 for dividing the clock selected by the changeover switch 26 by two.

The oscillator 23 generates a 27 MHz clock, for example, and the frequency divider 24 divides the clock by 2 to generate a 13.5 (= 27．2) MHz clock.
The frequency divider 25 divides the frequency by 3 to generate a clock of 9 (= 27/3) MHz.

A changeover switch 26 is a controller (not shown) for controlling a normal mode, a fallback mode, and the like.
Operates in response to a mode switching signal supplied from the frequency divider 24. In the normal mode, the 13.5 MHz clock from the frequency divider 24 is selected. In the fallback mode, the 9 MHz clock from the frequency divider 25 is selected.
Select the clock, and supplies the A / D converter 22 _Y was selected clock as the sampling clock.

On the other hand, the frequency divider 27 divides the frequency of the clock selected by the changeover switch 26 by two, and in the normal mode, the frequency divider 6.7.
A clock of 75 (= 13.5 ÷ 2) MHz is generated, and a clock of 4.5 (= 9 ÷ 2) MHz is generated in the fallback mode, and the generated clock is used as a sampling clock to A / D converters 22 _R and 22 _{R. B.}

Thus, the A / D conversion circuit 20 has
In the normal mode, the number of samples (number of pixels) per line is 72 for each of the luminance signal and the two series of color difference signals.
0 and 360, and 480 and 240 in the fallback mode, respectively. That is, in the fallback mode, the number of samples is 2/3 of that in the normal mode.
It has become. By the way, switching between the normal mode and the fallback mode is performed, for example, in a digital image receiving apparatus described later, where the quality of the transmission path, for example, the so-called error rate is detected to deteriorate the error rate, or the image quality is observed by observing the reproduced image. When deterioration occurs, the switching to the fallback mode is notified using a meeting line such as a telephone line, and the transmission side manually performs the switching. Further, for example, when this digital image transmitting apparatus is applied to satellite communication, a signal transmitted by its own station may be received to detect the quality of the transmission path, and the digital image transmitting apparatus may automatically perform the transmission based on the detection result. .

The luminance data and chrominance data thus obtained are supplied to the TBC 11. TBC11
Is composed of, for example, a so-called frame memory, and includes luminance data,
After temporarily storing the color difference data, the luminance data and the color difference data are read out by another stable clock. That is, when a video signal (luminance signal, color difference signal) that deviates from the standard television signal standard is input,
Even when video signals that are not synchronized with each other are switched and input, the sub-sampling circuits 12 _Y and 12 _C connected to the subsequent stage of the TBC 11 can be operated stably. And T
Luminance data read from the BC11 is supplied to the sub-sampling circuit 12 _Y, chrominance data is supplied to the sub-sampling circuit 12 _C.

The sub-sampling circuit 12 _Y is thinned out luminance data to 1/2, the sampling frequency in the normal mode becomes 6.75 MHz, the fallback mode to generate the luminance data to be 4.5 MHz.

On the other hand, the sub-sampling circuit 12 _C
Each of the two series of color difference data is thinned out to １ ／ to generate two series of color difference data whose sampling frequency is 3.375 MHz in the normal mode and 2.25 MHz in the fallback mode.

In other words, the sub-sampling circuit 12 _Y
From the above, the number of samples per line is 360 in the normal mode and 2 in the fallback mode.
Is output luminance data is 40 samples, from the subsampling circuit 12 _C, the number of samples per line is 180 samples in the normal mode, is output two series of color difference data is 120 samples in fallback mode . The luminance data thus sub-sampled is supplied to the encoding circuit _30Y and the motion detection circuit 14, and the color difference data is supplied to the changeover switch 13
Supplied to

The changeover switch 13 performs the data processing for the color difference data of the two series line-sequential supplies the resulting color-difference data to the encoding circuit 30 _C. Specifically, the changeover switch 13 alternately selects and outputs the color difference data (RY) of the odd line and the color difference data (BY) of the even line.

The motion detection circuit 14 performs motion detection using the luminance data supplied from the sub-sampling circuit 12 _Y, to detect an optimum so-called motion vector coding circuit the motion vector 30 _Y, 30 _C and Supply to MUX15. For example, the data generation amount of code data outputted from the encoding circuit 30 _Y, 30 _C detects the optimum motion vector that minimizes.

The coding circuits 30 _Y and 30 _C have the same circuit configuration (hereinafter referred to as the coding circuit 30), and comprise, for example, a feedback type predictive coding circuit.
As shown in, an adder 31 for calculating a prediction error by subtracting the predicted values from the color difference data (hereinafter referred to simply as a pixel value) from the luminance data or changeover switch 13 from the subsampling circuit 12 _Y, the adder A quantizer 32 that quantizes the prediction error from the reference 31 by a predetermined quantization and outputs code data, and an inverse quantizer that dequantizes the code data from the quantizer 32 and reproduces the prediction error 33
And an adder 34 for adding a prediction value to the prediction error from the inverse quantizer 33 to reproduce a pixel value, based on the pixel value from the adder 34 and the motion vector from the motion detection circuit 14. A prediction function circuit 35 for selecting a prediction function and generating a predicted value.

The prediction function circuit 35 includes an intra-field prediction function such as so-called pre-prediction or one-line prediction, an inter-field prediction function such as using lines above and below the previous field, and an inter-frame prediction function such as so-called motion compensation prediction. It has a prediction function and, based on the pixel value (hereinafter referred to as the previous pixel value) from the adder 34 and the motion vector from the motion detection circuit 14, selects an optimal prediction function (hereinafter referred to as an operation mode) from these.
Is selected for each pixel, and the obtained predicted value is supplied to the adder 31.

Each time a new pixel value (hereinafter referred to as a current pixel value) is supplied, the adder 31 subtracts a prediction value from the current pixel value to obtain a prediction error.

The quantizer 32 has, for example, a plurality of quantization widths (quantization steps), and has a predetermined quantization, for example, the amount of data generation is equal to or less than a predetermined value and is maximum, and a small value is finely quantized. The prediction error is quantized by non-linear quantization for coarsely quantizing a large value to generate code data, and this code data is output. The quantization step of the quantizer 32 is controlled by the controller based on, for example, the so-called buffer occupancy of the buffer memory 17.

The inverse quantizer 33 inversely quantizes the code data supplied from the quantizer 32 to reproduce a prediction error.
This prediction error is supplied to the adder 34.

The adder 34 calculates the prediction error and the prediction function circuit 3
5 to reproduce the pixel value corresponding to the current pixel value input to the adder 31, and to calculate the pixel value before the calculation for the prediction value for the next pixel value. It is supplied to the prediction function circuit 35 as a pixel value.

[0029] Thus, the encoding circuit 30 _Y generates the code data for the luminance data, the encoding circuit 30 _C generates the code data for the color difference data, these code data are supplied to the MUX 15.

The high-efficiency encoding of the encoding circuit 30 may be, for example, DCT in addition to the above-mentioned predictive encoding. Specifically, for example, an encoding circuit employing DCT divides the image data into blocks of, for example, 8 × 8 pixels (samples) in a spatial arrangement as shown in FIG. 4 and cut out from the current frame. An adder 41 for obtaining difference data between image data of a block (hereinafter referred to as current block data) and image data of a block cut out from a previous frame subjected to motion compensation (hereinafter referred to as previous block data); A changeover switch 42 for switching and selecting the difference data from the current data and the current block data;
A discrete cosine transform circuit (hereinafter referred to as a DCT circuit) 43 for performing a discrete cosine transform on the output of the changeover switch 42; a DCT output data from the DCT circuit 43 is quantized by a predetermined quantization to output code data; An inverse quantizer 45 for inversely quantizing the code data from the quantizer 44 to reproduce DCT output data; and an inverse quantizer 4
An inverse discrete cosine transform circuit (hereinafter referred to as an IDCT circuit) 46 for performing an inverse discrete cosine transform of the DCT output data from
An adder 47 for adding the previous block data to the difference data from the DCT circuit 46 to reproduce the current block data; and an adder 47 for adding the current block data from the IDCT circuit 46 to the current block data.
A changeover switch 48 for switching and selecting the current block data from the current block data and a motion vector and the like from the motion detection circuit 14 are subjected to motion compensation on the current block data from the changeover switch 48. And a motion compensation circuit 49 for converting data.

The encoding circuit has three operation modes, for example, an intra-field mode, an inter-field mode, and an inter-frame mode, and based on the motion vector supplied from the motion detection circuit 14, Select the pixel value (luminance data or color difference data) in the field in the intra-field mode, select the inter-field prediction error value of the pixel in the inter-field mode, and select the motion compensation inter-frame prediction error value of the pixel in the inter-frame mode. Then, block data composed of 8 × 8 pixels is subjected to two-dimensional discrete cosine transform, and the obtained DCT output data is quantized and output.

That is, the motion detection circuit 14
An optimum motion vector that minimizes the sum of absolute values of difference data for each pixel between block data to be compared is detected by so-called block matching within or between frames.

Each time the current block data is supplied, the adder 41 calculates a motion compensation circuit 49 from the current block data.
Is subtracted on a pixel-by-pixel basis from the motion-compensated previous block data supplied from, to obtain difference data of 8 × 8 pixels.

The changeover switch 42 is controlled by, for example, the above-described controller based on the motion vector from the motion detection circuit 14, the occupancy of the buffer memory 17, and the like. In the mode, the mode is switched to the INTER side, and the current block data, which is the pixel value in the field, and
It switches and selects the difference data from the adder 41, which is the inter-field prediction error value or the motion compensation inter-frame prediction error value, and outputs it.

The DCT circuit 43 converts the current block data selected by the changeover switch 42 or the difference data supplied from the adder 41 in block units into a discrete cosine transform,
DCT output data of × 8 coefficient is generated and supplied to the quantizer 44.

The quantizer 44 has a plurality of quantization steps, and quantizes the DCT output data supplied from the DCT circuit 43 to a predetermined value. The so-called low-frequency component is quantized with a large weight, that is, the low-frequency component is finely quantized, and the obtained code data is dequantized by the inverse quantizer 45 and M
UX15. The quantization step of the quantizer 44 is controlled by the controller based on, for example, the so-called buffer occupancy of the buffer memory 17.

The inverse quantizer 45 inversely quantizes the code data and converts the obtained DCT output data of 8 × 8 coefficients into IDCT data.
The signal is supplied to a circuit 46.

The IDCT circuit 46 performs an inverse discrete cosine transform of the DCT output data.
The block data corresponding to the current block data input to 1 is reproduced, and the difference data is reproduced in the inter-field mode and the inter-frame mode.

The adder 47 adds the difference data supplied from the IDCT circuit 46 and the motion-compensated previous block data supplied from the motion compensation circuit 49, and
And reproduces the block data corresponding to the current block data input to.

The changeover switch 48 is linked to the changeover switch 42, and selects the block data reproduced by the IDCT circuit 46 or the adder 47.

The motion compensating circuit 49 includes, for example, a frame memory. The motion compensating circuit 49 performs motion compensation on the block data supplied via the changeover switch 48 based on the motion vector from the motion detecting circuit 14, and obtains the obtained motion compensated data. When the block data of the next frame is input to the adder 41, the stored frame data is supplied to the adder 41 and the motion detection circuit 14 as the previous frame data.

[0042] Thus, the encoding circuit 30 _Y generates the code data for the luminance data, the encoding circuit 30 _C generates the code data for the color difference data, these code data are supplied to the MUX 15.

The MUX 15 includes encoding circuits 30 _Y , 30
_The motion vector supplied from the motion detection circuit 14 and the control data, which is information on the quantization step and the operation mode, are multiplexed with the respective code data for the luminance data and the color difference data supplied from _C , and the motion vector and the like are multiplexed. The converted code data is supplied to the VLC 16.

The VLC 16 performs, for example, so-called Huffman coding and run-length coding on the code data to generate variable-length code data.

The buffer memory 17 temporarily stores the variable-length code data supplied from the VLC 16, reads out the stored variable-length code data after smoothing it, and supplies the variable-length code data at a constant rate to the error correction encoder 18. .

The error correction encoder 18 comprises, for example, an encoder using a so-called convolutional code, and has a different error correction code amount assignment between the normal mode and the fallback mode. In addition, an error correction code having a large error correction code amount is added to the variable length code data. That is, the error correction encoder 18 has a coding rule of a normal mode and a coding rule of a fallback mode having a large error correction code amount and a high error correction capability. More specifically, the error correction encoder 18 sets the transmission rate to 22 Mbps, assigns 25% to the error correction code in the normal mode, and sets the transmission rate for variable-length code data to 16.5.
(= 22 × 0.75) Mbps, and an error correction code having an error correction code amount of 5.5 (= 22 × 0.25) Mbps converted to the transmission rate is added. On the other hand, in the fallback mode, if 50% is allocated to enhance the error correction capability, the transmission rate for variable-length code data is 11 (= 22).
× 0.5) Mbps, and an error correction code whose error correction code amount is 11 Mbps in transmission rate is added. Then, the variable-length code data to which the error correction code has been added in this manner is transmitted via a transmission path having the same transmission rate in the normal mode and the fallback mode.

Therefore, for example, the frame period is reduced to 1/3
Assuming that the time is 0 second and the number of lines is 496, in the normal mode, the number of samples per line for luminance data is 360 and the number of samples for color difference data is 180 as described above. The quantization step in the quantizer 32 or the quantizer 44 shown in FIG.
The average number of bits per sample is a value corresponding to 2.05 bits / sample. On the other hand, in the fallback mode, as described above, the number of samples in the horizontal direction for the luminance data is 240, and
Since there are 20 samples, the quantization step is a value corresponding to an average number of bits per sample converted to a transmission path of 2.05 bits / sample, as shown in Expression 2 below.

By the way, in the conventional apparatus, since the sampling frequency is not changed in the fallback mode, the quantization step is performed by calculating the average number of bits per sample converted to the transmission path as shown in the following equation 3. This is a value corresponding to 1.37 bits / sample. That is, in the digital image transmitting apparatus, in the fallback mode, by setting the sampling frequency to ／ of the normal mode as described above, the average number of bits per sample can be set to the same value as in the normal mode. In the above-described predictive coding, so-called S / N (Signal to No
iset ratio), and DCT can prevent the occurrence of so-called block distortion. The error correction method may be, for example, error correction using a block code or the like.

Average number of bits = 16.5 × 10 ⁶ / ((360 + 180) × 496 × 30) Expression 1 = 2.05 Average number of bits = 11 × 10 ⁶ / ((240 + 120) × 496 × 30) Equation 2 = 2.05 Average number of bits = 11 x 10 ⁶ / ((360 + 180) x 496 x 30) Equation 3 = 1.37 Next, the digital image receiving apparatus will be described.

As shown in FIG. 5, the digital image receiving apparatus includes an error correction decoder 51 for performing error correction processing on received image data, that is, variable length code data.
A mode determination circuit 60 for detecting a mode at the time of transmission based on variable-length code data and controlling a clock frequency of a digital / analog (hereinafter, referred to as D / A) conversion circuit 90 described later; A variable length decoding circuit (hereinafter referred to as VLD) 53 for temporarily storing the variable length code data from the buffer memory 52 and reproducing the code data by performing variable length decoding on the variable length code data from the buffer memory 52; A demultiplexer (hereinafter referred to as DMUX) 54 for separating the code data from the VLD 53 into code data for luminance data and color difference data.
If, to the code data for the separated luminance data in the DMUX54, a decoding circuit 70 _Y for performing decoding corresponding to the encoding during transmission, the code data for the separated chrominance data in the above DMUX54, the transmission a decoding circuit 70 _C for performing decoding corresponding to coding at the time, and the vertical interpolation circuit 55 for interpolating the chrominance data reproduced by該復Goka circuit 70 _C in the vertical direction, the decoding circuit 70 _Y
A horizontal interpolation circuit 56 _Y for interpolating the reproduced luminance data in the horizontal direction in a horizontal interpolation circuit 56 _C for interpolation processing in the horizontal direction color difference data from the vertical interpolation circuit 55,
A frame synchronizer 57 for synchronizing the luminance data and color difference data from the horizontal interpolation circuits 56 _Y and 56 _C with an external device, and converting the luminance data and color difference data from the frame synchronizer 57 into analog signals, and converting the original video signal. And the D / A conversion circuit 90 for reproducing.

And, this digital image receiving apparatus
The received image data, that is, the mode at the time of transmission based on the variable length code data is detected whether the normal mode or the fallback mode, and while performing error correction processing corresponding to the mode detected in the variable length code data, After the error-corrected variable-length code data is subjected to data processing such as decoding corresponding to variable-length coding at the time of transmission, coding corresponding to high-efficiency coding, and interpolation processing to reproduce image data,
The image data is converted into an analog signal by a clock corresponding to a sampling frequency at the time of transmission and output.

Specifically, the error correction decoder 51
The decoder includes a decoder corresponding to the error correction encoder 18 shown in FIG. 1 described above. The mode is switched between the normal mode and the fallback mode by the mode switching signal from the mode determination circuit 60, and based on the coding rule corresponding to the switched mode. Error correction of variable-length code data is performed, and an error state of data corresponding to, for example, a synchronization signal is detected. If an error occurs, an error flag is set (1).
Is supplied to the mode determination circuit 60.

The mode determination circuit 60 is cleared by an oscillator 61 for generating a predetermined clock and an error flag from the error correction decoder 51 and counts the clock from the oscillator 61 as shown in FIG. And a D-type flip-flop (hereinafter, referred to as D-FF) 63 that operates using the output of the counter 62 as a clock.

[0054] For example, as shown in FIG. 7A, at time t _1, a digital image transmission apparatus, for example when switching from the normal mode to the fallback mode, since the code rule is different, as shown in FIG. 7B, The error flag is set with a certain delay. Counter 62
Is cleared when the error flag is in the reset state (0), and when the error flag is in the set state, the oscillator 61
7D (FIG. 7C).
, The clock is divided by two, divided by four, divided by eight,.
..Output the signal. D-FF 63, for example operates at the rising edge of the divide-by-8 output of the counter 62 (QC), as shown in FIG. 7E, a 1 at time t ₂ to time T ₁ since the error flag gusset has elapsed mode The switching signal is supplied to the error correction decoder 51, the D / A conversion circuit 90, and the like.

The error correction decoder 51 switches to a mode different from the current operation mode, for example, from the normal mode to the fallback mode by the mode switching signal, and starts an error correction process with a high error correction capability.
As a result, as shown in FIG. 7B, the error flag is reset from time t ₂ to a predetermined time T ₂ has elapsed time t _3. Meanwhile, without immediately mode switching since the error flag is set by the mode switching after a time T ₁ has elapsed, at the time when the error flag is set due to an error or the like of the transmission line without changing the transmission mode, Unnecessary mode switching can be prevented.

The error-corrected variable-length code data is temporarily stored in the buffer memory 52. V
The LD 53 decodes the variable-length code data read from the buffer memory 52 to reproduce the code data, and supplies the code data to the DMUX 54.

The DMUX 54 converts the code data from the VLD 53 into code data corresponding to luminance data, code data corresponding to chrominance data, a motion vector, a quantization step,
Separating the control data which is information of the operation mode, the decoding circuit 70 _Y luminance data, and supplies the color difference data to the decoding circuit 70 _C, a motion vector,
Quantization step, control data decoding circuit 70
_Y, and supplies the 70 _C.

The decoding circuits 70 _Y and 70 _C have the same circuit configuration (hereinafter referred to as the decoding circuit 70), and comprise, for example, a decoding circuit corresponding to the predictive coding circuit shown in FIG. As shown in FIG. 8, an inverse quantizer 71 for inversely quantizing the code data from the DMUX 54 to reproduce a prediction error, and adding a prediction value to the prediction error from the inverse quantizer 71 to obtain a pixel value And a prediction function circuit 73 for generating a predicted value.

Then, the inverse quantizer 71 inversely quantizes the code data using the received quantization step, and supplies the obtained prediction error to the adder 72.

The adder 72 calculates the prediction error and the prediction function circuit 7
3 to reproduce a pixel value (luminance data or color difference data) by adding the predicted value supplied from 3 and output this pixel value.

The prediction function circuit 73 has an intra-field prediction function, an inter-field prediction function, and an inter-frame prediction function, like the prediction function circuit 35 shown in FIG.
The operation mode at the time of transmission is detected based on the control data supplied from the UX 54, a prediction function for the detected operation mode is selected, and the pixel value supplied from the adder 72 and the motion vector supplied from the DMUX 54 A predicted value is generated on the basis of
Feed to 2.

[0062] Thus, the decoding circuit 70 _Y reproduces the luminance data, the decoding circuit 70 _C reproduces the color difference data.

The decoding of the decoding circuit 70 is as follows.
In addition to decoding corresponding to the above-described predictive coding, for example, ID
CT or the like may be used. Specifically, for example, a decoding circuit adopting the IDCT, for example, as shown in FIG.
An inverse quantizer 81 for inversely quantizing the code data from the MUX 54 to reproduce DCT output data;
IDC for inverse discrete cosine transform of DCT output data from 1
A T circuit 82; an adder 83 that adds the previous block data to the difference data reproduced by the IDCT circuit 82 to reproduce block data; and a block data from the IDCT circuit 82 and the block data from the adder 83 Based on the changeover switch 84 for selecting the changeover and the motion vector from the DMUX 54, the block data supplied through the changeover switch 84 is subjected to motion compensation, and the obtained block data is added to the adder 83 as the previous block data.
And a motion compensating circuit 85 for supplying the motion compensation signal to the first stage.

The decoding circuit has three operation modes, an intra-field mode, an inter-field mode, and an inter-frame mode, corresponding to the encoding circuit shown in FIG. An operation mode at the time of transmission is detected based on the data, and DCT output data is subjected to data processing such as inverse quantization and inverse discrete cosine transform in accordance with the detected operation mode to reproduce block data. .

That is, the inverse quantizer 81 outputs the DMUX5
4 is inversely quantized based on the quantization step supplied from the DMUX 54, and the obtained 8 × 8 coefficient DCT output data is supplied to the IDCT circuit 82.

The IDCT circuit 82 performs an inverse discrete cosine transform of the DCT output data, reproduces block data (luminance data or chrominance data) in the intra-field mode, and inter-field prediction error value or motion in the inter-field mode and the inter-frame mode. The difference data, which is the inter-compensation frame prediction error value, is reproduced.

The adder 83 adds the difference data reproduced by the IDCT circuit 82 and the previous block data which has been motion-compensated and supplied from the motion compensation circuit 85 to reproduce block data (luminance data or color difference data). I do.

The changeover switch 84 is controlled according to the operation mode, and is set to the INTRA side in the intra-field mode, and to the INTER in the inter-field mode and the inter-frame mode.
Side, and the IDCT circuit 82 or the adder 83
And outputs the selected block data.

The motion compensation circuit 85 includes, for example, a frame memory, and performs motion compensation on the block data supplied via the changeover switch 84 based on the motion vector supplied from the DMUX 54, and converts the obtained block data into the previous block. The data is supplied to the adder 83 as data.

[0070] Thus, the decoding circuit 70 _Y reproduces the luminance data, the decoding circuit 70 _C reproduces the color difference data.

The horizontal interpolation circuit 56 _Y includes a decoding circuit 70
By interpolating the luminance data supplied from _Y on the line, the luminance data thinned out at the time of transmission is reproduced, and the sampling frequency is 6.75 MHz in the normal mode.
In the fallback mode, luminance data having a frequency of 4.5 MHz is reproduced.

The vertical interpolation circuit 55 has a decoding circuit 70 _C
By interpolating the chrominance data supplied line-sequentially between the lines, the two-series chrominance data is reproduced over all the lines.

The horizontal complement circuit 56 _C is provided with a vertical interpolation circuit 55.
The color difference data supplied from is interpolated on the line to reproduce the color difference data thinned out at the time of transmission,
The sampling frequency is 3.375 MHz in the normal mode and 2.25 MHz in the fallback mode.
Generates color difference data for a series.

The frame synchronizer 57 temporarily stores the luminance data and color difference data supplied from the horizontal interpolation circuits 56 _Y and 56 _C , respectively, and supplies an external device (not shown) for supplying a video signal reproduced by the digital image receiving apparatus. ), And supplies the read luminance data and color difference data to the D / A conversion circuit 90.

As shown in FIG. 10, for example, the D / A conversion circuit 90 converts D / A converters 91 _Y and 91 _{R for} converting the luminance data and the two-series color difference data from the frame synchronizer 57 into video signals, respectively. , 91 _B and the D
LPFs 92 _Y , 92 _R , 92 _B for respectively filtering the video signals from the / A converters 91 _Y , 91 _R , 91 _B ;
An oscillator 93 for generating the clocks of the D / A converters 91 _Y , 91 _R , and 91 _B , a frequency divider 94 for dividing the clock from the oscillator 93 by two, and a clock from the oscillator 93 for three A frequency divider 95 for frequency division and the frequency divider 9
A switch 96 for switching and selecting each clock from the clocks 4 and 95 and a frequency divider 97 for dividing the clock selected by the switch 96 into two.

The oscillator 93 generates a clock of, for example, 27 MHz, and the frequency divider 94 divides the frequency of the clock by 2 to generate a clock of 13.5 (= 27 ÷ 2) MHz.
The frequency divider 95 divides the frequency by 3 to generate a clock of 9 (= 27/3) MHz.

The changeover switch 96 is connected to the mode determination circuit 60
Operates in accordance with the mode switching signal from the first mode, selects a 13.5 MHz clock from the frequency divider 94 in the normal mode,
In fallback mode select of 9MHz from the frequency divider 95 a clock, and supplies the D / A converter 91 _Y was selected as the clock corresponding to the sampling clock of the A / D converter.

On the other hand, the frequency divider 97 divides the frequency of the clock selected by the changeover switch 96 by two, and in the normal mode, the frequency divider 6.7.
A clock of 75 (= 13.5 ÷ 2) MHz is generated, and a clock of 4.5 (= 9 ÷ 2) MHz is generated in the fallback mode, and the generated clock is converted to the D / A converters 91 _R and 91 _R.
Supplied to the 1 _B.

D / A converter 91_Y And LPF92_Y 
Uses the clock supplied from the changeover switch 96
The luminance data supplied from the frame synchronizer 57.
Data is converted to an analog signal and the luminance signal (Y) is reproduced.
And the D / A converter 91_R , 91 _B And LPF92
_R , 92_B Is the clock supplied from the frequency divider 97.
To convert two sets of color difference data into analog signals
After conversion, the color difference signals (RY, BY) are reproduced.

Thus, the D / A conversion circuit 90 has
The number of samples (the number of pixels) per line is set to 720 and 360 in the normal mode, and the luminance data and chrominance data set to 480 and 240 in the fallback mode are converted into analog signals. Output to external device.

As described above, in the digital image transmitting apparatus, when the video signal is sampled, converted to image data and transmitted, the fallback mode when the quality of the transmission path is deteriorated is lower than that in the normal mode. In addition, the sampling frequency of the A / D conversion circuit 20 is lowered, and the error correction code to be added by the error correction encoder 18 is transmitted with an increased code amount. At the time of conversion into a video signal by the A conversion circuit 90 and output, the mode at the time of transmission is detected based on the image data, and the D / A
By controlling the clock of the conversion circuit 90 to match the sampling frequency at the time of transmission, the average number of bits per sample can be set to the same value as in the normal mode. For example, in a system using predictive coding, S / N
Can be prevented. For example, in a system employing DCT, occurrence of block distortion can be prevented. Further, the digital image receiving apparatus can automatically switch between the normal mode and the fallback mode.

The present invention is not limited to the above-described embodiment. For example, A / D converters 91 _Y and 91 _Y
Instead of changing the sampling frequency of the _R, 91 _B, as well as slower than the read cycle from TBC11 in fallback mode to the normal mode may be read out by thinning. Further, the sub-sampling circuits 12 _Y and 12 _Y in the fallback mode
The thinning rate at _C may be made larger than that in the normal mode. In addition, as the encoding, in addition to the above-described predictive encoding and DCT, for example, transform encoding such as so-called slant transform and Haar transform can be used.

[0083]

As is apparent from the above description, according to the present invention, in a digital image transmitting apparatus, when a video signal is sampled, converted into image data and transmitted, a fallback mode is usually used. The sampling frequency of the analog / digital conversion means is lowered compared to the mode, and the error correction code amount is increased and transmitted.
In a digital image receiving apparatus, when converting received image data into a video signal and outputting the video signal, a mode at the time of transmission is detected based on the image data, and a clock of the digital / analog conversion means is controlled based on the detection result. By doing so, the average number of bits per sample can be set to the same value as in the normal mode. For example, in a system employing predictive coding, deterioration of S / N can be prevented,
Further, for example, in a system employing DCT, occurrence of block distortion can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a digital image transmission device to which the present invention has been applied.

FIG. 2 shows an A / D constituting the digital image transmitting apparatus.
FIG. 3 is a block diagram illustrating a specific circuit configuration of a conversion circuit.

FIG. 3 is a block diagram showing a specific circuit configuration of an encoding circuit constituting the digital image transmission device.

FIG. 4 is a block diagram showing another specific circuit configuration of the encoding circuit constituting the digital image transmission device.

FIG. 5 is a block diagram showing a circuit configuration of a digital image receiving apparatus to which the present invention has been applied.

FIG. 6 is a block diagram showing a specific circuit configuration of a mode determination circuit constituting the digital image receiving device.

FIG. 7 is a time chart for explaining the operation of the mode determination circuit.

FIG. 8 is a block diagram showing a specific circuit configuration of a decoding circuit constituting the digital image receiving device.

FIG. 9 is a block diagram showing another specific circuit configuration of the decoding circuit constituting the digital image receiving device.

FIG. 10 shows a D / D constituting the digital image receiving apparatus.
FIG. 3 is a block diagram illustrating a specific circuit configuration of an A conversion circuit.

[Explanation of symbols]

51 error correction decoder, 52 buffer memory, 5
3 VLD, 54 DMUX, 55 Vertical correction circuit, 5
6 horizontal interpolation circuit, 57 frame synchronizer, 6
0 mode determination circuit, 70 decoding circuit, 90 D / A
Conversion circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naohisa Kitasato F-term (reference) 5C059 KK03 LA01 LB01 MA02 MA03 MA05 MA23 MC11 ME01 NN01 PP16 RF05 UA09 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo UA12 5K014 AA01 BA05 DA01 EA08 FA11

Claims (2)

[Claims] 1. An error correction means for receiving image data transmitted from a digital image transmission device and performing error correction processing on the received image data, and a digital signal for converting the image data from the error correction means into a video signal. Digital image receiving / analog converting means, and control means for detecting a mode at the time of transmission based on received image data and controlling a clock so as to match a sampling frequency at the time of transmission based on the detection result. apparatus. 2. An image data transmitted from a digital image transmission device is received, an error correction process is performed on the received image data, and the image data subjected to the error correction process is converted into a video signal. A digital image receiving method for detecting a mode at the time of transmission based on the received image data and controlling a clock so as to match a sampling frequency at the time of transmission based on the detection result.