JP3227813B2 - Digital image transmission device, digital image transmission method, digital image transmission system, and digital image transmission / reception method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a digital image transmission device, a digital image transmission method, a digital image transmission system, and a digital image transmission / reception method.

[0002]

2. Description of the Related Art In a digital image transmission system in which a video signal is converted into a digital signal and transmitted as image data, an error correction code is added to image data or audio data in order to correct a data error in a transmission line. It is common to transmit.

[0003] When the quality of the transmission path is lower than the normal state, a fallback mode in which the amount of data for image data and audio data is reduced and the reduced amount of data is allocated to an error correction code to enhance error correction capability. And have been adopted in various digital image transmission systems.

Specifically, after a video signal is sampled (sampled) by a sampling clock having a predetermined frequency and converted into a digital signal, the obtained image data is subjected to, for example, predictive coding or discrete cosine transform (hereinafter, DCT: Discrete). cos
ine Transfom), variable-length coding such as Huffman coding and run-length coding, and data processing such as addition of an encoder correction code. In the fallback mode, the quantization width (quantization step) of quantization in high-efficiency coding is used.
And collect the quantized data in the vicinity of 0 to reduce the data amount per sample (one pixel) after variable length coding, and allocate the reduced data amount to the error correction code. It is designed to be transmitted.

[0005]

As described above, in the conventional digital image transmission system, since the quantization step of the high-efficiency coding is increased in the fallback mode and transmitted, for example, predictive coding is adopted. In such a system, there is a problem that a so-called S / N (Signal to Noise ratio) is deteriorated, and in a system adopting DCT, so-called block distortion becomes noticeable.

The present invention has been made in view of the above circumstances, and in the fallback mode, for example, a digital image that can reduce S / N degradation when using predictive coding and block distortion when using DCT is used. It is an object of the present invention to provide a transmission device, a digital image transmission method, a digital image transmission system, and a digital image transmission / reception method.

In order to achieve the above object, a digital image transmitting apparatus according to the present invention comprises: an analog / digital conversion means for converting a video signal into image data;
An error correction code adding unit for adding an error correction code to the image data from the digital conversion unit and transmitting the image data; a normal mode; and a fallback mode when the quality of the transmission path is deteriorated. When transmitting in the mode, the sampling frequency of the video signal is lowered compared to the normal mode, and the amount of error correction code added by the error correction code adding means is increased, so that the average number of bits per sample can be reduced. And control means for performing control so as to have the same value as the mode. Further, the digital image transmission method according to the present invention converts a video signal into image data, adds an error correction code to the converted image data, and transmits the converted image data when the quality of the transmission line is degraded. When transmitting in the fallback mode, the sampling frequency of the video signal is lowered compared to the normal mode, the amount of error correction code added to the image data is increased, and the average number of bits per sample is reduced in the normal mode. It is characterized by performing control so as to make the same value as the above and transmitting.

Further, the digital image transmission system according to the present invention provides an analog / digital converter for converting a video signal into image data.
There are digital conversion means, error correction code addition means for adding error correction codes to the image data from the analog / digital conversion means and transmitting the data, normal mode, and fallback mode when the quality of the transmission path is degraded. When the image data is transmitted in the fallback mode, the sampling frequency of the video signal is lowered and the amount of error correction code added by the error correction code adding means is increased in comparison with the normal mode. A digital image transmitting apparatus having control means for controlling the average number of bits per unit to have the same value as in the normal mode, and receiving image data transmitted from the digital image transmitting apparatus,
Error correction means for performing error correction processing on the received image data, digital / analog conversion means for converting the image data from the error correction means into a video signal, and a mode for transmission based on the received image data. And a control means for controlling the clock so as to match the sampling frequency at the time of transmission based on the detection result.

In the digital signal transmitting / receiving method according to the present invention, when a video signal is converted into image data and an error correction code is added to the converted image data to be transmitted, the quality of the transmission line of the image data deteriorates. When transmitting in the fallback mode, the sampling frequency of the video signal is lowered and the amount of error correction code added to the image data is increased, as compared with the normal mode, to reduce the average number of bits per sample. Control is performed so that the same value as in the normal mode is transmitted, and the transmitted image data is received.
Performs error correction processing on the received image data, converts the error-corrected image data into a video signal, detects the mode of transmission based on the received image data, and transmits based on the detection result. The clock is controlled so as to match the sampling frequency at the time of (1).

[0010]

In the digital image transmitting apparatus and the digital image transmitting method according to the present invention, when the video signal is sampled, converted to image data and transmitted, the fallback mode is used to convert the video signal compared to the normal mode. The transmission is performed with the sampling frequency lowered and the error correction code amount increased.

Further, in the digital image transmission system and the digital image transmission / reception method according to the present invention, when the video signal is sampled, converted into image data and transmitted, the fallback mode has a higher image quality than the normal mode. The signal sampling frequency is lowered and the error correction code amount is increased before transmission. Then, when converting the received image data into a video signal and outputting the video signal, a mode at the time of transmission is detected based on the image data, and a clock is set so as to match the sampling frequency at the time of transmission based on the detection result. Control.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital image transmitting apparatus, a digital image transmitting method, a digital image transmitting system and a digital image transmitting / receiving method according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a digital image transmitting apparatus to which the present invention is applied, and FIG. 5 is a block diagram showing a circuit configuration of a digital image receiving apparatus to which the present invention is applied. That is, a digital image transmission system according to the present invention comprises the above digital image transmitting device and digital image receiving device.

First, a digital image transmitting apparatus will be described. As shown in FIG. 1, this digital image transmitting apparatus samples an image signal to generate image data, and an analog / digital (hereinafter referred to as A / D) conversion circuit 20; A time axis correction circuit (hereinafter, TBC: Time BaseCor) that corrects the time axis of data
rector) 11, a sub-sampling circuit 12 for so-called sub-sampling of the luminance data from the TBC 11.
_Y , a sub-sampling circuit 12 _C for sampling the color difference data from the TBC 11, a changeover switch 13 for making the two series of color difference data from the sub-sampling circuit 12 _C line-sequential, and the sub-sampling circuit 12 _Y
Encoding circuit 30 for encoding the motion detection circuit 14 for detecting a motion on the basis of the luminance data, the luminance data from the subsampling circuit 12 _Y by the high efficiency coding from
Multiplexing and _Y, and the encoding circuit 30 _C for coding by the high efficiency coding the chrominance data from the changeover switch 13, the respective code data, etc. to the luminance data and chrominance data from the encoding circuit 30 _Y, 30 _C (Hereinafter, referred to as MUX 15), and a variable-length encoding circuit (hereinafter, referred to as VLC) 16 which performs variable-length encoding on multiplexed code data from the MUX 15 to generate variable-length encoded data.
A buffer memory 17 for temporarily storing the variable length code data from the VLC 16; and an error correction encoder 18 for adding an error correction code to the variable length code data read from the buffer memory 17 and transmitting the same.

This digital image transmitting apparatus has:
For example, video signals supplied as a luminance signal (Y) and a color difference signal (RY, BY) have different frequencies in two modes: a normal mode and a fallback mode when the quality of a transmission path is deteriorated. After converting to a digital signal using the sampling clock of, for example, sub-sampling,
So-called predictive coding and discrete cosine transform (hereinafter DCT: Discrete
Cosine Transfom) and data processing such as variable-length coding such as Huffman coding and run-length coding, and an error correction code is added for transmission.

Specifically, as shown in FIG. 2, for example, the A / D conversion circuit 20 is a low-pass filter (hereinafter referred to as LPF) which is a pre-filter for converting a luminance signal and a color difference signal into digital signals. 21 _Y , 21 _R , 2
And 1 _B, the LPF 21 _Y, 21 _R, 21 filtered luminance signal at _B, and respectively sample the color difference signals, the luminance data and generates color difference data A / D converter 22 _Y, 2
2 _R , 22 _B ; an oscillator 23 for generating a sampling clock; a frequency divider 24 for dividing the clock from the oscillator 23 by two;
A frequency divider 25 for dividing the frequency, a switch 26 for switching and selecting each clock from the frequency dividers 24 and 25, and a frequency divider 27 for dividing the clock selected by the switch 26 into two. Is done.

The oscillator 23 generates, for example, a 27 MHz clock, and the frequency divider 24 divides the clock by 2 to generate a 13.5 (= 27 ÷ 2) MHz clock.
The frequency divider 25 divides the frequency by 3 to generate a clock of 9 (= 27/3) MHz.

A changeover switch 26 is a controller (not shown) for controlling a normal mode, a fallback mode and the like.
Operates in response to a mode switching signal supplied from the frequency divider 24. In the normal mode, the 13.5 MHz clock from the frequency divider 24 is selected. In the fallback mode, the 9 MHz clock from the frequency divider 25 is selected.
Select the clock, and supplies the A / D converter 22 _Y was selected clock as the sampling clock.

On the other hand, the frequency divider 27 divides the frequency of the clock selected by the changeover switch 26 by two.
A clock of 75 (= 13.5 ÷ 2) MHz is generated, a clock of 4.5 (= 9 ÷ 2) MHz is generated in the fallback mode, and the generated clocks are used as sampling clocks for the A / D converters 22 _R and 22 _R. Supply to _B.

Thus, the A / D conversion circuit 20 has
In the normal mode, the number of samples (number of pixels) per line is 72 for each of the luminance signal and the two series of color difference signals.
0 and 360, and 480 and 240 in the fallback mode, respectively. That is, in the fallback mode, the number of samples is 2/3 of that in the normal mode.
It has become. By the way, switching between the normal mode and the fallback mode is performed, for example, in a digital image receiving apparatus described later, where the quality of the transmission path, for example, the so-called error rate is detected to deteriorate the error rate, or the image quality is observed by observing the reproduced image. When deterioration occurs, the switching to the fallback mode is notified using a meeting line such as a telephone line, and the transmission side manually performs the switching. Further, for example, when this digital image transmitting apparatus is applied to satellite communication, a signal transmitted by its own station may be received to detect the quality of the transmission path, and the digital image transmitting apparatus may automatically perform the transmission based on the detection result. .

Then, the luminance data thus obtained is obtained.
Data and color difference data are supplied to the TBC 11. TBC11
Is composed of, for example, a so-called frame memory, and includes luminance data,
After storing the color difference data once, switch to another stable clock.
More luminance data and color difference data are read.
You. That is, it deviates from the standard television signal standard.
When a video signal (luminance signal, color difference signal) is input,
Video signals that are not synchronized with each other are switched and input.
In the event that the TBC 11 is connected,
Sub-sampling circuit 12_Y, 12_CEtc.
It can be made to work. And TB
The luminance data read from C11 is sub-sampled
Circuit 12_YColor difference data is sub-sampled
Circuit 12 _CSupplied to

The sub-sampling circuit 12 _Y is thinned out luminance data to 1/2, the sampling frequency in the normal mode becomes 6.75 MHz, the fallback mode to generate the luminance data to be 4.5 MHz.

On the other hand, the sub-sampling circuit 12 _C
The color difference data of the series is thinned out to １ ／ each, and the sampling frequency becomes 3.375 MHz in the normal mode.
In the fallback mode, two series of color difference data of 2.25 MHz are generated.

In other words, the sub-sampling circuit 12 _Y
From the above, the number of samples per line is 360 in the normal mode and 24 in the fallback mode.
0 Sample a is the luminance data is output from the subsampling circuit 12 _C, the number of samples per line is 180 samples in the normal mode, is output two series of color difference data is 120 samples in fallback mode . The luminance data thus sub-sampled is supplied to the encoding circuit _30Y and the motion detection circuit 14, and the color difference data is supplied to the changeover switch 13.

The changeover switch 13 performs the data processing for the color difference data of the two series line-sequential supplies the resulting color-difference data to the encoding circuit 30 _C. Specifically, the changeover switch 13 alternately selects and outputs the color difference data (RY) of the odd line and the color difference data (BY) of the even line.

The motion detection circuit 14 performs the sub-sampling
Road 12_YMotion detection using luminance data supplied from
To detect the optimal so-called motion vector,
Tor encoding circuit 30_Y, 30_CAnd supply to MUX15
I do. For example, the encoding circuit 30 _Y, 30_COutput from
Optimal operation that minimizes the amount of code data generated
Vector.

The coding circuits 30 _Y and 30 _C have the same circuit configuration (hereinafter referred to as the coding circuit 30), and are composed of, for example, a feedback type predictive coding circuit, and as shown in FIG. An adder 31 for calculating a prediction error by subtracting a prediction value from luminance data from the sampling circuit 12 _Y or chrominance data (hereinafter simply referred to as a pixel value) from the changeover switch 13, and determining a prediction error from the adder 31 A quantizer 32 that quantizes the data by quantizing and outputs code data; an inverse quantizer 33 that inversely quantizes the code data from the quantizer 32 to reproduce a prediction error;
A prediction value is added to the prediction error from the inverse quantizer 33,
An adder 34 for reproducing a pixel value; and a prediction function circuit 3 for selecting a prediction function based on the pixel value from the adder 34 and a motion vector from the motion detection circuit 14 and generating a prediction value.
And 5.

The prediction function circuit 35 performs intra-field prediction functions such as so-called pre-prediction and one-line prediction, inter-field prediction functions such as using lines above and below the previous field, and inter-frame prediction functions such as so-called motion compensation prediction. It has a prediction function and, based on the pixel value (hereinafter referred to as the previous pixel value) from the adder 34 and the motion vector from the motion detection circuit 14, selects an optimal prediction function (hereinafter referred to as an operation mode) from these.
Is selected for each pixel, and the obtained predicted value is supplied to the adder 31.

Each time a new pixel value (hereinafter referred to as a current pixel value) is supplied, the adder 31 subtracts a prediction value from the current pixel value to obtain a prediction error.

The quantizer 32 has, for example, a plurality of quantization widths (quantization steps), and has a predetermined quantization, for example, the data generation amount is equal to or less than a predetermined value and is maximum, and a small value is finely quantized. The prediction error is quantized by non-linear quantization for coarsely quantizing a large value to generate code data, and this code data is output. The quantization step of the quantizer 32 is controlled by the controller based on, for example, the so-called buffer occupancy of the buffer memory 17.

The inverse quantizer 33 inversely quantizes the code data supplied from the quantizer 32 to reproduce a prediction error.
This prediction error is supplied to the adder 34.

The adder 34 calculates the prediction error and the prediction function circuit 3
5 to reproduce the pixel value corresponding to the current pixel value input to the adder 31, and to calculate the pixel value before the calculation for the prediction value for the next pixel value. It is supplied to the prediction function circuit 35 as a pixel value.

[0032] Thus, the encoding circuit 30 _Y generates the code data for the luminance data, the encoding circuit 30 _C generates the code data for the color difference data, these code data are supplied to the MUX 15.

The high-efficiency encoding of the encoding circuit 30 may be, for example, DCT or the like in addition to the above-described predictive encoding. Specifically, for example, an encoding circuit employing DCT divides the image data into blocks of, for example, 8 × 8 pixels (samples) in a spatial arrangement as shown in FIG. 4 and cut out from the current frame. An adder 41 for obtaining difference data between image data of a block (hereinafter referred to as current block data) and image data of a block cut out from a previous frame subjected to motion compensation (hereinafter referred to as previous block data); A changeover switch 42 for switching and selecting the difference data from the current data and the current block data;
A discrete cosine transform circuit (hereinafter referred to as a DCT circuit) 43 for performing a discrete cosine transform on the output of the changeover switch 42; a DCT output data from the DCT circuit 43 is quantized by a predetermined quantization to output code data; An inverse quantizer 45 for inversely quantizing the code data from the quantizer 44 to reproduce DCT output data; and an inverse quantizer 4
An inverse discrete cosine transform circuit (hereinafter referred to as an IDCT circuit) 46 for performing an inverse discrete cosine transform of the DCT output data from
An adder 47 for adding the previous block data to the difference data from the DCT circuit 46 to reproduce the current block data; and an adder 47 for adding the current block data from the IDCT circuit 46 to the current block data.
A changeover switch 48 for switching and selecting the current block data from the current block data and a motion vector and the like from the motion detection circuit 14 are subjected to motion compensation on the current block data from the changeover switch 48. And a motion compensation circuit 49 for converting data.

The encoding circuit has three operation modes, for example, an intra-field mode, an inter-field mode, and an inter-frame mode, and an optimal operation mode is determined based on a motion vector supplied from the motion detection circuit 14. Is selected, the pixel value (luminance data or color difference data) in the field is selected in the intra-field mode, the inter-field prediction error value of the pixel is selected in the inter-field mode, and the motion compensation inter-frame prediction error value of the pixel is selected in the inter-frame mode. Then, block data composed of 8 × 8 pixels is subjected to two-dimensional discrete cosine transform, and the obtained DCT output data is quantized and output.

That is, the motion detection circuit 14
An optimum motion vector that minimizes the sum of absolute values of difference data for each pixel between block data to be compared is detected by so-called block matching within or between frames.

Each time the current block data is supplied, the adder 41 calculates a motion compensation circuit 49 from the current block data.
Is subtracted on a pixel-by-pixel basis from the motion-compensated previous block data supplied from, to obtain difference data of 8 × 8 pixels.

The changeover switch 42 is controlled by, for example, the above-described controller based on the motion vector from the motion detection circuit 14, the occupancy of the buffer memory 17, and the like. In the mode, the mode is switched to the INTER side, and the current block data, which is the pixel value in the field, and
It switches and selects the difference data from the adder 41, which is the inter-field prediction error value or the motion compensation inter-frame prediction error value, and outputs it.

The DCT circuit 43 converts the current block data selected by the changeover switch 42 or the difference data supplied from the adder 41 in block units into a discrete cosine transform,
DCT output data of × 8 coefficient is generated and supplied to the quantizer 44.

The quantizer 44 has a plurality of quantization steps, and quantizes the DCT output data supplied from the DCT circuit 43 to a predetermined value. The so-called low-frequency component is quantized with a large weight, that is, the low-frequency component is finely quantized, and the obtained code data is dequantized by the inverse quantizer 45 and M
UX15. The quantization step of the quantizer 44 is controlled by the controller based on, for example, the so-called buffer occupancy of the buffer memory 17.

The inverse quantizer 45 inversely quantizes the code data and converts the obtained DCT output data of 8 × 8 coefficients into an IDCT.
It is supplied to the circuit 46.

The IDCT circuit 46 performs an inverse discrete cosine transform of the DCT output data.
The block data corresponding to the current block data input to 1 is reproduced, and the difference data is reproduced in the inter-field mode and the inter-frame mode.

The adder 47 adds the difference data supplied from the IDCT circuit 46 and the motion-compensated previous block data supplied from the motion compensation circuit 49 to form an adder 41.
And reproduces the block data corresponding to the current block data input to.

The changeover switch 48 is linked to the changeover switch 42, and selects the block data reproduced by the IDCT circuit 46 or the adder 47.

The motion compensating circuit 49 includes, for example, a frame memory, and performs motion compensation on the block data supplied via the changeover switch 48 based on the motion vector from the motion detecting circuit 14. When the block data of the next frame is input to the adder 41, the stored frame data is supplied to the adder 41 and the motion detection circuit 14 as the previous frame data.

[0045] Thus, the encoding circuit 30 _Y generates the code data for the luminance data, the encoding circuit 30 _C generates the code data for the color difference data, these code data are supplied to the MUX 15.

The MUX 15 includes encoding circuits 30 _Y and 30 _C
The motion vector supplied from the motion detection circuit 14 and the control data, which is information on the quantization step and the operation mode, are multiplexed with each code data for the luminance data and the color difference data supplied from the The supplied code data is supplied to the VLC 16.

The VLC 16 performs, for example, so-called Huffman coding and run-length coding on the code data to generate variable-length code data.

The buffer memory 17 temporarily stores the variable-length code data supplied from the VLC 16, smoothes and reads out the stored variable-length code data, and supplies the variable-length code data at a constant rate to the error correction encoder 18. .

The error correction encoder 18 comprises, for example, an encoder using a so-called convolutional code. The error correction encoder 18 has a different amount of error correction code between the normal mode and the fallback mode. In addition, an error correction code having a large error correction code amount is added to the variable length code data. That is, the error correction encoder 18 has a coding rule of a normal mode and a coding rule of a fallback mode having a large error correction code amount and a high error correction capability. More specifically, the error correction encoder 18 sets the transmission rate to 22 Mbps, assigns 25% to the error correction code in the normal mode, and sets the transmission rate for variable-length code data to 16.5.
(= 22 × 0.75) Mbps, and an error correction code having an error correction code amount of 5.5 (= 22 × 0.25) Mbps converted to the transmission rate is added. On the other hand, in the fallback mode, if 50% is allocated to enhance the error correction capability, the transmission rate for variable-length code data is 11 (= 22).
× 0.5) Mbps, and an error correction code whose error correction code amount is 11 Mbps in transmission rate is added. Then, the variable-length code data to which the error correction code has been added in this manner is transmitted via a transmission path having the same transmission rate in the normal mode and the fallback mode.

Therefore, for example, the frame period is reduced to 1/3
Assuming that the time is 0 second and the number of lines is 496, in the normal mode, the number of samples per line for luminance data is 360 and the number of samples for color difference data is 180 as described above. The quantization step in the quantizer 32 or the quantizer 44 shown in FIG.
The average number of bits per sample is a value corresponding to 2.05 bits / sample. On the other hand, in the fallback mode, as described above, the number of samples in the horizontal direction for the luminance data is 240, and
Since there are 20 samples, the quantization step is a value corresponding to an average number of bits per sample converted to a transmission path of 2.05 bits / sample, as shown in Expression 2 below.

By the way, in the conventional apparatus, since the sampling frequency is not changed in the fallback mode, the quantization step is performed by calculating the average number of bits per sample converted to the transmission path as shown in the following equation 3. This is a value corresponding to 1.37 bits / sample. That is, in the digital image transmitting apparatus, in the fallback mode, by setting the sampling frequency to ／ of the normal mode as described above, the average number of bits per sample can be set to the same value as in the normal mode. In the above-described predictive coding, so-called S / N (Signal to No
iset ratio), and DCT can prevent the occurrence of so-called block distortion. The error correction method may be, for example, error correction using a block code or the like.

Average number of bits = 16.5 × 10 ⁶ / ((360 + 180) × 496 × 30) Expression 1 = 2.05

Average number of bits = 11 × 10 ⁶ / ((240 + 120) × 496 × 30) Expression 2 = 2.05

Average number of bits = 11 × 10 ⁶ / ((360 + 180) × 496 × 30) Equation 3 = 1.37

Next, a digital image receiving apparatus will be described.
explain. This digital image receiving apparatus is shown in FIG.
The received image data, that is, the variable-length code data
Error correction decoder 51 for performing error correction processing on data
And the transmission mode based on the variable-length code data.
Digital / analog (hereinafter referred to as D / A)
B) Mode determination for controlling the clock frequency of the conversion circuit 90
From the error correction decoder 51
A buffer memory 52 for temporarily storing long code data,
The variable-length code data from the buffer memory 52 is subjected to variable-length decoding.
A variable-length decoding circuit that encodes and reproduces encoded data
VLD 53) and code data from the VLD 53
Is divided into code data for luminance data and chrominance data, etc.
Demultiplexer (hereinafter referred to as DMUX) 54
And a code for the luminance data separated by the DMUX 54.
Performs decoding corresponding to the encoding at the time of transmission
Decoding circuit 70_YAnd the color separated by DMUX54
The code data for the difference data is
Decoding circuit 70 for performing a corresponding decoding_CAnd the decoding circuit
70_CInterpolates the color difference data reproduced in
Vertical interpolation circuit 55 and the decoding circuit 70_YPlayed in
Horizontal interpolation circuit 56 for interpolating the obtained luminance data in the horizontal direction
_YAnd the color difference data from the vertical interpolation circuit 55
Horizontal interpolation circuit 56 that performs interpolation processing in the_CAnd the horizontal interpolation cycle
Road 56_Y, 56 _CBrightness data and color difference data from external
A frame synchronizer 57 for synchronizing with a device;
Luminance data and color difference data from the frame synchronizer 57
Data to analog signals and play back the original video signal.
And a D / A conversion circuit 90.

And, this digital image receiving apparatus
The received image data, that is, the mode at the time of transmission based on the variable length code data is detected whether the normal mode or the fallback mode, and while performing error correction processing corresponding to the mode detected in the variable length code data, After the error-corrected variable-length code data is subjected to data processing such as decoding corresponding to variable-length coding at the time of transmission, coding corresponding to high-efficiency coding, and interpolation processing to reproduce image data,
The image data is converted into an analog signal by a clock corresponding to a sampling frequency at the time of transmission and output.

Specifically, the error correction decoder 51
The decoder includes a decoder corresponding to the error correction encoder 18 shown in FIG. 1 described above. The mode is switched between the normal mode and the fallback mode by the mode switching signal from the mode determination circuit 60, and based on the coding rule corresponding to the switched mode. Error correction of variable-length code data is performed, and an error state of data corresponding to, for example, a synchronization signal is detected. If an error occurs, an error flag is set (1).
Is supplied to the mode determination circuit 60.

The mode determination circuit 60 is cleared by an oscillator 61 for generating a predetermined clock and an error flag from the error correction decoder 51 and counts the clock from the oscillator 61 as shown in FIG. And a D-type flip-flop (hereinafter, referred to as D-FF) 63 that operates using the output of the counter 62 as a clock.

Then, as shown in FIG. 7A, for example, at time t ₁ , when the digital image transmitting apparatus switches from the normal mode to the fallback mode, for example, the coding rules are different. The error flag is set with a certain delay. The counter 62
When the error flag is in the reset state (0), it is cleared. When the error flag is in the set state, the clock (shown in FIG. 7C) from the oscillator 61 is counted. As shown in FIG. Divide-by-4, divide-by-8, ...
・ Output the signal. D-FF 63, for example operates at the rising edge of the divide-by-8 output of the counter 62 (QC), as shown in FIG. 7E, a 1 at time t ₂ to time T ₁ since the error flag gusset has elapsed mode The switching signal is supplied to the error correction decoder 51, the D / A conversion circuit 90, and the like.

The error correction decoder 51 switches to a mode different from the current operation mode, for example, from the normal mode to the fallback mode, in response to the mode switching signal, and starts an error correction process having a high error correction capability.
As a result, as shown in FIG. 7B, the error flag is reset from time t ₂ to a predetermined time T ₂ has elapsed time t _3. Meanwhile, without immediately mode switching since the error flag is set by the mode switching after a time T ₁ has elapsed, at the time when the error flag is set due to an error or the like of the transmission line without changing the transmission mode, Unnecessary mode switching can be prevented.

The error-corrected variable-length code data is temporarily stored in the buffer memory 52. V
The LD 53 decodes the variable-length code data read from the buffer memory 52 to reproduce the code data, and supplies the code data to the DMUX 54.

The DMUX 54 converts the code data from the VLD 53 into code data corresponding to luminance data, code data corresponding to chrominance data, a motion vector, a quantization step,
Separating the control data which is information of the operation mode, the decoding circuit 70 _Y luminance data, and supplies the color difference data to the decoding circuit 70 _C, a motion vector, quantization step, decoding circuit control data 70 _Y ,
70 is supplied to the _C.

The decoding circuits 70 _Y and 70 _C have the same circuit configuration (hereinafter referred to as the decoding circuit 70), and are composed of, for example, decoding circuits corresponding to the predictive coding circuit shown in FIG. As shown in FIG. 8, an inverse quantizer 71 for inversely quantizing the code data from the DMUX 54 to reproduce a prediction error, and adding a prediction value to the prediction error from the inverse quantizer 71 to obtain a pixel value And a prediction function circuit 73 for generating a predicted value.

The inverse quantizer 71 inversely quantizes the code data using the received quantization step, and supplies the obtained prediction error to the adder 72.

The adder 72 calculates the prediction error and the prediction function circuit 7
3 to reproduce a pixel value (luminance data or color difference data) by adding the predicted value supplied from 3 and output this pixel value.

The prediction function circuit 73 has an intra-field prediction function, an inter-field prediction function, and an inter-frame prediction function, like the prediction function circuit 35 shown in FIG.
The operation mode at the time of transmission is detected based on the control data supplied from the UX 54, a prediction function for the detected operation mode is selected, and the pixel value supplied from the adder 72 and the motion vector supplied from the DMUX 54 A predicted value is generated on the basis of
Feed to 2.

[0067] Thus, the decoding circuit 70 _Y reproduces the luminance data, the decoding circuit 70 _C reproduces the color difference data.

The decoding of the decoding circuit 70 is as follows.
In addition to decoding corresponding to the above-described predictive coding, for example, ID
CT or the like may be used. Specifically, for example, a decoding circuit adopting the IDCT, for example, as shown in FIG.
An inverse quantizer 81 for inversely quantizing the code data from the MUX 54 to reproduce DCT output data;
IDC for inverse discrete cosine transform of DCT output data from 1
A T circuit 82; an adder 83 that adds the previous block data to the difference data reproduced by the IDCT circuit 82 to reproduce block data; and a block data from the IDCT circuit 82 and the block data from the adder 83 Based on the changeover switch 84 for selecting the changeover and the motion vector from the DMUX 54, the block data supplied through the changeover switch 84 is subjected to motion compensation, and the obtained block data is added to the adder 83 as the previous block data.
And a motion compensating circuit 85 for supplying the motion compensation signal to the first stage.

The decoding circuit has three operation modes, an intra-field mode, an inter-field mode and an inter-frame mode, corresponding to the encoding circuit shown in FIG. An operation mode at the time of transmission is detected based on the data, and DCT output data is subjected to data processing such as inverse quantization and inverse discrete cosine transform in accordance with the detected operation mode to reproduce block data. .

That is, the inverse quantizer 81 outputs the DMUX5
4 is inversely quantized based on the quantization step supplied from the DMUX 54, and the obtained 8 × 8 coefficient DCT output data is supplied to the IDCT circuit 82.

The IDCT circuit 82 performs an inverse discrete cosine transform of the DCT output data, reproduces block data (luminance data or chrominance data) in the intra-field mode, and inter-field prediction error value or motion in the inter-field mode and the inter-frame mode. The difference data, which is the inter-compensation frame prediction error value, is reproduced.

The adder 83 adds the difference data reproduced by the IDCT circuit 82 and the previous block data which has been motion-compensated and supplied from the motion compensation circuit 85 to reproduce block data (luminance data or chrominance data). I do.

The changeover switch 84 is controlled according to the operation mode, and is set to the INTRA side in the intra-field mode, and to the INTER side in the inter-field mode and the inter-frame mode.
Side, and the IDCT circuit 82 or the adder 83
And outputs the selected block data.

The motion compensation circuit 85 includes, for example, a frame memory, and performs motion compensation on the block data supplied through the changeover switch 84 based on the motion vector supplied from the DMUX 54, and converts the obtained block data into the previous block. The data is supplied to the adder 83 as data.

[0075] Thus, the decoding circuit 70 _Y reproduces the luminance data, the decoding circuit 70 _C reproduces the color difference data.

The horizontal interpolation circuit 56 _Y is provided with a decoding circuit 70 _Y
By interpolating on the line the luminance data supplied from, the luminance data thinned out at the time of transmission is reproduced,
The luminance data whose sampling frequency is 6.75 MHz in the normal mode and 4.5 MHz in the fallback mode is reproduced.

The vertical interpolation circuit 55 interpolates the chrominance data supplied from the decoding circuit 70 _C line-sequentially between the lines, thereby reproducing two series of chrominance data over all the lines.

The horizontal supplementary circuit 56 _C reproduces the chrominance data thinned out at the time of transmission by interpolating the chrominance data supplied from the vertical interpolation circuit 55 on the line. It generates two series of color difference data of 3.375 MHz and 2.25 MHz in the fallback mode.

The frame synchronizer 57 temporarily stores luminance data and color difference data supplied from the horizontal interpolation circuits 56 _Y and 56 _C , respectively, and external equipment (not shown) for supplying a video signal reproduced by the digital image receiving apparatus. ), And supplies the read luminance data and color difference data to the D / A conversion circuit 90.

The D / A conversion circuit 90 is, for example, as shown in FIG.
As described above, the luminance from the frame synchronizer 57 is
Data and two series of color difference data are converted to video signals respectively.
D / A converter 91_Y, 91_R, 91_BAnd the D / A
Converter 91_Y, 91_R, 91 _BEach video signal from
LPF92 to filter_Y, 92_R, 92_BAnd D /
A converter 91_Y, 91_R, 91_BGenerate a clock for
93 and a clock from the oscillator 93
A frequency divider 94 for dividing the frequency and a clock from the oscillator 93
From the frequency dividers 95 and 95, and the frequency dividers 94 and 95
A changeover switch 96 for switching and selecting each clock of
The clock selected by the changeover switch 96 is divided by two.
And a frequency divider 97.

The oscillator 93 generates a clock of, for example, 27 MHz, and the frequency divider 94 divides the frequency of the clock by 2 to generate a clock of 13.5 (= 27 ÷ 2) MHz.
The frequency divider 95 divides the frequency by 3 to generate a clock of 9 (= 27/3) MHz.

The changeover switch 96 is connected to the mode determination circuit 60
Operates in accordance with the mode switching signal from the first mode, selects a 13.5 MHz clock from the frequency divider 94 in the normal mode,
In fallback mode select of 9MHz from the frequency divider 95 a clock, and supplies the D / A converter 91 _Y was selected as the clock corresponding to the sampling clock of the A / D converter.

On the other hand, the frequency divider 97 divides the frequency of the clock selected by the changeover switch 96 by two, and in the normal mode, divides the clock by 6.
A clock of 75 (= 13.5 ÷ 2) MHz is generated, and a clock of 4.5 (= 9 ÷ 2) MHz is generated in the fallback mode, and the generated clocks are D / A converters 91 _R and 91 _R.
Supply to _B.

[0084] D / A converter 91 _Y and LPF 92 _Y is
Using the clock supplied from the changeover switch 96, the luminance data supplied from the frame synchronizer 57 is converted into an analog signal, and the luminance signal (Y) is reproduced.
/ A converters 91 _R and 91 _B and LPFs 92 _R and 92
_B uses the clock supplied from the frequency divider 97 to
Each of the color difference data of the series is converted into an analog signal,
The color difference signals (RY, BY) are reproduced.

Thus, this D / A conversion circuit 90
The number of samples (the number of pixels) per line is set to 720 and 360 in the normal mode, and the luminance data and chrominance data set to 480 and 240 in the fallback mode are converted into analog signals. Output to external device.

As described above, in the digital image transmitting apparatus, when the video signal is sampled, converted into image data and transmitted, the fallback mode when the quality of the transmission path is deteriorated is lower than that in the normal mode. In addition, the sampling frequency of the A / D conversion circuit 20 is lowered, and the error correction code to be added by the error correction encoder 18 is transmitted with an increased code amount. At the time of conversion into a video signal by the A conversion circuit 90 and output, the mode at the time of transmission is detected based on the image data, and the D / A
By controlling the clock of the conversion circuit 90 to match the sampling frequency at the time of transmission, the average number of bits per sample can be set to the same value as in the normal mode. For example, in a system using predictive coding, S / N
Can be prevented. For example, in a system employing DCT, occurrence of block distortion can be prevented. Further, the digital image receiving apparatus can automatically switch between the normal mode and the fallback mode.

The present invention is not limited to the above-described embodiment. For example, the A / D converters 91 _Y , 91 _R ,
Instead of changing the sampling frequency of 91 _B, as well as slower than the read cycle from TBC11 in fallback mode to the normal mode may be read out by thinning. Further, the thinning rate in the sub-sampling circuits 12 _Y and 12 _C in the fallback mode may be made larger than that in the normal mode. In addition, the coding includes the above-described predictive coding and DCT.
In addition, for example, transform coding such as so-called slant transform and Haar transform can be used.

[0088]

As is apparent from the above description, according to the present invention, in a digital image transmitting apparatus, when a video signal is sampled, converted into image data and transmitted, a fallback mode is usually used. The sampling frequency of the analog / digital conversion means is lowered compared to the mode, and the error correction code amount is increased and transmitted.
In a digital image receiving apparatus, when converting received image data into a video signal and outputting the video signal, a mode at the time of transmission is detected based on the image data, and a clock of the digital / analog conversion means is controlled based on the detection result. By doing so, the average number of bits per sample can be set to the same value as in the normal mode. For example, in a system employing predictive coding, deterioration of S / N can be prevented,
Further, for example, in a system employing DCT, occurrence of block distortion can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a digital image transmission device to which the present invention has been applied.

FIG. 2 shows an A / D constituting the digital image transmitting apparatus.
FIG. 3 is a block diagram illustrating a specific circuit configuration of a conversion circuit.

FIG. 3 is a block diagram showing a specific circuit configuration of an encoding circuit constituting the digital image transmission device.

FIG. 4 is a block diagram showing another specific circuit configuration of the encoding circuit constituting the digital image transmission device.

FIG. 5 is a block diagram showing a circuit configuration of a digital image receiving apparatus to which the present invention has been applied.

FIG. 6 is a block diagram illustrating a specific circuit configuration of a mode determination circuit included in the digital image receiving device.

FIG. 7 is a time chart for explaining the operation of the mode determination circuit.

FIG. 8 is a block diagram showing a specific circuit configuration of a decoding circuit constituting the digital image receiving device.

FIG. 9 is a block diagram showing another specific circuit configuration of the decoding circuit constituting the digital image receiving device.

FIG. 10 shows a D / D constituting the digital image receiving apparatus.
FIG. 3 is a block diagram illustrating a specific circuit configuration of an A conversion circuit.

[Explanation of symbols]

18 Error correction encoder 20 A / D conversion circuit 22 _Y , 22 _R , 22 _B A / D converter 23 Oscillator 23 26 Changeover switch 51 Error correction Decoder 60: Mode determination circuit 90: D / A conversion circuit 91 _Y , 91 _R , 91 _B: D / A converter 93: Oscillator 96: Changeover switch

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-2-30238 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/41-1/419 H04L 1 / 00 H04N 7/30

Claims (4)

(57) [Claims] 1. An analog / digital conversion means for converting a video signal into image data , an error correction code adding means for adding an error correction code to image data from the analog / digital conversion means and transmitting the image data, A fallback mode when the quality of the transmission path is degraded. When transmitting image data in the fallback mode, the video signal is transmitted as compared with the normal mode.
Signal sampling frequency, the amount of error correction code added by the error correction code addition means is increased, and the average number of bits per sample is set to the normal mode.
And a control means for performing control so as to obtain the same value as that of the digital image transmitting apparatus. 2. A video signal is converted into image data, and an error correction code is added to the converted image data and transmitted.
When transmitting the above image data, the quality of the transmission path is degraded.
Normal mode when transmitting in fallback mode
Lower the sampling frequency of the video signal compared to
Error correction added to the image data
Increase the code amount and increase the average number of bits per sample
Control and send to the same value as in normal mode.
And a digital image transmission method. 3. An analog converter for converting a video signal into image data.
Digital / digital conversion means and image data from the analog / digital conversion means.
Error correction code adding procedure to add error correction code and transmit
Stage, normal mode, and fall when transmission line quality deteriorates
And a fall-back mode.
When transmitting in video mode, the video signal
Signal sampling frequency, and
-Increase the amount of error correction code added by the correction code addition means.
The average number of bits per sample in normal mode
And control means for controlling so as to have the same value as
Digital image transmitting device and image data transmitted from the digital image transmitting device
And performs error correction processing on the received image data.
Error correcting means, and converting the image data from the error correcting means into a video signal.
Digital / analog conversion means and a mode for transmission based on the received image data
Is detected, and a sampling cycle at the time of transmission is detected based on the detection result.
Control means for controlling the clock so as to match the wave number.
Digital image transmission system, wherein the digital image receiving apparatus comprising, in that it consists of
M 4. A video signal is converted into image data, and an error correction code is added to the converted image data and transmitted.
The image data when the quality of the transmission path deteriorates.
When transmitting in fallback mode, the
And lower the sampling frequency of the video signal
In both cases, the amount of error correction code added to the above image data
The average number of bits per sample
The control is performed so that the same value as that of the image data is transmitted, the received image data is received, and the received image data is received.
Error correction processing, and converts the image data on which the error correction processing has been performed into a video signal.
In other words, the mode at the time of transmission based on the received image data
Is detected, and a sampling cycle at the time of transmission is detected based on the detection result.
The feature is that the clock is controlled to match the wave number
Digital image transmission and reception method.