JPH03250885A - Video signal transmitter - Google Patents

Abstract

PURPOSE:To control a quantization step size with high accuracy with simple constitution by converting an output data of a quantization circuit into a parallel variable length coding data and a code length data and then converting the data into a serial variable length coding data. CONSTITUTION:A parallel output data from a requantization circuit 24 is converted into a parallel variable length coding data DT and a code length data DL and stored in buffer memory circuits 62, 64 and then converted again into a serial variable length coding data DVLC, then a parallel serial conversion circuit 66 is in operation at a low speed. ln this case, a counter circuit 68 detects a difference of the data quantity between the parallel variable length coding data DT from the 1st conversion table 60 and the serial variable length coding data DVLC outputted from the transmission buffer circuit 33 to select the quantization step size based on the result of detection. Thus, the requantization circuit is controlled with simple constitution and high accuracy.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology Problems to be solved by the invention B (Figures 6 and 7) El! ! ! Means to solve the problem (Figures 1 and 3)
2 Effects (Figures 1 and 3) G Example (Figures 1 to 5) (Gl) Structure of Example (Figures 1 to 5) (Gl-1)
Variable length encoding circuit (Figs. 3 to 5) (G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments H Effects of the invention A Field of industrial application The present invention is applicable to video signals. Regarding a transmission device, the present invention can be applied to, for example, a video signal transmission device that performs high-efficiency encoding processing on a moving image video signal and transmits the result.

B. Summary of the Invention The present invention provides a video signal transmission device with a simple configuration by converting output data of a quantization circuit into parallel variable-length encoded data and code length data, and converting the data into serial variable-length encoded data. The quantization step size can be controlled with good precision.

C. Prior Art Conventionally, in so-called video communication transmission systems that transmit video signals consisting of moving images to remote locations, such as video conferencing systems and video telephone systems, in order to efficiently utilize transmission paths, the video signal is Video signals are subjected to interframe encoding processing using interframe correlation, thereby increasing the transmission efficiency of significant information.

That is, on the transmission device side, a motion vector detection circuit detects a motion vector of an image to be transmitted based on an image of a predetermined frame (hereinafter referred to as a reference frame).

Further, the transmitting device side moves the reference frame image by the amount of the motion vector to generate a comparison reference image, and then sequentially detects difference data pixel by pixel between the image to be transmitted and the image to be transmitted.
The difference data is transmitted together with the motion vector i.

In the receiving device, the reference frame image transmitted in advance is moved by the amount of the transmitted motion vector, and then the transmitted difference data is added to reproduce the original image.

As a result, image data for one frame can be transmitted with a smaller amount of data than when directly transmitting image data for one frame, and by repeating the process, video signals can be transmitted efficiently. can do.

Problems to be Solved by the Invention Incidentally, in this type of video signal transmission device, differential data is subjected to discrete cosine transformation.
After the sine transform), requantization processing and variable length encoding processing are performed, and furthermore, it is possible to transmit with high efficiency.

Furthermore, at this time, the requantization step size is switched and controlled so that the amount of data transmission per frame becomes a predetermined value.

Further, data subjected to variable length encoding processing is transmitted at a predetermined transmission speed via a transmission buffer circuit by changing the data length.

That is, as shown in FIG. 6, for example, 8-bit conversion data D output from the discrete cosine conversion circuit
IIC? After requantization processing is performed by the requantization circuit 2, variable length encoding processing is performed by the variable length encoding circuit 3.

At this time, the amount of data generated is detected by the variable length encoding circuit 3, and the requantization step size of the requantization circuit 2 is switched and controlled based on the detection result, so that the amount of data transmission per frame reaches a predetermined value. control so that

Further, the variable length encoded data is converted into serial data and output to the transmission buffer circuit 4, thereby outputting the encoded data at a predetermined transmission speed.

At this time, the counter circuit 5 sequentially counts up the input data of the transmission buffer circuit 4 and sequentially counts down the output data of the transmission buffer circuit 4, thereby detecting the remaining capacity of the transmission buffer circuit 4.

Furthermore, the requantization step size of the requantization circuit 2 is switched based on the count value of the counter circuit 5 to prevent overflow and underflow of the transmission buffer circuit 4.

However, in reality, data with a low frequency of occurrence may be continuously input to the variable length encoding circuit 3.

In this case, the variable length encoding circuit 3 generates data with a long data length, and when converting the variable length encoded data into serial data, a high-speed parallel-serial conversion operation is required.

Therefore, there is a problem that the configuration of the variable length encoding circuit 3 becomes complicated accordingly.

One possible method for solving this problem is to insert a large capacity buffer memory circuit 6 between the requantization circuit 2 and the variable length encoding circuit 3, as shown in FIG.

However, when the buffer memory circuit 6 is inserted in this way, the delay time until the requantized data is stored in the transmission buffer circuit 4 increases accordingly.

Therefore, there is a problem in that the feedback of the count results is delayed accordingly, making it difficult to switch and control the requantization step size with high precision.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a video signal transmission device that can control a requantization circuit with high precision with a simple configuration.

E Means for Solving the Problems In order to solve the problems, in the present invention, image data DIN is subjected to intra-frame encoding processing and inter-frame encoding processing, and then re-quantization processing and variable length encoding processing before being transmitted. In the video signal transmission device 1o, a requantization circuit 24
A first conversion table 60 that converts the parallel output data output from the parallel variable length encoded data D into parallel variable length encoded data D, and outputs code length data DL of the parallel variable length encoded data D based on the parallel output data. and the second conversion table 60 for converting parallel variable length encoded data D? and a buffer memory circuit 62.64 that temporarily stores the code length data DL, and the parallel variable length encoded data D? based on the code length data D+- output from the buffer memory circuit 62.64. a parallel-to-serial conversion circuit 66 that converts the data into serial variable length encoded data DvLc;
A transmission buffer circuit 33 stores and sequentially outputs serial variable length encoded data DvLe, and a first
A counter circuit 68 detects the difference between the data amount of the parallel variable length encoded data D output from the conversion table 60 and the serial variable length encoded data D VLC output from the transmission buffer circuit 33, Based on the count result of the counter circuit 68, the quantization step size of the requantization circuit 24 is switched.

The parallel output data output from the F-action requantization circuit 24 is converted into parallel variable length encoded data Dr and code length data D.
, and stored in the buffer memory circuits 62 and 64, and then converted to serial variable length encoded data DvLC, the parallel-to-serial conversion circuit 66 can be operated at a low speed.

At this time, the counter circuit 68 converts the first conversion table 60
The data amount difference between the parallel variable length encoded data DT outputted from the transmission buffer circuit 33 and the serial variable length encoded data DVLC outputted from the transmission buffer circuit 33 is detected, and the quantization step size is switched based on the detection result. By doing so, the quantization step size can be switched and controlled with high precision.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) Configuration of Embodiment In FIG. 1, 10 indicates a video signal transmission device as a whole, which mutually transmits video and audio of a caller to a transmission target.

That is, the video signal transmission 10 is transmitted to the television camera 12.
The television camera 12 captures an image of the caller through the
The video signal Sv output from the video signal processing circuit 1
Give to 4.

The video signal processing circuit 14 converts the video signal Sv into a luminance signal and a color difference signal, and then converts the signal into a digital signal using an analog-to-digital conversion circuit.

The video signal processing circuit 14 converts the luminance signal and color difference signal converted into digital signals into a CCITT (inter
national telegraph and te
lephone consultative coms
+1ttee) Convert to the recommended format.

That is, after converting the frame frequency to 15 (Hz) by thinning out the video signal every predetermined frame, the number of pixels between the vertical and horizontal scanning directions is reduced.

As a result, regarding the luminance signal, an input video signal is created in which image data DIN of 352 x 288 pixels (that is, the image size of CIF) or 176 x 144 Wi elements (that is, the image size of QCIF) is continuous in the horizontal and vertical scanning directions. .

In this way, the video signal Sv is subjected to preliminary processing via the video signal processing circuit 14 to reduce the amount of data, and an input video signal in which the image data DIN are consecutive in the order of line scanning can be obtained.

As shown in FIG. 2, the motion vector detection circuit 16 stores the image data DIN in a memory circuit in a built-in scan conversion circuit, and then sequentially reads the image data DIN in a predetermined order, thereby changing the arrangement of the image data DIN. Rearrange in a predetermined order.

That is, the motion vector detection circuit 16 divides one frame of image (FIG. 2(A)) into 2×6 blocks (1, OB (hereinafter referred to as block groups) in the horizontal and vertical scanning directions.
(Figure 2 (B)).

Further, the motion vector detection circuit 16 divides each block group GOB into 11×3 macroblocks Bk, and then further divides the macroblock BK into microblocks B of 8×8 pixels in the horizontal and vertical scanning directions. Figure 2 (C)).

As a result, the video signal processing device 1 transfers and processes image data in units of block groups GOB.

Furthermore, at this time, in the arrangement of the image data DIN in the block group GOB, the image data DIN is arranged consecutively in units of macroblocks B, and within macroblocks B, the image data DIN is arranged in units of microblocks BL in the order of rask scanning. The image data D1 is made continuous.

Note that macroblock B here has the following for the luminance signal:
While image data (Y, -Y,) of 16 x 16 pixels continuous in the horizontal and vertical scanning directions is taken as one unit, the video signal processing circuit 14 uses two color difference signals corresponding to the image data (Y, -Y,). After the data amount is reduced, time-axis multiplexing processing is performed, and each minute block BL (C
, , , CI), data for 16×16 pixels is allocated.

At this time, the motion vector detection circuit 16
The image of the previous frame reproduced in step 8 is set as the reference frame image, and macroblock B is processed.

The motion vector is detected for each motion.

Furthermore, the motion vector detection circuit 16 moves the reference frame image by the amount of the motion vector obtained by horizontal ratio, and moves the reference frame image by an amount corresponding to the 16×16 macroblock B of the current frame.
After creating image data for pixels, the image data D,
□ is output to the difference data creation circuit 20.

At the same time, the motion vector detection circuit 16 outputs the rearranged image data DINO after being delayed by the time required to detect the motion vector.

Furthermore, the motion vector detection circuit 16 processes image data.

The frame number, block group and macroblock address data, motion vector I/DUG, and the sum of absolute values obtained when detecting the motion vector are sent to the header D HET.
is generated and output to the difference data creation circuit 20.

The difference data creation circuit 20 outputs the image data DINII for each predetermined frame to the subsequent discrete cosine transform circuit 22 without any processing, thereby transmitting the intra-frame encoded image data every predetermined period. It is designed so that it can be transmitted to the target.

On the other hand, for frames other than those to be subjected to intra-frame encoding processing, image data D□1 is subtracted from image data D-0, and the resulting difference data D2 is output to the discrete cosine transform circuit 22.

As a result, in the video signal processing device 10, by transmitting the difference data D2, the image data is subjected to interframe encoding processing, and by switching between the intraframe encoding processing and the interframe encoding processing at a predetermined period, the image data is transmitted. The input video signal is efficiently transmitted to the target.

Furthermore, at this time, the difference data creation circuit 20 generates the image data D
Pml as image data DIN. When subtracting from the image data D, high-frequency components of the image data D□ are suppressed using a loop filter circuit as necessary.

As a result, in the video signal processing device 10, even if the motion vector is detected in units of macroblocks Bk and the difference data D2 is encoded, the boundaries between eight macroblocks are not noticeable.

Furthermore, the difference data creation circuit 20 detects the amount of data required for transmission in units of macroblocks 81, and it is possible to transmit the amount of data by performing intra-frame encoding processing with a smaller amount of data than by performing inter-frame encoding processing. If it is determined that the image data DIN+ is to be transmitted using intra-frame encoding, even if it is macroblock B of the frame that is subjected to inter-frame encoding, the image data DIN+ is transferred to the subsequent disk without any processing. It is output to the Li-I cosine conversion circuit 22.

(In the video signal transmission device 10, when performing interframe encoding processing, depending on the amount of data required for transmission,
In addition to suppressing the high-frequency components of the image data DtlG, the processing method is switched from inter-frame encoding processing to intra-frame encoding processing. is being done.

At the same time, the difference data creation circuit 20 removes the data of the sum of absolute values from the header D'AtT transmitted from the motion vector detection circuit 16, and then generates the identification data of the interframe encoding process and the intraframe encoding process, and the loop filter circuit 20. The data is outputted to the discrete cosine conversion circuit 22 with the addition of identification data as to whether or not it is difference data obtained through the .

The discrete cosine conversion circuit 22 converts 2 of the video signal.
Using dimensional correlation, the image data D, - and the difference data D2 output from the difference data creation circuit 20 are subjected to discrete cosine transform in units of minute blocks BL, and the resulting transformed data 1) oct is requantized by the circuit. Output to 24.

At this time, the discrete cosine conversion circuit 22 converts the conversion data D into the header transmitted from the difference data creation circuit 20.
Data such as the cumulative code length of t+CT is added and output.

The requantization circuit 24 requantizes and outputs the converted data DI and eT.

At this time, the requantization circuit 24 detects the cumulative code length and data amount of the converted data DI and cA based on the header output from the discrete cosine transform circuit 22, and also detects the remaining amount of the transmission buffer circuit 33, The quantization step size is switched based on the detection result.

As a result, the requantization circuit 24 maintains the amount of data per frame required for transmission at a predetermined value.

Further, the requantization circuit 24 converts the converted data DC from the header output from the discrete-I/cosine conversion circuit 22.
After removing data such as the cumulative code length of T, data of the quantization step size is added and output.

The entertainment quantization circuit 26 executes a conversion process inverse to that of the requantization circuit 24 based on the header output from the requantization circuit 24, thereby converting the conversion of the discrete cosine conversion circuit 20 reproduced on the transmission target side. Data D DCT is reproduced on the transmission side.

On the other hand, the discrete cosine inverse transform circuit 28 carries out the inverse transform process of the discrete cosine transform circuit 22 based on the header transmitted via the entertainment quantization circuit 26.

Thereby, in the video signal transmission device 10, the input data of the discrete cosine conversion circuit 22 that is reproduced on the transmission target side can be reproduced on the transmission side.

That is, for the video signal that is intra-frame encoded and transmitted via the discrete cosine inverse transform circuit 28, eight image data DI can be reproduced, whereas the video signal that is transmitted after the inter-frame encode processing can be reproduced. Regarding the video signal, the difference data D2 can be reproduced.

The decoder circuit 18 is composed of a frame memory circuit and an adder circuit, and switches its operation based on the header transmitted via the discrete cosine inverse transform circuit 2B.

That is, when intra-frame encoded data (that is, image data that reproduces image data DIN+1) is output from the discrete cosine inverse transform circuit 28, the decoder circuit 18 directly stores the image data in the frame memory circuit. do.

Furthermore, with respect to the image data stored in the frame memory circuit, at the timing when the image data DIN of the next frame is inputted to the motion vector detection circuit 16, the image data Dsv stored in the frame memory circuit is transferred to the motion vector detection circuit. Output to 16.

As a result, the motion vector detection circuit 16 can detect a motion vector for a frame subsequent to a frame subjected to intra-frame encoding by setting the frame subjected to intra-frame encoding as a reference frame.

Furthermore, the decoder circuit 18 receives interframe encoded data (
In other words, when data that reproduces the difference data D2 is output, the image data D3V stored in the frame memory circuit is moved by the motion vector of the difference data D2, and then the moved image data is output. The difference data D2
and stores it in the frame memory circuit.

This makes it possible to reproduce the original image data of the interframe encoded frame through the addition circuit, and thus the images transmitted to the transmission target side can be sequentially reproduced and stored in the frame memory circuit. can.

Furthermore, the decoder circuit 18 detects the image data D stored in the frame memory circuit at the timing when the image data DIN of the next frame is input to the motion vector detection circuit 16. sv is output to the motion vector detection circuit 16.

Thereby, the motion vector detection circuit 16 can sequentially detect the motion vector of the current frame using the previous frame as a reference frame.

Further, at this time, in the decoder circuit 18, the loop filter circuit is used to suppress the high frequency component of the difference data D2 created through the loop filter circuit, and the difference data D2 is moved by the amount of the motion vector. The loop filter circuit is switched in conjunction with the difference data creation circuit 20 to make the boundaries between macroblocks 81 less noticeable.

The variable length encoding circuit 30 subjects the output data of the requantization circuit 24 obtained via the buffer circuit 32 to variable length encoding processing together with motion vector data, etc., and then outputs the data together with the header to the transmission buffer circuit 33.

The transmission buffer circuit 33 once stores the output data of the variable length encoding circuit 30, and then sequentially outputs the data in a predetermined order.

The stuff bit addition circuit 34 is the transmission buffer circuit 33
output data to the error correction circuit 36, and at this time, detect the amount of input/output data of the transmission buffer circuit 33, and compare the data amount of the input/output data of the transmission buffer circuit 33 with the transmission speed of
When the amount of input data in step 3 becomes extremely small, stuff bits are inserted between the data at a predetermined timing.

The error correction circuit 36 generates a BCH code (bose chaud) according to the output data of the stuff bit addition circuit 34.
huri hocquenchem code) is added to the output data output from the stuff bit addition circuit 34 and output.

Further, the error correction circuit 36 corrects errors in the data obtained from the transmission target via the multiplex conversion circuit 38 based on the BCH code added to the data and transmitted, so that even if an error occurs during transmission, This is designed to effectively avoid image quality deterioration.

The multiplex conversion circuit 38 multiplexes the digital audio signal with the output data of the error correction circuit 36, and then sends the signal to the line L1.

Thereby, the video signal Sv and the audio signal can be efficiently transmitted to the transmission target.

At the same time, the multiplex conversion circuit 38 inputs the data transmitted from the transmission target via the circuit @Ll, and separates the multiplexed video signal and digital audio signal.

Furthermore, the separated digital audio signal is output to a predetermined decoding circuit, and the video signal is sent to a stuff bit removal circuit 4.
Output to 0.

The stuff bit removal circuit 40 removes the stuff bits inserted by the stuff bit addition circuit 34 on the transmission target side.

The buffer circuit 42 once stores the data from which the stuff bits have been removed, then separates the header and outputs it to the decoding circuit 44 .

The decoding circuit 44 performs inverse processing of the variable length encoding circuit 30 on the transmission target side.

The recreational quantization circuit 46 performs recreational quantization processing on the output data of the decoding circuit 44 based on the header inputted via the composite circuit 44, and thereby requantizes the data to be requantized on the transmission target side. Reproduce the human power data of 24.

Similar to the discrete cosine inverse transform circuit 2, the discrete cosine inverse transform circuit 48 processes the output data of the entertainment quantization circuit 46 based on the header, thereby reproducing the data subjected to the discrete cosine transform on the transmission target side. do.

The decoder circuit 50 executes the same processing as the decoder circuit 18 based on the transmitted header, thereby reproducing the image data encoded on the transmission target side.

The video signal processing circuit 52 uses a supplementary deduction method to
After performing the reverse processing of the video signal processing circuit 14, the resulting video signal is output to the monitor device 54, thereby making it possible to monitor the image of the communication target sent from the transmission target.

(Gl-1) Variable length encoding circuit As shown in FIG. It is given to the long encoding table 60.

Further, the variable length encoding circuit 30 supplies the header D□a input via the buffer circuit 32 to a header decoding circuit (not shown), and separates the macroblock address data, motion vector, and block pattern data. .

Further, the variable length encoding circuit 30 obtains relative values between consecutive macroblocks for the separated address data and motion vectors, and provides the data of the relative values to the variable length encoding table 60 together with the block pattern data. In the video signal transmission device 10, when the discrete cosine transform circuit 22 creates the converted data DDCT, it is determined based on the conversion result whether or not the converted data DDC has noticeable noise that does not need to be transmitted. Based on the results, convert data D only for the necessary minute blocks.

It is designed to output .

The block pattern represents this determination result, and is a pattern of the determination result in units of macroblocks.

As shown in FIG. 4, the variable length encoding table 60 has two
The first table allows input data to be input in real time with a data length of up to 20
It is converted into bit parallel variable length encoded data D.

On the other hand, in the second table, input data is converted in real time into code length data DL representing the code length of D pieces of parallel variable length encoded data.

Buffer memory circuits 62 and 64 temporarily store parallel variable-length encoded data D and code length data DL, respectively, and then convert them to parallel-serial converter circuit (P/5) 66.
The parallel variable length encoded data D7 and the code length data DL are sequentially outputted at a relatively low speed in synchronization with the operation.

On the other hand, as shown in FIG. 5, the parallel-to-serial conversion circuit 66 extracts significant bits of the parallel variable-length encoded data D7 and sequentially converts them into serial data based on the code length data DL.

As a result, serial variable-length encoded data D is obtained by variable-length encoding processing of the requantized image data, macroblock address data, motion vector, and block pattern data via the parallel-to-serial conversion circuit 66.
VLC is obtained, and the serial variable length encoded data Dvhc is sequentially outputted via the transmission buffer circuit 33.

Therefore, the parallel-to-serial conversion circuit 66 can operate at a low speed by converting the parallel variable-length encoded data D input via the buffer circuit 62 into serial data, and can operate at a low speed with a correspondingly simple configuration. DI)
C? can be subjected to variable length encoding processing.

Furthermore, in this embodiment, the header D□ other than the macroblock address data, motion vector, and block pattern data is output to the transmission buffer circuit 33 via a predetermined format conversion table, thereby providing the necessary data for decoding. Output data to the transmission target.

The counter circuit 68 counts up the code length data D, counts down the output data of the transmission buffer circuit 33, and transfers the count result to the requantization circuit 2.
Output to 4.

This allows the requantization circuit 24 to output data with a predetermined quantization step size, and immediately detect how the remaining amount of the transmission buffer circuit 33 changes as a result of the output. .

That is, in the variable length encoding circuit 30, the processing result can be quickly fed back to the requantization circuit 24, and the requantization step size can be switched and controlled with high precision accordingly.

The arithmetic logic circuit 70 having an adder circuit configuration receives code length data D.
L is cumulatively charged and the addition result is output to the requantization circuit 24, and the requantization circuit 24 switches the quantization step size so that the data transmission amount per frame becomes a predetermined value. It is done like this.

(G2) Operation of the embodiment In the above configuration, the video signal Sv output from the television camera 12 is subjected to preliminary processing in the video signal processing circuit 14 to reduce the amount of data, and is converted into image data in the CCITT recommended format. Converted to DIN.

After the image data DIN is rearranged in the motion vector detection circuit 16, a motion vector is detected for each macroblock.

Here, image data DPI+ as a comparison standard is generated based on the detected motion vector, and the image data DPI+ is generated as a comparison standard.
+ is image data D IN! It is output to the difference data creation circuit 20 together with l.

In the difference data creation circuit 20, intraframe encoding processing is selected at a predetermined frame period, and in the intraframe encoding processing, the image data DIHD is directly input to the discrete cosine transformation circuit 22.

On the other hand, in the interframe encoding process, the image data D PI+ is subtracted from the image data DIND to create difference data D2, and the difference data D2 is output to the discrete cosine transform circuit 22.

As a result, the converted data DDC is obtained via the discrete cosine conversion circuit 22, and the converted data DDC is obtained.
7 is requantized by the requantization circuit 24 and then output to the variable length encoding circuit 30 via the buffer circuit 32.

Here, the output data of the requantization circuit 24 is inputted to the variable length encoding table 60 together with the macroblock address data, motion vector, and flock pattern data.
Parallel variable length encoded data D having a maximum data length of 20 bits and code length data DL representing the code length of the parallel variable length encoded data D are converted in real time.

Parallel variable length encoded data D〒 and code length data D
After L is once stored in the buffer circuits 62 and 64,
The signal is outputted to the parallel-to-serial conversion circuit 66 at a relatively low speed in synchronization with the operation of the parallel-to-serial conversion circuit 66, where it is converted into serial variable length encoded data DVLC.

As a result, in the parallel-serial conversion circuit 66,
It can operate at low speed, and the configuration of the variable length encoding circuit 30 can be simplified accordingly.

In this way, the serial variable length coded data D VLC is sent to the transmission target via the transmission buffer circuit 33, the stuff bit adding circuit 34, the error correction circuit 36, and the multiplex conversion circuit 38. You can talk while monitoring.

On the other hand, in the counter circuit 68, the code length data DL is sequentially counted up, whereas the output data of the transmission buffer circuit 33 is sequentially counted down,
By feeding back the count result to the requantization circuit 24, the processing result can be quickly fed back, and the requantization step size can be switched and controlled with high accuracy.

Further, the output data of the requantization circuit 24 is sequentially passed through the entertainment quantization circuit 26 and the discrete cosine inverse transform circuit 28, and is returned to the original image data by the decoder circuit 18, and the image data is used for motion vector detection. The image data of the previous frame is output as image data Dsv.

(G3) Effects of the embodiment According to the above configuration, the output data of the requantization circuit 24 is converted into parallel variable length encoded data D and code length data D.
By converting it into L and storing it in a buffer memory circuit, and then converting it into serial variable length encoded data DVLC,
The parallel-to-serial conversion circuit 66 can be operated at a low speed, and the configuration of the variable length encoding circuit 30 can be simplified accordingly.

Further, by converting into parallel variable length encoded data DT and code length data D, the counter circuit 68 generates
The code length data DL and the output data of the transmission buffer circuit 33 are counted, and the requantization step size can be switched and controlled with high precision based on the counting results.

(G4) Other Embodiments In the above-described embodiments, a case was described in which the output data of the requantization circuit 24 was subjected to variable length encoding processing together with macroblock address data, motion vectors, and block pattern data. The present invention is not limited to this, but can be widely applied to cases where output data of the requantization circuit 24 is subjected to variable length encoding processing as necessary.

Furthermore, in the above-described embodiment, the present invention is applied to a video signal transmission device that transmits a video signal together with an audio signal, but the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this. It can be widely applied when transmitting, recording on a recording medium, etc.

Effects of the Invention As described above, according to the present invention, the output data of the requantization circuit is converted into parallel variable-length encoded data and code length data, and then converted into serial variable-length encoded data. The conversion circuit can be operated at a low speed, and the configuration of the variable length encoding circuit can be simplified accordingly.

Furthermore, by once converting into parallel variable-length encoded data and code length data, the count result of the counter circuit can be quickly fed back. Thus, the requantization step size can be switched and controlled with high precision with a simple configuration. It is possible to obtain a video signal transmission device that can perform

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a video signal transmission device according to an embodiment of the present invention, FIG. 2 is a route diagram for explaining the operation of a motion vector detection circuit, and FIG. 3 is a block diagram showing a variable length encoding circuit. , FIGS. 4 and 5 are route diagrams for explaining its operation, and FIGS. 6 and 7 are block diagrams showing conventional variable length encoding circuits. 2.24...Requantization circuit, 3.30...
...Variable length encoding circuit, 4.33...Transmission buffer circuit, 10...Video signal transmission device, 60.
...Variable length encoding table, 62.64...
...Buffer memory circuit, 66...Parallel-serial conversion circuit. Tape "R0 Output Diagram - 01001010100001 Serial Sum Variable & Encoded Data Diagram

Claims (1)

[Claims] In a video signal transmission device that performs intra-frame encoding processing and inter-frame encoding processing on image data, requantization processing and variable length encoding processing, and then transmits the data, output from a requantization circuit. a first conversion table that converts parallel output data into parallel variable length encoded data; and a second conversion table that outputs code length data of the parallel variable length encoded data based on the parallel output data. , a buffer memory circuit that temporarily stores the parallel variable length encoded data and the code length data; and a buffer memory circuit that converts the parallel variable length encoded data into a serial variable length code based on the code length data output from the buffer memory circuit. a transmission buffer circuit that stores the serial variable length encoded data and sequentially outputs it; and a transmission buffer circuit that stores the serial variable length encoded data and sequentially outputs the encoded data; a counter circuit that detects a difference in data amount between the parallel variable length encoded data output from the conversion table and the serial variable length encoded data output from the transmission buffer circuit; Based on the results,
A video signal transmission device characterized in that the quantization step size of the requantization circuit is switched.