JP3112170B2 - Image data encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means for solving the problem (FIGS. 1 and 5) F function (FIGS. 1 and 5) G Embodiment (FIGS. 1 to 5) (G1) Configuration of Embodiment (FIGS. 1 to 5) (G1-1) Video Signal Transmission Apparatus (FIGS. 3 and 4) (G1-2) ) Difference data creation circuit (FIG. 5) (G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments H Effects of the invention A Industrial application field The present invention relates to an image data encoding device. For example, the present invention can be applied to a video signal transmission device that transmits a moving image video signal after performing a high-efficiency encoding process.

B. Overview of the Invention In the image data encoding apparatus, the usability can be further improved by transmitting the video signal by performing intra-frame encoding processing immediately after the line is connected.

C Prior Art Conventionally, in a so-called video communication transmission system for transmitting a video signal composed of a moving image to a remote place such as a video conference system and a video telephone system, for example, the video signal is transmitted in order to efficiently use a transmission path. A video signal is subjected to an inter-frame encoding process using an inter-frame correlation, thereby increasing the transmission efficiency of significant information.

That is, on the transmission device side, the motion vector detection circuit detects the evaluation function in a stepwise manner using the method of Japanese Patent Laid-Open No. 55-158784, for example, based on the image of a predetermined frame (hereinafter referred to as a reference frame). Thus, the motion vector of the image to be transmitted is detected.

Further, the transmitting apparatus moves the image of the reference frame by the amount of the motion vector to generate the image of the comparison reference,
Difference data is sequentially detected on a pixel-by-pixel basis with an image to be transmitted, and the data is transmitted together with a motion vector.

In the receiving apparatus, after moving the previously transmitted reference frame image by the amount of the transmitted motion vector, the transmitted difference data is added to reproduce the original image.

This makes it possible to transmit one frame of image data with a smaller amount of data than in the case of directly transmitting one frame of image data, and to transmit the video signal efficiently by repeating the process. .

Problems to be Solved by the Invention D In the inter-frame encoding process, an image of a reference frame is required to decode original image data.

For this reason, in this type of video signal transmission device, for example, a frame one frame before is set as a reference frame, and instead of the difference data subjected to inter-frame coding for each predetermined frame, image data subjected to intra-frame coding is used. To be transmitted.

That is, the intra-frame encoding process is a process of encoding image data with high efficiency using the correlation within the frame. Generally, the transmission efficiency of the image data is deteriorated as compared with the case of performing the inter-frame encoding process. There is a feature that an original image can be reproduced only by transmitted image data.

Accordingly, if the image data of one frame before is subjected to intra-frame encoding processing, and the frame is set as a reference frame and the image data of the subsequent frame is subjected to inter-frame encoding processing, based on the transmitted difference data, The original image data can be reproduced.

Further, based on the image data thus reproduced, the image data of the subsequent frame can be reproduced.

However, in this type of video signal transmission device, a line is connected after the encoding process of image data is started.

Therefore, immediately after the line is connected, the inter-frame encoding process may be repeated.In this case, the transmission target reproduces the correct image until the intra-frame encoded image data is transmitted. No longer.

That is, for example, when transmitting image data that has been subjected to intra-frame encoding processing for every 128 frames, if the frame frequency of the image data is set to 10 (Hz), the talker on the transmission target side will have a maximum of about 13 seconds. Talking must be performed while monitoring an unnatural display image, which is inconvenient.

The present invention has been made in view of the above points, and aims to propose an image data encoding device capable of effectively avoiding unnatural display images and improving usability as compared with the related art. is there.

Means for Solving the Problem In order to solve such a problem, in the present invention, in an image data encoding device that encodes image data, an intra-frame encoding process or an inter-frame encoding process is performed on image data in macroblock units. Encoding means for performing any one of the encoding processing, and control means for specifying any one of the intra-frame encoding processing or the inter-frame encoding processing for the encoding means, the control means, When encoding image data to be decoded first, encoding is performed so that intra-frame encoding is performed on all macroblocks included in the image data to be decoded first. Means for controlling the means for encoding the next image data of the image data to be firstly decoded, when the macroblock included in the next image data includes intra-frame encoding. The encoding means is controlled so that an inter-frame encoding process is performed on a macroblock determined to have a smaller data amount of the encoded data subjected to the inter-frame encoding process than a data amount of the processed encoded data. Then, among the macroblocks included in the next image data, the macroblock determined to have a smaller data amount of the coded data subjected to the intra-frame coding process than the data amount of the coded data subjected to the interframe coding process is used. On the other hand, the encoding means is controlled so that the intra-frame encoding processing is performed.

F operation Since the image data to be decoded first is always subjected to the intra-frame encoding process, the receiving device can accurately decode the image data based on the intra-frame encoded image data. For the image data, the intra-frame encoding process or the inter-frame encoding process is selectively used for each macroblock so that the data amount of the encoded data is reduced, so that the next image data can be received efficiently and in a short time. Can be transmitted to

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) Configuration of Embodiment In FIG. 1, reference numeral 1 denotes a video telephone as a whole, which outputs a video signal _SV and an audio signal S _A to a transmission target via a line L1.

Further, the videophone device 1 demodulates the data transmitted from the transmission target via the line L1 and outputs a video signal _SVOUT and an audio output signal _SAOUT .

For this reason, the line connection device 2 connects the line L1 with the transmission target.
Perform connection processing work.

That is, after the call signal is output to the line L1, when the line L1 is connected to a predetermined transmission target, the incoming signal is detected and the logical level of the control signal S _CONT is raised.

Here, the control signal S _cont while the logic level is One rising is in a state capable of transmitting video signals S _V and audio signal S _A, while the logic level is falling moon is transmitted from the transmission target Indicates that data can be received.

Further, when the call is completed, the line connection device 2 outputs an on-hook signal to the line L1 and cuts off the line L1.

Video signal transmission apparatus contrast 10, after encoding processing to convert the video signal S _V to the digital signal by the transmitting section 10A, and outputs the digital audio signal multiplexed with which the caller of the image and sound Is output to the transmission target via the line connection device 2.

Further, as shown in FIG. 2, the video signal transmission device 10
The video signal S _V when processing encoded into a digital signal, after the logic level of the control signal S _CONT is One rising for a predetermined time period T, the image data by selecting the intra-frame coding process To process.

On the other hand, after the elapse of the period T, the image data is transmitted by performing the intra-frame encoding process for each predetermined frame.

As a result, immediately after the line L1 is connected, image data of several frames can be subjected to intra-frame encoding and transmitted.

Therefore, on the transmission target side, the image of the talker on the video signal transmission device 10 side can be monitored immediately after the line L1 is connected, and the conversation without discomfort can be realized.

Therefore, the usability of the video signal transmission device 10 can be improved accordingly.

Further, in the video signal transmission device 10, after the output data of the line connection device 2 is decoded by the receiving unit 10B, the video signal
An S _VOUT and an audio output signal S _AOUT are output, so that the user can talk while monitoring the image of the caller.

In (G1-1) video signal transmission apparatus Figure 3, the video signal transmission device 10, television images the caller via the JEE camera 12, a video signal S _V video signal output from the television camera 12 This is given to the processing circuit 14.

Video signal processing circuit 14 converts the video signal S _V to the luminance signal and the color difference signal into a digital signal by the analog-to-digital converter circuit.

Further, the video signal processing circuit 14 converts the luminance signal and the color difference signal converted into digital signals into CCITT (international signals).
elegraph and telephone consultative committee).

That is, after the video signal is decimated every predetermined frame to convert the frame frequency to 15 [Hz], the number of pixels in the vertical and horizontal scanning directions is reduced.

As a result, regarding the luminance signal, 352 × 288 pixels (that is, a CIF image size) or 1 in the horizontal and vertical scanning directions.
Image data D _IN of 76 × 144 pixels (i.e. in picture size of QCIF) to create an input video signal to be continuous.

Thus, the video signal is processed via the video signal processing circuit 14.
To reduce the amount of data subjected to preliminary processing S _V, the image data D _IN can be obtained input image signal consecutive in the order of line scanning.

As shown in FIG. 4, the motion vector detection circuit 16 stores the image data D _IN in a built-in scan conversion circuit once in a memory circuit, and then sequentially reads out the image data D _{IN in} a predetermined order. Rearrange the array in a predetermined order.

That is, the motion vector detecting circuit 16 divides the image of one frame (FIG. 2 (A)) into 2 × 6 blocks GOB (hereinafter referred to as block groups) in the horizontal and vertical scanning directions (FIG. 2 (B)). ).

Further motion vector detecting circuit 16, 8 × After dividing each blow poke group GOB of 11 × 3 in macroblock B _k, the more the macro block B _K in the horizontal and vertical scanning direction
FIG. 4 (C) is a diagram of deletion of dividing into minute blocks _BL in units of 8 pixels.

Thus, the video signal processing apparatus 1 transfers and processes image data in units of block groups GOB.

At this time, the image data D in the block group GOB
In _IN sequences may be made such that the image data D _IN in macroblocks B _k units are continuous, in the macroblock B _k, so that the image data D _IN is continuous small blocks B _L units in the order of raster scan Is made.

Here, the macro block B _k is
While 16 × 16 pixel image data (Y _{1 to} Y ₄ ) continuous in the horizontal and vertical scanning directions are defined as one unit, the video signal processing circuit 14 generates two corresponding color difference signals. After the data amount is reduced, the data is time-division multiplexed, and each of the small blocks B _L (C _r , C _B ) is 16 × 16.
Pixel data is allocated.

At this time, the motion vector detection circuit 16
In the reproduced 1 frame preceding image was set to the image of the reference frame, to detect a motion vector for each macroblock B _k.

Further motion vector detecting circuit 16, it is moved by the amount the reference frame image of the detected motion vector and creates picture data of 16 × 16 pixels at the position corresponding to the macroblock B _K of the current frame, the image data _DPR1 is output to the difference data creation circuit 20.

At the same time, the motion vector detection circuit 16 outputs the image data D _IND with the rearranged arrangement delayed by the time required for detecting the motion vector.

Further, the motion vector detection circuit 16 generates a header D _HET from the frame number of the image data D _IND , the address data of the block group and the macro block, the motion vector D _UG , and the sum of absolute values obtained at the time of the motion vector detection. Is output to the difference data creation circuit 20.

The difference data creation circuit 20 outputs the image data D _IND to the subsequent discrete cosine conversion circuit 22 without any processing for each predetermined frame, and thereby, for each predetermined period, the image data subjected to the intra-frame encoding processing. Can be transmitted to the transmission target.

For other than the frame to be processed intraframe coding contrast, the image data D _PRI is subtracted from the image data D _IND, and outputs the difference data D _Z obtained as a result of the discrete cosine transform circuit 22.

In this manner the video signal transmission device 10, by transmitting the difference data D _Z, the image data and inter-frame coding by switching the coding processing and interframe coding processing frame at a predetermined cycle, An input video signal is efficiently transmitted to a transmission target.

Further, at this time, the difference data creation circuit 20 outputs the image data D
The _PRI when subtracted from the image data D _IND, suppresses the high-frequency component of the image data D _PRI with a loop filter circuit as necessary.

As a result, the video signal processing apparatus 10 detects a motion vector in units of macroblocks B _k and calculates the difference data D _Z
Be treated encoded, it has been made so inconspicuous boundary between macro blocks B _k.

Further difference data generating circuit 20 is transmitted in less data than to detect the amount of data required for transmission in macro block B _k units, who has transmitted by processing frame coding is transmitted by inter-frame coding If you decide that you can,
Macro block B _{k of} a frame to be subjected to inter-frame coding
In even filed, and outputs the discrete cosine transform circuit 22 which follows without that in any way process the image data D _IND as in the case of transmitting intra-frame coding.

Thus, in the video signal transmission device 10, when performing the inter-frame encoding process, according to the amount of data required for transmission,
In addition to suppressing the high-frequency component of the image data D _UG , the processing method is switched from inter-frame encoding to intra-frame encoding, so that video signals can be transmitted efficiently using a selective prediction method. Has been made.

At the same time, the difference data creation circuit 20
After removing the data of the sum of absolute values from the header D _HET transmitted from 16, the identification data of the inter-frame encoding process and the intra-frame encoding process, and the identification of the difference data obtained through the loop filter circuit The data is added and output to the discrete cosine conversion circuit 22.

The discrete cosine conversion circuit 22 converts the video signal 2
Using the dimensional correlation, the image data D _IND and the difference data D _Z output from the difference data creating circuit 20 are subjected to discrete cosine transform (discrete cosine transcript) in units of minute blocks _BL.
sform), and outputs the resulting transform data D _DCT to the requantization circuit 24.

At this time, the discrete cosine conversion circuit 22 applies the conversion data D _DCT to the header transmitted from the difference data creation circuit 20.
And outputs the data such as the accumulated code length.

The requantization circuit 24 requantizes the transform data D _DCT and outputs it.

At this time, the requantization circuit 24 converts the converted data based on the header output from the discrete cosine conversion circuit 22.
It detects the accumulated code length and the data amount of the _DCT , detects the remaining amount of the transmission buffer circuit 33, and switches the quantization step size based on the detection result.

As a result, the requantization circuit 24 holds the data amount per frame required for transmission to a predetermined value.

Further re-quantization circuit 24, after removal of the data of the cumulative code length of the conversion data D _CT from the header output from the discrete cosine transform circuit 22, and outputs the added data of the quantization step size.

The inverse requantization circuit 26 performs an inverse conversion process with respect to the requantization circuit 24 based on the header output from the requantization circuit 24, and thereby a discrete cosine transform circuit 20 reproduced on the transmission target side. _Is converted on the transmission side.

In contrast, the discrete cosine inverse conversion circuit 28
Executes the inverse transform processing of the discrete cosine transform circuit 22 based on the header transmitted via the inverse requantization circuit 26.

Thus, in the video signal transmission apparatus 10, the input data of the discrete cosine conversion circuit 22 reproduced on the transmission target side can be reproduced on the transmission side.

That is, the video signal transmitted after being subjected to the intra-frame encoding process via the discrete cosine inverse transform circuit 28 can reproduce the image data D _IND , whereas the inter-frame encoding process can be performed. the video signal that can be reproduced difference data D _Z.

The decoder circuit 18 is composed of a frame memory circuit and an adding circuit, and switches its operation based on a header transmitted via the discrete cosine inverse conversion circuit 28.

That is, when the discrete cosine inverse transform circuit 28 outputs data subjected to intra-frame encoding processing (that is, image data obtained by reproducing the image data _DIND ), the decoder circuit 18 directly transmits the image data to the frame memory circuit. To be stored.

Further, with respect to the image data stored in the frame memory circuit, at the timing when the image data D _IN of the next frame is input to the motion vector detection circuit 16, the image data D _SV stored in the frame memory circuit is Output to the detection circuit 16.

As a result, the motion vector detection circuit 16 can detect a motion vector by setting the frame subjected to the intra-frame encoding processing as a reference frame for a frame subsequent to the frame subjected to the intra-frame encoding processing.

The decoder circuit 18 further, when the inter-frame coded data from the discrete cosine inverse transform circuit 28 (i.e., the data obtained by reproducing the difference data D _Z) is output, the image data stored in the frame memory circuit D
After the _SV is moved by the amount of the motion vector of the difference data D _Z, is stored in the frame memory circuit adds the image data obtained by the mobile to the difference data D _Z.

Thereby, the original image data of the frame subjected to the inter-frame encoding processing can be reproduced through the addition circuit,
Thus, the image transmitted to the transmission target side is sequentially reproduced,
It can be stored in a frame memory circuit.

Further, the decoder circuit 18 outputs the image data stored in the frame memory circuit at the timing when the image data D _IN of the next frame is input to the motion vector detection circuit 16 with respect to the image data stored in the frame memory circuit.
D _SV is output to the motion vector detection circuit 16.

Thus, the motion vector detection circuit 16 can sequentially detect the motion vector of the current frame using the frame one frame before as the reference frame.

Further, in the decoder circuit 18 at this time, the difference data D _Z created through a loop filter circuit,
Made to move by the amount of the motion vector by suppressing the high frequency component using a loop filter circuit, thereby switching the loop filter circuit in conjunction with the differential data creating circuit 20, conspicuous boundary between macroblocks B _k Not to be.

The variable-length encoding circuit 30 performs variable-length encoding on output data of the requantization circuit 24 obtained via the buffer circuit 32 together with motion vector data and the like, and then outputs the data to the transmission buffer circuit 33 together with the header.

The transmission buffer circuit 33 temporarily stores the output data of the variable length coding circuit 30, and then sequentially outputs the data in a predetermined order.

The buffer addition circuit 34 outputs the output data of the transmission buffer circuit 33 to the error correction circuit 36.At this time, the data amount of the input / output data of the transmission buffer circuit 33 is detected, and the transmission amount is compared with the transmission speed of the line L1. When the input data amount of the buffer circuit 33 becomes extremely small, a buffer bit is inserted between the data at a predetermined timing.

The error correction circuit 36 generates a BCH code (bose chaudhuri hocquenghe) according to the output data of the staff bit addition circuit 34.
m code) is generated and added to the output data output from the staff bit adding circuit 34 and output.

Further, the error correction circuit 36 corrects the data obtained from the transmission target via the multiplex conversion circuit 38 based on the BCH code transmitted by being added to the data, so that even if an error occurs during transmission, Image quality degradation can be effectively avoided.

The multiplex conversion circuit 38 multiplexes the digital audio signal with the output data of the error correction circuit 36, and then sends out the multiplexed data to the line L1.

Thereby, the video signal _SV and the audio signal can be efficiently transmitted to the transmission target.

At the same time, the multiplex conversion circuit 38 inputs data transmitted from the transmission target via the line L1, and separates the multiplexed video signal and digital audio signal.

Further, the separated digital audio signal is output to a predetermined decoding circuit, and the video signal is subjected to a staff bit removing circuit.
Output to 40.

The stuff bit removing circuit 40 removes the stuff bit inserted by the stuff bit adding circuit 34 on the transmission target side.

The buffer circuit 42 temporarily stores the data from which the stuff bit has been removed, and then separates the header and outputs it to the decoding circuit 44.

The decoding circuit 44 performs the reverse process of the variable length coding circuit 30 on the transmission target side.

The inverse requantization circuit 46 performs an inverse requantization process on the output data of the decoding circuit 44 based on the header input via the composite circuit 44, and thereby performs a requantization process on the transmission target side. The input data of the conversion circuit 24 is reproduced.

The discrete cosine inverse transform circuit 48 processes the output data of the inverse requantization circuit 46 based on the header in the same manner as the discrete cosine inverse transform circuit 28, thereby performing the discrete cosine transform processing on the transmission target side. Reproduce the data.

The decoder circuit 50 executes the same processing as that of the decoder circuit 18 based on the transmitted header, and thereby reproduces the encoded image data on the transmission target side.

The video signal processing circuit 52 uses an interpolation calculation method,
After the inverse processing of the video signal processing circuit 14 is performed, the resulting video signal is output to the monitor device 54, whereby the video of the communication target transmitted from the transmission target can be monitored.

(G1-2) Difference Data Creation Circuit As shown in FIG. 5, the difference data creation circuit 20 outputs the image data D _IND output from the motion vector detection circuit 16 to the selection circuit 62 via the buffer memory circuit 60. .

Thus the difference data generating circuit 20, when transmitting a video signal by processing intraframe coding, via the selector circuit 62 and the buffer memory circuit 64, and outputs the image data D _IND to the discrete cosine transformation circuit 22 followed.

Arithmetic circuitry arithmetic logic circuit 66, from the image data D _IND by subtracting the image data D _PRI to create a difference data D _Z, select the difference data D _Z via a buffer memory circuit 68 circuit 70
Output to

Thus the difference data generating circuit 20, when treated inter-frame coding for transmitting a video signal, and outputs the switching contacts of the selection circuits 62 and 70, the discrete cosine transform circuit 22 which follows the difference data D _Z.

An arithmetic logic circuit 72 having a subtraction circuit configuration inputs the image data D _PRI via a loop filter circuit 74 and outputs the image data D _IND
To create difference data D _FZ .

Further, the calculation logic circuit 72 outputs the difference data D _FZ to the selection circuit 70 via the buffer memory circuit 69, thereby switching the contacts of the selection circuit 70, and using the difference data D _FZ instead of the difference data D _Z. Discrete cosine conversion circuit 22
Output.

The squaring circuits 98, 100, and 102 respectively store image data
A square value of D _IND , difference data D _Z and difference data D _FZ is output.

Arithmetic logic circuits 104, 106, 108, and 110 having an addition circuit configuration
Are the image data D _IND , the squaring circuits 98, 100 and 102, respectively.
Is added to the output data of the latch circuits 112, 114, 116 and 118, and the addition result is added to the latch circuits 112, 1 respectively.
Output to 14, 116 and 118.

As a result, the arithmetic logic circuits 104, 106, 108, and 110 set the values of the image data D _IND and D _PRI to A and B, and set the output data value of the loop filter circuit 74 to FB, respectively, with the following equation: D _H1 = Σ (A) ... (1) _DH2 = Σ (A) ² ... (2) _DH3 = Σ ( _AB ) ² ... (3) _DH4 = Σ (A-FB) ² ... (4) The evaluation data D _H1 , D _H2 , D _H3, and D _H4 represented by the following expression are detected for each macro block, and the evaluation data D _H1 , D _H2 , D _H3, and D _H4 are output to the digital signal processing circuit 120.

Digital signal processing circuit 120 is constituted by the arithmetic processing circuit, system black poke signal S _CK in synchronization with the control circuit 122
It operates based on a predetermined reference signal output from the.

Further, the digital signal processing circuit 120 outputs the evaluation data to the header D _HET output from the motion vector detection circuit 16.
Adding D _H1, D _H2, D _H3 and D _H4, buffer memory circuit 12
The signal is output to the digital signal processing circuit 126 via 4.

Digital signal processing circuit 126 is configured by the arithmetic processing circuit like the digital signal processing circuit 120, the header D _HET
And switching control of the selection circuits 62 and 70 based on the control signal S _CONT .

That is, based on the frame number of the header D _HET , the image data D _IND is output to the discrete cosine conversion circuit 22 for each predetermined frame.

Thus, the video signal transmission device 10 can transmit a video signal by performing intra-frame encoding processing for each predetermined frame.

On the other hand, in the remaining frames, the difference data
The _DFZ is output to the discrete cosine transform circuit 22, and the video signal subjected to the inter-frame encoding process is transmitted.

At this time, the digital signal processing circuit 126 outputs the evaluation data D
_H2, D _H3 and obtain comparative results for D _H4, evaluation data when D _H2 is smaller than the evaluation data D _H3, D _H4, the image data D _IND a discrete cosine transform circuit 22 in place of the difference data D _FZ
Output to

That is, from the expressions (2), (3) and (4), the evaluation data
When D _H2 is smaller than the evaluation data D _H3 and D _H4, if transmission of image data D _IND instead difference data D _FZ, it can be transmitted by that amount efficiently image data.

Further, the digital signal processing circuit 126 outputs the evaluation data D _H4
Is smaller than the evaluation data D _H2 and D _H3 , the difference data D
And outputs the difference data D _Z to the discrete cosine transformation circuit 22 in place of the _FZ.

That connexion by the video signal be processed encoded difference data D _Z, might boundary macro block is inconspicuous, is better to the difference data D _Z instead of further difference data D _FZ processed coded In some cases, transmission can be performed efficiently.

Therefore, as in this embodiment, the evaluation data D _H1 , D _H2 , D
By switching the encoding process based on _H3 and D _H4 , a video signal can be efficiently transmitted as a whole.

On the other hand, when the logic level of the control signal S _CONT rises, the image data D _IND of several frames is output to the discrete cosine conversion circuit 22.

Thus, immediately after the connection of the line L1, the image data D _IND of several frames subjected to the intra-frame encoding processing can be transmitted to the transmission target.

Therefore, on the transmission target side, it is possible to have a conversation while monitoring the video of the talker of the video signal transmission device 10 immediately after the start of the call, and the usability of the video signal transmission device 10 can be improved.

Further, the digital signal processing circuit 126 removes the evaluation data D _H1 , D _H2 , D _H3 and D _H4 from the header D _HET output from the digital signal processing circuit 120, and then selects the selection circuit 62 and
The header D _HET is updated by adding the switching data of 70, and the updated header D _HET is output to the discrete cosine conversion circuit 22 via the buffer memory circuit 128.

In operation the above configuration of (G2) embodiment, the video signal S _V outputted from the television camera 12, preliminary processed by the video signal processing circuit 14 is the data amount is reduced subjected image CCITT recommendation Fomatsuto It is converted into data D _iN.

Image data D _IN, after the sequence of image data has been rearranged by the motion vector detection circuit 16, motion vector for each macro block is detected.

Here, based on the detected motion vector, the comparison reference image data _DPRI is generated, and the image data _DPRI is output to the difference data creation circuit 20 together with the image data _DIND .

In the difference data creation circuit 20, the intra-frame encoding process is selected at a predetermined frame cycle, and at this time, the image data D
_IND is output directly to the discrete cosine conversion circuit 22.

In inter-frame coding process on this, the image data D _IND image data D _PRI is subtracted the difference data D _Z and D _FZ is created from the difference data D _Z or D _FZ is the discrete cosine transformation circuit 22 Is output to

At this time, when the line L1 is connected and the logic level of the control signal S _CONT rises, the digital signal processing circuit 126 switches and controls the selection circuit 62, so that the image data D _IND of a plurality of frames is converted to the discrete cosine conversion circuit 22.
Is output to

As a result, the intra-frame encoding process is selected, and in the transmission target, it is possible to talk without any discomfort while monitoring the video of the caller immediately after the line L1 is connected.

The transform data D _DCT obtained through the discrete cosine transform circuit 22 is re-quantized by the re-quantization circuit 24, and is then subjected to the variable-length coding process by the variable-length coding circuit 30 through the buffer circuit 32. The output data is sequentially transmitted through a buffer circuit 33, a buffer data adding circuit 34, and an error correcting circuit 36.
And transmitted to the transmission target via the multiplex conversion circuit 38.

Further, the output data of the requantization circuit 24 is sequentially returned to the original image data by the decoder circuit 18 via the inverse requantization circuit 26 and the inverse discrete cosine transform circuit 28, and the image data is used for motion vector detection. _Is output as the image data D _SV of the previous frame.

(G3) Effects of the Embodiment According to the above configuration, the image data of several frames immediately after the connection of the line L1 is subjected to intra-frame encoding and transmitted, so that the line L1 is connected on the transmission target side. Immediately after the call, the caller can monitor the image of the caller and talk without any discomfort, and the usability can be improved accordingly.

(G4) Other Embodiments In the above-described embodiment, a case has been described in which, after the image data of several frames has been intraframe-coded and transmitted immediately after the connection of the line L1, the operation is switched to a normal operation. The present invention is not limited to this. For example, the operation may be switched to the intra-frame encoding processing operation immediately after the line L1 is cut off, and the connection of the line L1 may be waited for in the intra-frame encoding processing operation.

H Advantageous Effects of the Invention As described above, according to the present invention, the image data to be decoded first is always subjected to the intra-frame encoding process. Can be accurately reconstituted based on
In addition, for the next image data, the intra-frame encoding process or the inter-frame encoding process is selectively used for each macroblock so that the data amount of the encoded data is reduced, so that the next image data can be efficiently and quickly. The image data can be transmitted to the receiving apparatus, and thus an image data encoding apparatus which can effectively avoid unnatural images and has high transmission efficiency can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a videophone device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation thereof, FIG. 3 is a block diagram showing a video signal transmission device, and FIG.
The figure is a schematic diagram for explaining the operation of the motion vector detecting circuit, and FIG. 5 is a block diagram showing the difference data generating circuit. 1. Video telephone device 2. Line connection device 10. Video signal transmission device 2. Difference data creation circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 7/24 H03M 7/30 H04N 5/00 H04N 11/02 H04N 11/04

Claims (1)

(57) [Claims] An image data encoding apparatus for encoding image data, comprising: encoding means for performing any one of an intra-frame encoding process and an inter-frame encoding process on the image data in macroblock units; Control means for designating any one of the intra-frame coding processing and the inter-frame coding processing to the coding means, wherein the control means codes the image data to be decoded first. At the time of encoding, the encoding means is controlled so that the intra-frame encoding is performed on all macroblocks included in the image data to be firstly decoded. When encoding the next image data of the image data to be subjected to the encoding processing, the data of the encoded data subjected to the intra-frame encoding processing is included in the macroblock included in the next image data. Controlling the encoding means so that the inter-frame encoding process is performed on a macroblock determined to have a smaller data amount of the encoded data subjected to the inter-frame encoding process than the amount thereof, Among the macroblocks included in the next image data, a macroblock determined to have a smaller data amount of the coded data subjected to the intra-frame encoding process than the data amount of the coded data subjected to the inter-frame encoding process. An image data encoding device, wherein the encoding means is controlled so that the intra-frame encoding process is performed on the image data.