JP2002043869A - High-frequency integrated circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system, with which high gain and high efficiency can be obtained, regardless of the packaging style in the high-frequency integrated circuit of power amplifier or low-noise amplifier, packaged in a portable telephone set for inputting/outputting signals at a high-frequency. SOLUTION: This high-frequency integrated circuit is provided with a signal amplifier circuit 110 which is provided on a wafer 102, for amplifying an input signal and outputting the amplified input signal; a first ground terminal 113, provided on the wafer and connected with the ground electrode of the signal amplifier circuit only by wiring; and a second ground terminals 114, provided on the wafer and connected with the ground electrode of the signal amplifier circuit via a capacitively coupled circuit 115.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (Integr) used in a radio frequency (high frequency) band of a radio communication system or the like.
ated Circuit; IC).

[0002]

2. Description of the Related Art As mobile phones become smaller, lighter, have higher performance, and have lower prices, components inside the apparatuses are increasingly required to have higher efficiency and lower prices. In particular, high-frequency components such as power amplifiers that output signals need to use low-cost package members and the like while maintaining high performance in order to reduce component costs.

[0003] Power amplifiers usually used in the GHz band include GaAs-based Schottky gate field-effect transistors (metal semiconductor FETs; MESFETs) and GaAs, whose characteristics are obtained at high frequencies.
s-based heterojunction bipolar transistor
An IC chip using an amplifying element such as n bipolar transistor (HBT) is used. Since this element is expensive in terms of wafer cost and manufacturing cost, it is general to reduce the package mounting cost in order to keep the power amplifier product price low. An example of a low-cost package is a plastic package.

FIG. 13 is a schematic view of a conventional plastic package. An IC chip 102 is mounted on a bed 101 of a lead frame 100, and an outer region of the IC chip is covered with a mold resin (epoxy resin) 103. This plastic package is most suitable for cost reduction because it can be made of inexpensive materials such as epoxy resin and can be mass-produced on a mass production line.

A method for mounting an IC chip on a plastic package is as follows. An IC chip is fixed to a bed 101 and an IC power supply lead wire 104 and an input lead wire 1 are connected by wires 130.
05 and output leads 106 and IC chip pads 107
Make an electrical connection with the Similarly, the ground pad 108 of the IC chip is electrically connected to the ground lead wire 109 of the lead frame by the wire 130. After these electrical connections are made, the mold resin 1 fixed to the formwork
03 is injected to complete the plastic package. In this way, plastic packages are simple and suitable for mass production,
Because the material cost is low, it is most suitable for mass-produced products such as mobile phones.

[0006] As described above, the plastic package is very suitable for use in mobile phones and the like because both the mounting cost and the material cost can be extremely reduced. However, when a high-frequency integrated circuit is mounted on a plastic package, especially when a circuit that requires high gain and high efficiency, such as a power amplifier, is mounted on the plastic package, the characteristics of the plastic package as a whole compared to the characteristics of the IC chip alone Is deteriorated.

Hereinafter, the above-mentioned problem will be described with reference to FIG. In order to mount the IC chip 102 to the ground lead wire 109 by wire, the ground pad 10 on the IC chip is
When the grounding direction from 8 to the outside of the mold resin 103 is viewed, the grounding impedance Z appears to increase in proportion to the frequency due to the inductive nature of the wire 130. Here, a block diagram of a conventional IC chip is shown in FIG. In the conventional IC chip, the ground electrode of the signal amplifier circuit 110 and the ground terminal 113 of the IC chip are connected only by wiring.

Further, since a plastic package always has a ground capacitance, a capacitive connection from the ground pad 108 of the IC chip to a ground point outside the package (for example, a ground point of a printed circuit board on which the plastic package is mounted). Are combined. For this reason, when viewed from the IC chip 102, the wire 130 acts in parallel resonance due to the inductivity and the ground capacitance of the wire 130, so that the ground impedance increases as the operating frequency band of the amplifying element in the IC chip increases. Will be visible. As the ground impedance increases, the gain of the amplifying element in the IC chip decreases, and the output power ((output power) = (input power) x
(Gain)) and efficiency. Degradation of output power is a major problem in power amplifiers, and measures need to be taken.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency integrated circuit in which the above-mentioned deterioration of output power is reduced.

[0010]

According to a first aspect of the present invention, there is provided a signal amplification circuit provided on a semiconductor substrate and amplifying an input signal and outputting the amplified input signal; A first ground terminal connected to the ground electrode of the signal amplifier circuit only by wiring; and a first ground terminal provided on the semiconductor substrate and connected to a ground electrode of the signal amplifier circuit via a capacitive coupling circuit. This is a high-frequency integrated circuit having two ground terminals.

A second invention is the high-frequency integrated circuit according to the first invention, wherein the capacitance value of the capacitive coupling circuit is variable.

A third invention is the high-frequency integrated circuit according to the first invention, wherein the first and second ground terminals and a circuit outside the semiconductor substrate are connected using a wire. .

According to a fourth aspect of the present invention, the reciprocal of the square root of the product of the induction value of the wire and the capacitance value of the capacitive coupling circuit is a value close to the used angular frequency band of the signal amplifier circuit. A high-frequency integrated circuit according to a third aspect.

According to a fifth aspect of the present invention, in the high frequency integrated circuit according to the first aspect, the second ground terminal is further connected to a ground electrode of the signal amplifier circuit via a negative resistance circuit. It is.

According to a sixth aspect of the present invention, in the negative resistance circuit, a parasitic resistance value on the ground electrode side of the signal amplifier circuit and an absolute value of the resistance are substantially equal and have a negative sign resistance value. A high-frequency integrated circuit according to a fifth aspect of the invention.

A seventh invention is provided on a semiconductor substrate,
And a signal amplification circuit that amplifies an input signal and outputs the amplified input signal; provided on the semiconductor substrate;
A first ground terminal connected to the ground electrode of the signal amplifier circuit only by wiring; a second ground terminal provided on the semiconductor substrate and connected to the ground electrode of the signal amplifier circuit via a capacitive coupling circuit A high-frequency integrated circuit having a terminal, a lead frame on which the high-frequency integrated circuit is mounted, a first wire connecting the first ground terminal to a first ground lead of the lead frame, a second ground terminal, and the lead A semiconductor device comprising a second wire connecting a second ground lead of a frame, and a mold resin covering the high-frequency integrated circuit.

According to the present invention, even if the ground impedance of the path connected to the first ground terminal increases in the use frequency band of the amplifying transistor constituting the signal amplifying circuit, the second
In the path connected to the ground terminal, the relationship between the parasitic inductance component at the time of mounting and the capacitive coupling circuit acts in series resonance, so that the ground impedance can take a minimum value. Accordingly, it is possible to reduce the deterioration of the gain due to the parasitic component (ground capacitance) when the IC chip is mounted on the plastic package, and the deterioration of the output power.

In particular, the capacitance value C of the capacitive coupling circuit depends on the operating frequency f of the amplifying transistor constituting the signal amplifier circuit and the IC.
Using the inductor value L from the chip pad to the ground electrode outside the plastic package

[0019]

(Equation 1)

It is effective to set the capacitance value to a value close to the above value.

When a variable capacitance coupling circuit is used as the capacitance coupling circuit, the capacitance of the variable capacitance coupling circuit can be adjusted. Depending on the conditions, if the wiring of the motherboard (printed circuit board) on which the plastic package is mounted has inductive properties) or if the frequency band used changes, the capacitance value of the variable capacitive coupling circuit is adjusted using equation (1). By doing so, the series resonance frequency can be set freely, so that ideal characteristics of the amplifier element can be obtained regardless of the mounting conditions and use conditions. Here, the ideal characteristic of the amplifier element means that the value of the ground impedance is only the emitter resistance in the case of a bipolar transistor and only the source resistance in the case of a field effect transistor.

In the case where there is a path connected to the second ground terminal via the capacitive coupling circuit and the negative resistance generating circuit, the value of the negative resistance is changed to the resistance value parasitic to the ground terminal electrode inside the amplifying transistor. Can be set to a negative value with an absolute value approximately equal to For this reason, the emitter resistance included in the bipolar transistor or the source resistance included in the field-effect transistor can be canceled, and the resistance can be made closer to no resistance. As a result, it is possible to remove the attenuation that has conventionally been reduced by the emitter resistance or the source resistance from the gain characteristics of the amplifier element.

[0023]

Embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from actual ones. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

(First Embodiment) FIG. 1 is a block diagram of a high-frequency integrated circuit according to a first embodiment of the present invention. A portion surrounded by a dotted frame is a high-frequency integrated circuit (IC chip) 102 formed on a semiconductor substrate. Inside the IC chip 102 is a signal amplification circuit 110. The signal amplification circuit 110
For example, if the semiconductor substrate of the IC chip is a GaAs substrate,
GaAs Schottky gate field-effect transistor (Metal
-semiconductor FET; MESFET) and GaAs heterojunction bipolar transistor
r; HBT). Signal input terminal 11
1, signal output terminal 112, first ground terminal 113 and second
The ground terminals 114 are bonding pads (hereinafter simply referred to as pads) on the IC chip 102, respectively. The ground electrode of the signal amplifier circuit and the first ground terminal 113 are connected only by wiring, and the ground electrode of the signal amplifier circuit 110 and the second
The ground terminal 114 is short-circuited in an AC manner via a capacitive coupling circuit 115.

According to the present embodiment, even if the ground impedance of the path connected to the first ground terminal 113 increases in the operating frequency band of the amplifying element, the path connected to the second ground terminal 114 is formed by using a plastic Since the relationship between the parasitic inductance component and the capacitive coupling circuit when mounted on the package acts in series resonance, the ground impedance can take a minimum value. Therefore, depending on the ground capacity
The gain of the amplifying element in the IC chip 102 hardly deteriorates, and the deterioration of the output power can be reduced.

In particular, when the present embodiment is applied to a package having a large inductivity, such as an induction value of a bonding wire during mounting and an induction value of a lead frame, such as a plastic package, the influence of the plastic package can be completely eliminated. Gain characteristics and efficiency can be obtained.

FIG. 2 is a specific circuit diagram of the circuit configuration of FIG. The inside of the dotted line indicates the IC chip 102, and the IC chip 1
02, first and second amplifying transistors (bipolar transistors) Q1 and Q2, an AC coupling capacitor Cc
1, Cc2, Cc3, signal blocking inductors Lv1, Lv2, Lv3, Lv4, and grounding capacitors Cg1, Cg connected in series to the grounding electrodes (emitter electrodes) of the amplifying transistors Q1, Q2, respectively.
It consists of two. The ground capacitors Cg1 and Cg2 correspond to the capacitive coupling circuit 115 in FIG. The portions indicated by squares in the figure are the pads of the IC chip. RFin is a signal input pad, RFout is a signal output pad, and Vb1, Vc1, Vb2, and Vc2 are bias power supply pads of each transistor. The inductors Lw1, Lw2, Lw3, Lw4 of the ground wires outside the dotted frame mean bonding wires when the IC chip is mounted on a plastic package.
The ground pads (118, 119) inside the IC chip and the ground electrode outside the IC chip are connected. That is, when the IC chip is mounted, the inductor always enters between the ground pad inside the IC chip and the ground electrode outside the IC chip.

Although the value of the inductor of the ground wire greatly varies depending on the mounting form, when a plastic package is used, the inductance generally has a value of about 0.5 nH to 2 nH.

In this embodiment, the amplifying transistor Q shown in FIG.
Since there are capacitors Cg1 and Cg2 connected in series to the ground electrode (emitter electrode) of Q1 and inductors Lw2 and Lw4 of the ground wire, series resonance is used for Cg1 and Lw2 and Cg2 and Lw4 based on equation (1). It can be generated at frequency f. Therefore, even when mounted on a plastic package, the ground impedance (Z in FIG. 2) is only the wiring resistance of a wire or the like, and can ideally be reduced to 0Ω. That is, no negative feedback is applied to the transistor even at the time of mounting, and the gain characteristic of the transistor does not deteriorate. Also, the efficiency is improved.

FIG. 3 is a diagram in which the high-frequency integrated circuit (IC chip) 102 according to the present embodiment is mounted on a plastic package using a lead frame. The first ground lead 116 and the second ground lead 11 are used as ground leads.
7 are used. The first ground lead 116 corresponds to the ground wire inductors Lw1 and Lw3 of FIG. 2, and the second ground lead 117 corresponds to the ground wire inductors Lw2 and Lw2 of FIG.
It corresponds to Lw4.

Conventionally, in order to minimize the influence of the bonding wire, it is necessary to use the bed below the IC as a ground electrode and to take out the ground electrode from the bed to the back surface. For this reason, a lead frame dedicated to the IC is required, and the process of the mold package is complicated, which has contributed to an increase in cost.

By using this embodiment, a normal lead wire (lead wire of a lead frame) is used as a ground lead wire.
Can be used, and a general lead frame and a mounting process can be used, so that a simple and low-cost product can be obtained.

FIG. 4 is a schematic diagram of a parasitic component due to mounting inside the plastic package in the present embodiment. Here, the components from the second ground pad 119 of the IC chip 102 to the second ground lead 117 are shown. The capacitor and the inductor are connected in series by the capacitor of the capacitive coupling circuit 115 and the inductor of the bonding wire 130. The ground capacitance 200 of the IC chip is shown in parallel connection with the capacitor of the capacitive coupling circuit 115.

FIG. 5 shows this embodiment (FIG. 4) and a conventional example (FIG. 1).
It is a figure which shows the characteristic of the ground impedance at the time of mounting of 4). The solid line is the ground impedance of the present embodiment,
The broken line is the conventional ground impedance. In the conventional example (FIG. 14), the influence of the inductance (0.2 to 0.3 nH) of the bonding wire 130 of about 1 mm and the parallel connection of the parasitic capacitance (ground capacitance) 200 (several tens of pF) from the chip to the ground together with the frequency are provided. The ground impedance increases, parallel resonance occurs at a certain frequency, and the impedance becomes infinite. For example, when the used frequency band is 2 GHz and the inductance is 0.2 to 0.3 nH, the ground impedance is as high as about 3Ω.

In this embodiment (FIG. 4), the value of the capacitor is set so that the capacitor (capacitive coupling circuit) 115 formed inside the IC chip and the inductance of the bonding wire 130 form a series resonance at the operating frequency f. For,
The ground impedance becomes substantially zero. For example, when the operating frequency f is 2.0 GHz and the inductance is 1 nH, the capacitor is set to 6.3 pF. Note that the value of the ground capacitance is extremely large when viewed from the operating frequency f, so that the current hardly flows to the ground capacitance 200 side. Therefore, in this embodiment, since the frequency band other than the used frequency band f is not used, the ground capacitance 200 can be ignored, and the capacitance coupling circuit 11 can be used.
5 and the wire 130 can be regarded as a series circuit. If the value of the capacitive coupling circuit 115 and the value of the wire 130 are set so as to cause series resonance in the used frequency band f, the ground impedance Z becomes

[0036]

(Equation 2)

The minimum point is reached, and the circuit can operate stably. Here, R indicates the resistance of the entire series circuit of the capacitive coupling circuit 115, the wire 130, and the emitter resistance of the amplifying element. Further, as shown in FIG. 5, the ground impedance can be obtained in a bandpass shape with respect to the used frequency band Δf.
It is also possible to remove unnecessary signals.

FIG. 6 shows this embodiment (FIG. 4) and a conventional example (FIG. 1).
FIG. 4 is a diagram showing gain characteristics and efficiency characteristics of the amplifier element when mounting is performed in 4). A solid line indicates the present embodiment, and a broken line indicates a conventional example. The measurement was performed under the same input / output conditions and using the same amplifier IC. The measurement frequency is 2.0 GHz which is the operating frequency band f. The ratio of the output power to the input power, that is, the gain of the present embodiment is about 12 dB better than that of the conventional example. This is a value determined by the ratio of the ground impedance including the resistance of the transistor element of the present embodiment and the conventional example in the operating frequency band f of the amplifying element.
Assuming that the ground impedance in GHz is 3Ω, the increase in the ground impedance due to the wire inductance is about 12 dB, which indicates that the present embodiment requires the ground impedance to be the minimum value of only the element parasitic resistance.

Further, since the output power increases under the same conditions, as shown in FIG. 6, the present embodiment can also eliminate the influence of the wire inductance on the efficiency, thereby achieving high efficiency. .

FIG. 7 is a schematic sectional view of the capacitive coupling circuit 115 of FIG. In the present embodiment, as the capacitive coupling circuit 115, a metal-insulator-metal (MIM) capacitor including the first wiring layer 304, the second insulating layer 303, and the second wiring layer 305 is used. For example, the semiconductor substrate 301 is a GaAs substrate, the first insulating layer 302 is an SiO ₂ layer, and the second insulating layer 303
Is an SiO ₂ layer, the first wiring layer 304 is an Au layer, and the second wiring layer 305 is an Au layer. The first wiring layer 304 is connected to the ground electrode of the amplifying element in the signal amplifier circuit 110 of FIG. 1, and the second wiring layer 305 is connected to the second ground terminal 114 of FIG.

(Second Embodiment) FIG. 8 is a schematic block diagram of a high-frequency integrated circuit according to a second embodiment of the present invention.
The same components as those in FIG. 1 are referred to the description of FIG. 1 and are omitted here. FIG. 1 differs from FIG.
In that the capacitive coupling circuit 115 is replaced with a variable capacitive coupling circuit 120, and an adjustment terminal 121 for changing the capacitance value of the variable capacitive coupling circuit is provided.
The adjustment terminal is a bonding pad on the IC chip and can be electrically connected to the outside of the IC chip. Further, when the variable capacitance coupling circuit is a variable diode, the adjustment terminal is a voltage terminal.

Also in this embodiment, as described in the first embodiment, the deterioration of the gain of the amplifying element in the IC chip due to the ground capacitance hardly occurs, and the deterioration of the output power can be reduced. Further, since the capacitance value of the variable capacitance circuit can be adjusted after mounting the IC chip on the plastic package, the deterioration of the output power can be reduced more accurately than in the first embodiment.

FIG. 9 is a specific circuit diagram of the circuit configuration of FIG. The variable capacitance coupling circuit 120 in FIG. 8 corresponds to the ground capacitors Cg3 and Cg4. The same components as those in FIG. 2 are referred to the description of FIG. 2 and are omitted here. The difference from FIG. 2 is that the capacitance values of the grounding capacitors Cg3 and Cg4 change. With such a configuration, the ground inductances Lw1 to Lw4 depend on the mounting form.
Should change the capacitance value accordingly,
The minimum ground impedance state can be realized regardless of the mounting form. Further, even when the use frequency f of the transistors Q1 and Q2 is changed, the capacitance value may be changed in accordance with the change, which is excellent in versatility.

FIG. 10 shows the variable capacitance coupling circuit 120 of FIG.
FIG. In the present embodiment, the variable capacitance coupling circuit
As a path 120, a P layer 406 (impurity is boron (B),
The impurity concentration is 1 × 10^Fifteencm^-3), P⁺Layer 407 (impurity
Is boron (B) and the impurity concentration is 1 × 10¹⁷cm^-3), N⁺
Layer 408 (impurity is arsenic (As), impurity concentration is 1 × 1
0¹⁸cm^-3) And N layer 409 (impurity is arsenic (As),
The impurity concentration is 1 × 10^{1 6}cm^-3Varactor composed of
A diode was used. For example, the semiconductor substrate 401 is GaAs
The substrate and the insulating layer 402 are made of SiO_TwoLayer, the first wiring layer 404
The Au layer and the second wiring layer 405 are Au layers. First wiring layer
Reference numeral 404 denotes the ground of the amplification element in the signal amplification circuit 110 of FIG.
The second wiring layer 405 is connected to the second ground terminal 114 of FIG.
Connected to 8 is a second wiring layer
What is necessary is just to be connected somewhere in 405.

(Third Embodiment) FIG. 11 shows a third embodiment of the present invention.
1 is a block diagram of a high-frequency integrated circuit according to an embodiment. The same components as those in FIG. 1 are referred to the description of FIG. 1 and are omitted here. 1 in that a negative resistance circuit 122 is provided between the capacitive coupling circuit 115 and the second ground terminal 114. Also in the present embodiment, as described in the first embodiment, the deterioration of the gain of the amplifying element in the IC chip due to the ground capacitance hardly occurs, and the deterioration of the output power can be reduced.

Further, in this embodiment, an amplifying element in an IC chip (here, described as a bipolar transistor)
Absolute value corresponding to the parasitic resistance (emitter resistance RE) of
A negative resistance circuit 122 having a negative sign is provided, and the ground impedance is set to -RE at the used frequency f. In this case, when the ground impedance is viewed from the intrinsic transistor region of the transistor Q1, it becomes 0Ω, and an ideal signal amplifier circuit without negative feedback can be provided. That is, by providing the negative resistance circuit 122, it is possible to obtain the gain characteristic inherent in the intrinsic transistor region.

FIG. 12 is a circuit diagram of the negative resistance circuit 122 of FIG. The terminal 501 is connected to the signal amplification circuit 11 shown in FIG.
The terminal 114 is the second ground terminal in FIG. 11, which is connected to the ground electrode of the amplifying element within 0 via a capacitive coupling circuit 115. 502 is a bipolar transistor, 503 is a capacitor, and 504 is a coil.

The impedance Z when viewed from the terminal 501 toward the second ground terminal 114 is represented by the following equation.

[0049]

(Equation 3)

Here, gm is the bipolar transistor 5
02 is the transconductance, C is the capacitance of the capacitive element 503, and L is the inductance of the coil 504.

Therefore, if [ωL−1 / (ωC)] is set to be negative, that is, if ω ² LC is set to less than 1, the negative resistance circuit 122 may generate a negative resistance. it can.

(Other Embodiments) The first to third embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments. In the present invention, the above-described embodiments can be appropriately modified without departing from the spirit thereof. For example, the capacitive coupling circuit 115 of FIG.
May be replaced by the variable capacitance coupling circuit 120 described above.

[0053]

According to the present invention, it is possible to provide a high-frequency integrated circuit with reduced output power deterioration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a high-frequency integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the circuit configuration of FIG.

FIG. 3 is a plastic package diagram on which the high-frequency integrated circuit according to the first embodiment is mounted.

FIG. 4 is a schematic diagram of a parasitic component due to mounting inside a plastic package in the first embodiment.

FIG. 5 is a diagram showing the relationship between frequency and impedance.

FIG. 6 is a diagram showing a relationship among input power, output power, and efficiency.

FIG. 7 is a schematic sectional view of the capacitive coupling circuit 115 of FIG. 1;

FIG. 8 is a block diagram of a high-frequency integrated circuit according to a second embodiment of the present invention.

FIG. 9 is a specific circuit diagram of the circuit configuration of FIG. 8;

FIG. 10 is a schematic sectional view of the variable capacitance coupling circuit 120 of FIG. 8;

FIG. 11 is a block diagram of a high-frequency integrated circuit according to a third embodiment of the present invention.

FIG. 12 is a circuit diagram of a negative resistance circuit 122 shown in FIG. 11;

FIG. 13 is a schematic view of a conventional plastic package.

FIG. 14 is a schematic view of a parasitic component caused by mounting inside a conventional plastic package.

FIG. 15 is a block diagram of a conventional high-frequency integrated circuit.

[Explanation of symbols]

Q1 to Q4 Transistors Cc1 to Cc3 AC coupling capacitor Cg1 to Cg4 Capacitor Lv1 to Lv4 Signal blocking inductor Lw1 to Lw4 Ground wire inductor RFin Signal input pad Vb1, Vb2 Base power supply voltage pad Vc1, Vc2 Collector power supply voltage pad REFERENCE SIGNS LIST 100 Lead frame 101 Bed 102 IC chip 103 Mold resin 104 IC power supply lead 105 Input lead 106 Output lead 107 Pad 108 Ground pad 109 Ground lead 110 Signal amplification circuit 111 Signal input terminal 112 Signal output terminal 113 First ground terminal 114 second ground terminal 115 capacitive coupling circuit 116 first ground lead 117 second ground lead 118 first ground pad 119 second ground pad 120 variable capacitance coupling circuit 121 adjustment terminal 122 negative resistance circuit 130 wire 200 ground The amount 301, 401 semiconductor substrate 302 first insulating layer 303 second insulating layer 304 and 404 the first wiring layer 305, 405 the second wiring layer 402 insulating layer 406 P layer 407 P ⁺ layer 408 N ⁺ layer 409 N layer 501 terminals 502 Bipolar transistor 503 Capacitance element 504 Coil

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AC01 AC03 AC05 AC12 AC15 AV04 AZ06 BE07 BE09 BH02 BH03 BH19 DF01 DF02 EZ01 EZ20 5J092 AA01 CA36 FA16 HA06 HA11 HA25 HA29 HA33 QA02 QA03 QA04 SA13 TA01 TA02 TA03

Claims (7)

[Claims] A signal amplification circuit provided on a semiconductor substrate for amplifying an input signal and outputting the amplified input signal; and a ground electrode provided on the semiconductor substrate for the signal amplification circuit. A high-frequency integrated circuit comprising: a first ground terminal connected only by wiring; and a second ground terminal provided on the semiconductor substrate and connected to a ground electrode of the signal amplification circuit via a capacitive coupling circuit. 2. The high-frequency integrated circuit according to claim 1, wherein the capacitance value of the capacitive coupling circuit is variable. 3. The high-frequency integrated circuit according to claim 1, wherein the first and second ground terminals are connected to a circuit outside the semiconductor substrate using a wire. 4. A reciprocal of a square root of a product of an induction value of the wire and a capacitance value of the capacitive coupling circuit is a value close to an angular frequency band used by the signal amplifying circuit.
A high-frequency integrated circuit according to claim 1. 5. The high-frequency integrated circuit according to claim 1, wherein said second ground terminal is further connected to a ground electrode of said signal amplifier circuit via a negative resistance circuit. 6. The negative resistance circuit according to claim 1, wherein a parasitic resistance value on the ground electrode side of the signal amplification circuit is substantially equal to an absolute value of the resistance, and has a negative sign resistance value. Item 6. The high-frequency integrated circuit according to Item 5. 7. A signal amplifier circuit provided on a semiconductor substrate and amplifying an input signal and outputting the amplified input signal; and a ground electrode provided on the semiconductor substrate and connected to the ground electrode of the signal amplifier circuit. A first ground terminal connected only by wiring, and a second ground terminal provided on the semiconductor substrate and connected to a ground electrode of the signal amplification circuit via a capacitive coupling circuit
A high-frequency integrated circuit having a ground terminal; a lead frame on which the high-frequency integrated circuit is mounted; a first wire connecting the first ground terminal to a first ground lead wire of the lead frame; A semiconductor device comprising: a second wire connecting a second ground lead of a lead frame; and a mold resin covering the high-frequency integrated circuit.