JP2002043615A - Led array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance productivity and to reduce a manufacturing cost by reducing a film thickness as a whole, shortening a film growing time, and decreasing a consumption of a raw material. SOLUTION: A buffer layer 2 and a one-conductivity type semiconductor layer 3 (an ohmic contact layer 3a, a single layer stressed layer or a stressed superlattice layer 3a and a clad layer (electron injected layer) 3c) are sequentially laminated on a substrate 1. A heat cycle for reducing a dislocation density is conducted during formation or after formation of the layer 3a, and thereby at least a part of the layer region of the layer 3a is subjected to a heat cycle treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging a plurality of island-shaped semiconductor layers formed by sequentially laminating a semiconductor layer of one conductivity type and a semiconductor layer of the opposite conductivity type on a substrate. The present invention relates to an LED array suitable for a light source and the like.

[0002]

2. Description of the Related Art A conventional LED array is shown in FIGS. FIG. 3 is a sectional view, and FIG. 4 is a plan view.

[0003] Reference numeral 21 denotes a substrate made of a single crystal semiconductor, a single crystal insulator, or the like.
And the one conductivity type semiconductor layer 23 and the opposite conductivity type semiconductor layer 24
It has a configuration in which layers are sequentially stacked by an OCVD method or the like, and a plurality of such island-shaped semiconductor layers are arranged.

[0004] The buffer layer 22 is for reducing dislocations and comprises a first buffer layer 22a and a strained superlattice layer or a single-layer strained layer 22b. After forming the buffer layer 22, a one-conductivity-type semiconductor layer 23 and a reverse-conductivity-type semiconductor layer 24 are formed. The one conductivity type semiconductor layer 23 includes a first ohmic contact layer 23a and a first cladding layer 23b, and the opposite conductivity type semiconductor layer 24 includes a light emitting layer 24a, a second cladding layer 24b, and a second ohmic contact layer 24c. Consists of

The first ohmic contact layer 23a
Is connected to the common electrode 26, and the individual electrode 25 is connected to the second ohmic contact layer 24c.

Reference numerals 27a and 27b denote protective films made of a silicon nitride film or the like.
By arranging a plurality of ED chips, an LED array is formed.

As described above, the buffer layer 22 is formed on the substrate 21.
However, if the buffer layer 22 is not provided, a semiconductor layer is formed on the substrate 21 using a different material from the semiconductor layer. Dislocations occur in the semiconductor layer due to the difference. Therefore, the dislocation density is reduced by providing the buffer layer 22 between the substrate 21 and the semiconductor layer.

As a method for lowering the dislocation density with the buffer layer 22, two-step growth, thermal cycling, strained superlattices, insertion of a single-layer strained layer having a different lattice constant, and the like have been proposed (see JP-A-8-330234). ).

FIG. 5 shows an example of a temperature profile when a GaAs buffer layer 22 is formed on a Si substrate.

[0010] The horizontal axis is the time required for the heating cycle,
The vertical axis is the heating temperature.

The substrate 21 is placed in a hydrogen atmosphere at 800 to 100
After pretreating at 0 ° C. and forming an amorphous layer of about several hundreds of degrees at a low temperature of 400 to 500 ° C., a buffer layer is formed at a normal single crystal film growth temperature (such a two-stage film forming). The process is called two-step growth). Then, the film formation is temporarily interrupted, and a thermal cycle in which the temperature is raised and lowered is repeated to lower the dislocation density, and further, a strained superlattice or a single-layer strained layer is formed.

By performing such a thermal cycle or forming such a strained layer, as shown in FIG. 6, the dislocation reduction effect becomes more remarkable as the thickness of the buffer layer becomes larger. In the figure, the horizontal axis indicates the thickness of the buffer layer, and the vertical axis indicates the dislocation density.

[0013]

However, a buffer layer is formed by two-step growth to effectively reduce dislocations. On the other hand, when the thickness of the buffer layer increases, the film forming time increases. However, there is a problem that the raw material consumption is increased, and as a result, the productivity is reduced and the production cost is increased.

The inventor of the present invention has made intensive studies in view of the above circumstances. As a result, an island-shaped semiconductor layer is formed on a substrate by using a material different from that of this substrate. In an LED array in which a plurality of layers are arranged by laminating, and furthermore, a part of one conductive semiconductor layer is exposed and individual electrodes and a common electrode are both arranged on the substrate surface, a thermal cycle for reducing dislocation density is performed by ohmic contact. The film thickness of the buffer layer is reduced while maintaining the dislocation density by performing the same during the formation of the layer and also after forming the ohmic contact layer to form the distorted superlattice or the single-layer strained layer for dislocation reduction. And that productivity can be improved.

The present invention has been accomplished based on the above findings, and an object of the present invention is to provide a low-cost LED array by improving the productivity and reducing the manufacturing cost.

[0016]

In the LED array of the present invention, a buffer layer, a one-conductivity-type semiconductor layer, and a reverse-conductivity-type semiconductor layer are sequentially laminated on a substrate by using a material different from that of the substrate. A plurality of island-shaped semiconductor layers are arranged, and a part of each one-conductivity-type semiconductor layer is exposed to provide an individual electrode and a common electrode. A layer, a single-layer strained layer or strained superlattice layer, and a clad layer are sequentially laminated, and at least a part of the ohmic contact layer is subjected to a thermal cycle treatment.

According to the LED array of the present invention, a buffer layer is formed on a substrate by, for example, two-step growth, and an ohmic contact layer of a semiconductor layer of one conductivity type is formed. During the film formation, the film formation is temporarily interrupted, and a thermal cycle of repeating a temperature rise and a high temperature is performed to lower the dislocation density, thereby performing a heat cycle process on at least a part of the ohmic contact layer, Then, the formation of the contact layer is continued. Then, a strained superlattice or a single-layer strained layer is formed. Thereafter, a cladding layer of the semiconductor layer of one conductivity type and a semiconductor layer of the opposite conductivity type are formed.

With such a layer structure, even if the thickness of the buffer layer is reduced to the same extent as the conventional one, the thermal cycling process is performed on the ohmic contact layer thereon, so that the dislocation density is small. A semiconductor layer is obtained, and as a result,
As a whole, the film thickness can be reduced, and as a result, the film formation time is shortened and the consumption of raw materials is reduced,
As a result, productivity is improved and manufacturing costs are reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of an LED array according to the present invention. FIG. 1 is a sectional view thereof, and FIG. 2 is a plan view thereof.

In FIG. 1, 1 is a substrate, 2 is a buffer layer, 3 is a semiconductor layer of one conductivity type, 4 is a semiconductor layer of opposite conductivity type, and 5
Is an individual electrode, and 6 is an insulating film.

The substrate 1 comprises a single crystal semiconductor substrate such as silicon (Si) or a single crystal insulating substrate such as sapphire (Al ₂ O ₃ ). In the case of silicon, the (100) plane is <01
A substrate or the like turned off by 2 to 7 ° in the 1> direction is preferably used. In the case of sapphire, a C-plane substrate is preferably used.

The buffer layer 2 is formed to a thickness of about 1 to 4 μm using aluminum gallium arsenide or the like by using two-step growth or the like.

The buffer layer 2 is provided to prevent misfit dislocation due to mismatch of the lattice constant between the substrate 1 and the semiconductor layer, and may not particularly contain semiconductor impurities.

The one-conductivity-type semiconductor layer 3 comprises an ohmic contact layer 3a, a single-layer strained or strained superlattice layer 3b, and a cladding layer (electron injection layer) 3c.

Ohmic contact layer 3a, clad 3
c is formed to a thickness of about 0.1 to 1.0 μm, and the single-layer strained layer or strained superlattice layer 3b is formed to a thickness of 0.01 to 1.0 μm.
It is formed to a thickness of about 0.5 μm.

Each of the ohmic contact layer 3a, the single-layer strained layer or strained superlattice layer 3b, and the clad layer 3c
Each gallium arsenide, indium gallium arsenide, are formed like an aluminum gallium ^{arsenide, 1 × 10 16 ~10 1 8} atoms of one conductivity type semiconductor impurity such as silicon
/ Cm ³ .

As described above, the ratio of the In composition of the single-layer strained layer or strained superlattice layer 3b made of indium gallium arsenide is preferably about 0.05 to 0.3. In the cladding layer 3c, the Al composition ratio is preferably set to about 0.2 to 0.5.

In the present invention, the thermal cycle for reducing the dislocation density is performed during or after the formation of the ohmic contact layer 3a, whereby the thermal cycle is performed on at least a part of the ohmic contact layer 3a. Has been treated.

This thermal cycling process utilizes the difference in the coefficient of thermal expansion between the substrate material and the grown film, and repeatedly raises and lowers the temperature, thereby applying stress to the film and causing penetration due to lattice mismatch. This is performed for the purpose of bending dislocations and reducing the dislocation density in the light emitting layer. As shown in FIG. 5, a thermal cycle in which the temperature is raised and lowered repeatedly after the two-step growth may be used. It is not limited to a cycle.

The single-layer strained layer or strained superlattice layer 3b also inserts a layer having a different lattice constant to apply stress to the film and reduce threading dislocations reaching the light emitting layer by bending dislocations at the layer interface. is there.

The opposite conductivity type semiconductor layer 4 includes the light emitting layer 4a, the second
And a second ohmic contact layer 4c.

The light emitting layer 4a and the second cladding layer 4b have a thickness of 0.1 mm.
The ohmic contact layer 4c is formed to a thickness of about 0.01 to 0.1 μm.

The second ohmic contact layer 4c is made of gallium arsenide or the like. The light emitting layer 3a and the second cladding layer 3b preferably have different mixed crystal ratios of aluminum arsenide (AlAs) and gallium arsenide (GaAs) in consideration of an electron confinement effect and a light extraction effect.

The light emitting layer 3a and the second cladding layer 3b contain opposite conductivity type semiconductor impurities such as zinc (Zn) in an amount of 1 × 10 ¹⁶ to 1 × 10 ^16.
0 ¹⁸ contained about atoms / cm ^3, the second ohmic contact layer 3c is may contain about ^{1 × 10 19 ~10 20 atoms /} cm 3 the opposite conductivity type semiconductor impurity such as zinc.

The insulating films 7a and 7b are made of silicon nitride or the like and have a thickness of about 2000 to 5000 °. The individual electrode 5 and the common electrode 6 are made of gold / chrome (Au / Au).
Ge / Cr) or the like, and is formed to a thickness of about 1 μm.

In the LED array of the present invention, as shown in FIG.
Are arranged in a line on the substrate 1 and a current is passed between the individual electrode 5 and the common electrode 6 to selectively emit light from each of the light emitting diodes. Used as a light source for exposure.

Next, a method for manufacturing the above-described LED array will be described. First, a buffer layer 2, one conductivity type semiconductor layer 3, and a reverse conductivity type semiconductor layer 4 are formed on a single crystal substrate 1 by MOC.
It is formed by sequentially laminating by a VD method or the like.

When these semiconductor layers 2, 3, and 4 are formed, the substrate temperature is first set to 300 to 500 ° C.
After forming an amorphous gallium arsenide film to a thickness of about 2000 °, the substrate temperature is raised to 600 to 800 ° C. to form semiconductor layers 2, 3, and 4 having a desired thickness.

In this case, TMG ((C
H_Three )_Three Ga), arsine (AsH) _Three ), TMA ((C
H_Three )_Three Al), TMI ((CH_Three )_Three In) etc.
The gas for controlling the conductivity type is silane
(SiH_Four ), Hydrogen selenide (H_Two Se), DMZ
((CH_Three )_Three Zn) or the like is used, and a carrier gas and
H_TwoAre used.

Next, the semiconductor layers 2, 3, and 4 are patterned in an island shape so that adjacent elements are electrically separated from each other. This etching is performed by wet etching using a sulfuric acid-hydrogen peroxide-based etchant, dry etching using CCl ₂ F ₂ gas, or the like.

Next, etching is performed to expose a part of the one conductivity type semiconductor layer 3 on one end side. This etching is also performed by wet etching using a sulfuric acid / hydrogen peroxide based etchant, dry etching using CCl ₂ F ₂ gas, or the like.

Next, a silane gas is formed by a plasma CVD method.
(SiH_Four ) And ammonia gas (NH _Three ) Using nitridation
An insulating film made of silicon is formed and patterned.
Next, chromium and gold are formed by evaporation or sputtering.
Patterning, and plasma CVD again
And the silane gas (SiH_Four ) And ammonia gas (N
H_Three) To form an insulating film made of silicon nitride
It is completed by patterning.

Thus, according to the LED array of the present invention,
For example, the buffer layer 2 is formed by two-step growth, and the ohmic contact layer 3 of the one conductivity type semiconductor layer 3 is formed.
is formed, the film formation is temporarily interrupted during the formation of the ohmic contact layer 3a, and a thermal cycle in which the temperature is raised and the high temperature is repeated to lower the dislocation density, whereby at least one of the ohmic contact layers 3a is formed. The thermal cycling treatment is performed on the layer region of the portion to form such a layer structure, so that even if the thickness of the buffer layer 2 is reduced to the same extent as the conventional one, the thermal cycling process is performed on the ohmic contact layer 3a thereon. By performing the treatment, a semiconductor layer having a low dislocation density was obtained, and as a result, the overall film thickness could be reduced.

For example, a conventional L as shown in FIGS.
In the ED array, the buffer layer 2 is used to reduce dislocations.
The thickness of the ohmic contact layer 23a is 1 μm, while the thickness of the ohmic contact layer 23a is 2 μm.
On the other hand, according to the LED array of the present invention, it was confirmed that the buffer layer 2 was 1 μm and the ohmic contact layer 3a was 1 μm, so that a dislocation reduction effect equivalent to that of the related art could be obtained.

If the film thickness is the same as the conventional one, the same effect of reducing dislocations as when the buffer layer 22a is formed to a thickness of 3 μm is obtained, and the characteristics of the element are improved.

[0045]

As described above, according to the LED array of the present invention, an island-like semiconductor layer made of a different material is formed on the substrate by stacking the one conductivity type semiconductor layer and the opposite conductivity type semiconductor layer. In a configuration in which the individual electrodes and the common electrode are both arranged on the substrate surface while exposing a part of the semiconductor layer of one conductivity type, a thermal cycle for reducing the dislocation density is performed in the ohmic contact layer, and the dislocation reduction is also performed. The formation of the single-layer strained layer or strained superlattice layer after the formation of the ohmic contact layer for the purpose of reducing the thickness of the buffer layer while maintaining the dislocation density or maintaining the thickness of the buffer layer The dislocation density can be reduced, and as a result, the overall film thickness can be reduced. As a result, the film formation time is shortened and the consumption of raw materials is reduced as compared with the conventional method. It is that strike is lowered.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an LED array of the present invention.

FIG. 2 is a plan view showing an LED array of the present invention.

FIG. 3 is a cross-sectional view showing a conventional LED array.

FIG. 4 is a plan view showing a conventional LED array.

FIG. 5 is a diagram showing a temperature profile of a conventional buffer layer.

FIG. 6 is a diagram showing the relationship between the thickness of a buffer layer and the dislocation density of a semiconductor layer in the related art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... board | substrate, 2 ... buffer layer, 3 ... one conductivity type semiconductor layer, 4 ... reverse conductivity type semiconductor layer, 5 ... individual electrode, 6 ... common electrode, 7 ... ... insulating film, 21 ... substrate, 22 ... buffer layer, 23 ... one conductivity type semiconductor layer, 24 ... reverse conductivity type semiconductor layer, 25 ... individual electrode, 26 ... common electrode , 27 ... insulating film,

Claims (1)

[Claims] 1. A plurality of island-shaped semiconductor layers each comprising a buffer layer, a one-conductivity-type semiconductor layer, and a reverse-conductivity-type semiconductor layer sequentially laminated with a material different from a constituent material of the substrate. An LED array provided with an individual electrode and a common electrode by exposing a part of each semiconductor layer of one conductivity type, wherein the semiconductor layer of one conductivity type is an ohmic contact layer, a single-layer strained layer or a strained superlattice. An LED array comprising a layer and a cladding layer sequentially laminated, and wherein at least a part of a layer region of the ohmic contact layer is subjected to a thermal cycling process.