JP2002043312A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device which can reduce infiltration of a wet liquid into the interface between a photoresist film and an insulating film. SOLUTION: The manufacturing method of a semiconductor device is provided with a process for forming a plasma TEOS film 3 on an Al alloy wiring layer 1 by a plasma CVD method, a process for applying a photoresist film on the film 3, a process for forming a resist pattern 5 on the film 3 by exposing and developing this photoresist film and a process for wet-etching the film 3 using this resist pattern 5 as a mask. The process for forming the film 3 is conducted so that the time to take from the period that oxygen gas is introduced in a chamber till the period that the introduction of TEOS gas into the chamber is stopped as a high-frequency power is applied to the oxygen gas to the stop of the high-frequency power being applied is longer than two seconds.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a wet etching step. In particular, the present invention relates to a method for manufacturing a semiconductor device capable of reducing penetration of a wetting liquid into an interface between a photoresist film and an insulating film.

[0002]

2. Description of the Related Art FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

A plasma TEOS (Tet) is formed on an Al alloy wiring 101 by using a plasma CVD (Chemical Vapor Deposition) apparatus using a high frequency and a low frequency (not shown).
(raEthyl OrthoSilicate) film 103 is formed.

That is, a wafer is placed in a chamber of a plasma CVD apparatus, the pressure in the chamber is reduced, and the wafer is controlled to a predetermined temperature.
Gas and oxygen gas are introduced. Next, plasma is generated by applying an RF power, and the Al alloy wiring 101 is generated.
A TEOS film is deposited thereon. Thereafter, the introduction of the TEOS gas and the oxygen gas is stopped, and the deposition of the TEOS film is terminated.

Thereafter, a photoresist film is applied on the plasma TEOS film 103, and the photoresist film is exposed and developed to form a resist pattern 105 having an opening 105a on the plasma TEOS film 103. .

Next, the plasma TEOS film 103 is wet-etched using the resist pattern 105 as a mask. Thereby, the opening 105 of the resist pattern is formed.
The plasma TEOS film 103 exposed by a is etched isotropically, and the plasma TEOS film 103 is formed with a first connection hole 103a extending under the resist pattern.

Thereafter, the plasma TEOS film 103 is dry-etched using the resist pattern 105 as a mask. As a result, a second connection hole 103b is formed in the plasma TEOS film 103, and the second connection hole 103b is connected to the first connection hole 103a. The first connection hole and the second connection hole are located on the Al alloy wiring 101.

Next, after the resist pattern 105 is peeled off, the plasma TEOS in the first connection hole and the second connection hole are removed.
An Al alloy film (not shown) is deposited on the film 103,
By patterning the 1 alloy film, an Al alloy wiring (not shown) is formed. This Al alloy wiring is first,
It is electrically connected to the lower Al alloy wiring 101 in the second connection hole.

[0009]

By the way, in the conventional method for manufacturing a semiconductor device, the plasma TEOS film 103 is not used.
When wet etching is performed, the wet liquid permeates the interface between the plasma TEOS film 103 and the resist pattern 105, and the first connection hole 103a expands in the direction of the arrow 107 from a desired shape.

Further, the degree of penetration of the wetting liquid into the interface between the TEOS film 103 and the resist pattern varies depending on the used CVD apparatus, photoresist coating apparatus, and etching apparatus. However, variations occur depending on the CVD apparatus, photoresist coating apparatus, and etching apparatus used.

The cause of such a wetting liquid infiltration may be caused by the resist pattern 105 and the TEOS film 1.
It is conceivable that the adhesiveness with No. 03 is poor. Therefore, in order to improve the adhesion between the resist pattern and the TEOS film, an adhesion enhancer such as HMDS (hexamethyle disilazane) is applied to the plasma TEOS film before applying the photoresist film on the plasma TEOS film 103. It is conceivable to perform another process such as However, even if such another treatment is performed, it is not enough to reduce the penetration of the wetting liquid into the interface between the TEOS film and the resist pattern.
In addition, performing such a process increases the number of steps, and thus increases the manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device which can reduce the penetration of a wetting liquid into the interface between a photoresist film and an insulating film. Is to do. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the penetration of a wetting liquid into an interface between a photoresist film and a plasma TEOS film.

[0013]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a base film by a plasma CVD method, and a step of forming a photo-resist on the insulating film. Applying a resist film, exposing and developing the photoresist film to form a resist pattern on the insulating film, and wet etching the insulating film using the resist pattern as a mask. In the step of forming the insulating film, after the introduction of the source gas is stopped while introducing the oxygen gas into the chamber and applying the high frequency power, the time until the applied high frequency power is stopped is set to 2 seconds. It is characterized by the above.

According to the method of manufacturing a semiconductor device described above, when the formation of the insulating film on the base film by the plasma CVD method is completed, the introduction of the source gas is stopped, and then only the oxygen gas is supplied for 2 seconds or more. It is introduced into the chamber, and high-frequency power is supplied during that time. Therefore, when a photoresist film is applied on the insulating film in a subsequent step, the adhesion between the photoresist film and the insulating film can be improved. As a result, when wet etching is performed on the insulating film, penetration of the wet etching solution into the interface between the insulating film and the resist pattern can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the source gas is a TEOS gas and the insulating film is a plasma TEOS film. Thereby, it is possible to reduce the penetration of the wetting liquid into the interface between the photoresist film and the plasma TEOS film.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1A, a plasma TEOS film 3 is formed on an Al alloy wiring 1 by using a plasma CVD apparatus (not shown) using two frequencies of a high frequency and a low frequency. I do.

That is, a wafer is placed in a chamber of a plasma CVD apparatus, the pressure in the chamber is reduced, and the wafer is controlled at a predetermined temperature of, for example, about 350 ° C. to 400 ° C., and then TEOS gas and oxygen gas are introduced into the chamber. Is introduced. Next, plasma is generated in the chamber by applying high-frequency power and low-frequency power from an RF power supply. In this way, the plasma T
An EOS film 3 is deposited. Thereafter, while the RF power (high-frequency power and low-frequency power) is turned on, the introduction of the TEOS gas is stopped, and thereafter, 2 seconds or more (preferably 2 seconds to
Second) Oxygen gas is introduced into the chamber, the RF power supply is stopped, and the deposition of the TEOS film is completed. During the introduction of the oxygen gas for 2 seconds or more, the plasma in the oxygen atmosphere alone is set on the plasma TEOS film 3.

Thereafter, a photoresist film is applied on the plasma TEOS film 3, and the photoresist film is exposed and developed, whereby a resist pattern 5 having an opening 5a is formed on the plasma TEOS film 3. .

Next, as shown in FIG. 1B, the plasma TEOS film 3 is wet-etched using the resist pattern 5 as a mask. Thereby, the plasma TEOS exposed by the opening 5a of the resist pattern is formed.
The film 3 is isotropically etched, and the plasma TEOS film 3
A first connection hole 3a is formed under the resist pattern.

Thereafter, the plasma TEOS film 3 is dry-etched using the resist pattern 5 as a mask. Thereby, the second connection hole 3b is formed in the plasma TEOS film 3, and the second connection hole 3b is connected to the first connection hole 3a. The first connection hole and the second connection hole are located on the Al alloy wiring 1.

Next, after removing the resist pattern 5,
Plasma TEOS film 3 in first connection hole and second connection hole
An Al alloy film (not shown) is deposited thereon, and the Al alloy film is patterned to form an Al alloy wiring (not shown). The Al alloy wiring is electrically connected to the lower Al alloy wiring 1 in the first and second connection holes.

According to the above embodiment, the Al alloy wiring 1
At the time of forming the plasma TEOS film 3 thereon, at the end of the film formation, after stopping the introduction of the TEOS gas as a source gas, only oxygen gas is introduced into the chamber for 2 seconds or more, and the RF power is also Is supplied. For this reason, when a photoresist film is applied on the plasma TEOS film 3 in a subsequent step, the adhesion between the photoresist film and the plasma TEOS film is improved as compared with a semiconductor device manufactured by a conventional manufacturing method. Can be. As a result, when wet etching is performed on the plasma TEOS film 3, it is possible to suppress the penetration of the wet etching solution into the interface between the plasma TEOS film 3 and the resist pattern 5. Thereby, the first connection hole 3a can be prevented from being unnecessarily widened, and the connection hole 3a having a desired shape can be obtained. Fine hole processing by wet etching becomes possible.

Further, in the present embodiment, as described above, the penetration of the wetting liquid into the interface between the plasma TEOS film 3 and the resist pattern 5 can be suppressed.
Variations in the extent of expansion of the first connection holes 3a due to the VD device, the photoresist coating device, and the etching device can be suppressed. Therefore, the shape of the first connection hole 3a can be made constant.

In this embodiment, since the adhesion between the photoresist film and the plasma TEOS film can be improved as described above, an adhesion enhancer such as HMDS may be used before the photoresist film is applied. Plasma TEOS film 3
It can complement the improvement of the adhesion by another treatment such as coating on the surface. In addition, since the step of performing such separate processing can be expected to be eliminated, it is also possible to expect a reduction in manufacturing cost.

Next, the experimental results will be described.

FIG. 2 shows the results of experiments on the shape of the first connection hole formed by using the above-described method for manufacturing a semiconductor device. After the introduction of the TEOS gas is stopped, only the oxygen gas is introduced into the chamber. FIG. 6 is a diagram showing the relationship between the time taken and the width of one side spread by wet etching.

That is, FIG. 2 shows that a plurality of semiconductor devices are manufactured by the manufacturing method according to the present embodiment (specifically, the following manufacturing method), and that the first connection holes of one of the semiconductor devices are expanded by wet etching. Width (Figure 1
(Width corresponding to reference numeral 7 shown in (b)). Note that this experiment was performed using two types of plasma CVD apparatuses. Reference numeral 11 denotes a first plasma CVD.
It is an experimental result using the apparatus, and reference numeral 12 is an experimental result using the second plasma CVD apparatus.

The semiconductor device has a dual frequency plasma CV.
In the D apparatus, TEOS gas and oxygen gas are introduced into the chamber, the wafer temperature is set to 350 ° C. to 400 ° C.,
After applying the high frequency power and the low frequency power to generate plasma, forming a plasma TEOS film, turning off the introduction of the TEOS gas, and setting the time until the RF power (high frequency power and low frequency power) is turned off to zero. 0.0 seconds, 0.5 seconds, 1.
It was manufactured by changing to 0 seconds, 1.5 seconds, and 2.0 seconds.

According to FIG. 2, the first and second plasmas C
In both of the VD devices, the introduction time of only oxygen gas is set to 2
It was found that when the time was longer than one second, the width of one side spread due to wet etching could be reduced.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In the above embodiment, the plasma TE
Although the OS film 3 is formed, the present invention is not limited to this Al alloy wiring. A plasma TEOS film can be formed on an insulating film, and a plasma TEOS film can be formed on a silicon substrate. It is also possible to form a film.

In the above-described embodiment, a dual-frequency plasma CVD apparatus is used, but another plasma CVD apparatus can be used.

[0034]

As described above, according to the present invention, when the formation of an insulating film on a base film by the plasma CVD method is completed, the introduction of the source gas is stopped, and then the oxygen is applied for 2 seconds or more. Only gas is introduced into the chamber, and high-frequency power is supplied during that time. Therefore, it is possible to provide a method of manufacturing a semiconductor device which can reduce the penetration of the wetting liquid into the interface between the photoresist film and the insulating film.

According to the present invention, the source gas is TEO.
By using S gas and using a plasma TEOS film as the insulating film, it is possible to provide a method of manufacturing a semiconductor device which can reduce penetration of a wet liquid into an interface between a photoresist film and a plasma TEOS film.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the time when only oxygen gas is introduced into a chamber after the introduction of TEOS gas is stopped and the width of one side spread by wet etching.

FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1,101 Al alloy wiring 3,103 Plasma TEOS film 3a, 103a First connection hole 3b, 103b Second connection hole 5,105 Resist pattern 5a, 105a Opening 7 One-side spreading width of first connection hole by wet etching 11th Experimental results using the first plasma CVD apparatus 12 Experimental results using the second plasma CVD apparatus 107 Arrow

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/768 H01L 21/90 PF term (Reference) 4K030 AA06 AA09 AA14 BA44 DA08 EA01 FA01 JA11 KA30 LA02 LA15 5F033 KK09 QQ19 QQ37 RR04 SS04 SS15 5F045 AA08 AB32 AC09 AC11 BB17 HA14 HA22 HA25 5F058 BA10 BC02 BD04 BF07 BF25 BF29 BH11 BH16 BJ02

Claims (2)

[Claims] A step of forming an insulating film on a base film by a plasma CVD method, a step of applying a photoresist film on the insulating film, and exposing and developing the photoresist film to form an insulating film. Forming a resist pattern thereon; and wet-etching the insulating film using the resist pattern as a mask. The step of forming the insulating film comprises introducing an oxygen gas into the chamber and applying high frequency power. A method for manufacturing a semiconductor device, wherein the time from stopping the introduction of a source gas while applying a voltage to stopping the applied high-frequency power is 2 seconds or more. 2. The method according to claim 1, wherein said source gas is TEOS gas, and said insulating film is a plasma TEOS film.