JP2002026297A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which can be improved in degree of integration and accuracy, can be reduced in power consumption, and is formed in a gate array type or ECA type. SOLUTION: This semiconductor device has diffusion regions 11 and 12 which are respectively provided in the well regions 9 and 10 of a semiconductor substrate on which transistors are formed and divided into a plurality of source regions or drain regions, metallic wiring 20 which selects the divided source or drain regions by the number corresponding to the sizes of transistors and connects the selected regions to the transistors and, in addition, the transistors to each other based on wiring information, and gate electrodes 14 constituting the transistors together with the source or drain regions and the device is constituted in the gate array type or ECA type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of transistors, and more particularly to a semiconductor device suitable for designing a desired electric circuit by automatic placement and routing.

[0002]

2. Description of the Related Art A method of designing a desired electric circuit using a semiconductor substrate on which a plurality of transistors are formed can be classified in various ways, and a gate array method is one of the methods classified by a design method. The gate array system employs a manufacturing method called a master slice system, and has a semiconductor substrate serving as a master. A large number of transistors of the same size are arranged neatly on the semiconductor substrate serving as the master,
A desired electric circuit is formed by wiring these transistors with metal wiring in a slicing process. Since the transistors are previously arranged on the semiconductor substrate serving as the master, the positions of the transistors can be determined by automatic arrangement and wiring, and a desired electric circuit can be formed only by performing circuit design. With the advantage that. In addition, since a semiconductor substrate serving as a master can be prepared, there is an additional advantage that the period of circuit design can be shortened.

Further, in order to realize a gate array system by incorporating a memory, an analog circuit, an A / D converter, etc., a memory portion, an analog circuit portion, an A / D converter portion, etc. are previously provided on a master semiconductor substrate. A method that can be realized by making it is called an embedded cell array method (ECA method). In the semiconductor device of the ECA method, not only a desired electric circuit can be formed by automatic arrangement and wiring, but also a functional block itself can be formed, so that there is an advantage that the design period can be further reduced.

FIG. 34 shows, for example, "'95 Mitsubishi Semiconductor CM
FIG. 21 is a front view showing a chip layout of a semiconductor substrate in a conventional gate array type semiconductor device described in “OS Gate Array 0.8 μm Data Book”.
In the figure, reference numeral 1 denotes a transistor forming region in which a plurality of field effect transistors are formed in a matrix, and 2 denotes bonding pads for connecting an electric circuit formed on the semiconductor substrate to external pins of the semiconductor device.
Are external input / output buffers disposed between the input / output transistors in the transistor formation region 1 and the bonding pads 2 for matching these interfaces.

FIG. 35 is a partially enlarged layout diagram showing an example of the transistor forming region 1. As shown in FIG. In this example, a plurality of P-channel field-effect transistors and a plurality of N-channel field-effect transistors are formed in the transistor forming region 1. In the figure, 4 is a P-type diffusion region formed in a long shape along one side of the transistor forming region 1, and 5 is an N-type formed in a long shape in parallel with the P-type diffusion region 4. It is a mold diffusion region.
Reference numerals 6 denote gate electrodes disposed at regular intervals on the P-type diffusion region 4 and the N-type diffusion region 5, respectively.

FIG. 36 is a circuit layout diagram showing an example of a circuit layout when an electric circuit in the transistor formation region 1 is automatically arranged and wired. In the figure, reference numeral 7 denotes a functional block such as a logic circuit or a flip-flop constituting the electric circuit. As shown in FIG. 36, in the automatic placement and routing, generally, a functional block 7 is laid out for each bank in which a pair of the P-type diffusion region 4 and the N-type diffusion region 5 are paired. Each of the functional blocks 7 is arranged at the same time. Thus, a gate array type semiconductor device is formed.

FIG. 37 shows, for example, "'95 Mitsubishi Semiconductor Embedded Cell Array / Cell-Based IC Data Book".
1 is a front view showing a chip layout of a semiconductor substrate in a conventional ECA-type semiconductor device described in FIG. In the figure, reference numeral 8 denotes functional blocks supplied to circuit designers as general-purpose functional blocks such as a memory and an A / D converter. Then, in the transistor formation region other than the function block 8, a function block is provided in the same manner as in the case of the gate array system.
Thereby, a predetermined electric circuit is realized.

However, in such a semiconductor device formed by the gate array system or the ECA system, the use of the transistors formed in the transistor formation region 1 is unknown, and therefore, all the transistors having the ability to operate as an output buffer are used. It is formed in the size of. Therefore, the transistor used as an internal circuit of the functional block 7 has an unnecessarily large size. As a result, the size of the same functional block 7 is increased due to the large transistor size, the length of the wiring in the functional block 7 is increased, and the wiring capacity is increased.

Further, since the function blocks 7 are allocated to the semiconductor substrate by the automatic placement and routing, not all the transistors in each bank are necessarily used, and the use efficiency of the transistors is reduced accordingly. For these reasons, high integration cannot be expected in a semiconductor device formed by a gate array system or an ECA system, and power consumption increases. Further, since there is only one type of transistor size, the balance between the P-channel field-effect transistor and the N-channel field-effect transistor is poor, and the threshold value may deviate from a potential obtained by equally dividing the VDD potential by two. Becomes large.

[0010] In addition to the above documents, there are other documents having descriptions related to the conventional semiconductor device. For example, Japanese Patent Application Laid-Open No. Hei 2-268644 discloses that a transistor is divided in a field. JP-A-1-289268 where the drain region is independent, JP-A-3-6007 where the gate isolation method is not used
No. 2 publication.

[0011]

Since the conventional gate array type or ECA type semiconductor device is constructed as described above, the design burden on the circuit designer is reduced, and the semiconductor substrate is not completely completed before the circuit design is completed. Has the advantage that the time from the completion of circuit design to the delivery of the semiconductor device can be shortened. However, in the semiconductor device formed thereby, high integration cannot be expected, and power consumption increases. Further, there is a problem that the accuracy is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to shorten the design period and to achieve higher integration than a conventional semiconductor device formed by a gate array system or an ECA system. It is an object of the present invention to obtain a semiconductor device capable of reducing power consumption and increasing accuracy.

[0013]

In a semiconductor device according to the present invention, a diffusion region in each well region where a transistor is formed is divided into a plurality of source regions or drain regions.
Each divided source region or drain region is selected by the number corresponding to the transistor size and connected by metal wiring.

In the semiconductor device according to the present invention, the diffusion region of each well region is divided into a plurality of source regions or drain regions at the same time while sharing the source region or the drain region. A common gate electrode is prepared for a region or a drain region.

In the semiconductor device according to the present invention, the diffusion region of each well region is divided into a plurality of source regions or drain regions while sharing the source region or the drain region. A gate electrode is prepared for each source region or drain region.

In the semiconductor device according to the present invention, while the source region or the drain region is shared, the diffusion region of each well region is divided into a plurality of source regions or drain regions. Alternatively, a common gate electrode is prepared in the drain region.

In the semiconductor device according to the present invention, while the source region or the drain region is shared, the plurality of diffusion regions of each well region are simultaneously divided into a plurality of source regions or drain regions. A gate electrode is prepared for each region or drain region.

In the semiconductor device according to the present invention, an independent source region or drain region of a plurality of diffusion regions in each well region is divided into a plurality of source regions or drain regions, and the plurality of source regions or drain regions are divided. Are provided with a common gate electrode.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows E according to the first embodiment of the present invention.
FIG. 2 is a front view showing a layout of an electric circuit on a semiconductor substrate in a semiconductor device formed by the CA method. FIG. 2 is a cross-sectional view taken along the line aa shown in FIG. 1 shows an example of a layout of an electric circuit on a semiconductor substrate serving as a master when one diffusion region exists.

In FIG. 1, reference numeral 9 denotes an N well region on the semiconductor substrate, and reference numeral 10 denotes a P well region. 1
1 is an N well region 9 for forming a transistor.
Is a single P-type diffusion region, and 12 is a P-well region 10 for forming a transistor.
Is an N-type diffusion region which is disposed only once. Reference numeral 13 denotes a field oxide film formed in the P-type diffusion region 11 and the N-type diffusion region 12, respectively, for dividing the P-type diffusion region 11 or the N-type diffusion region 12 into a plurality of source regions or drain regions. . Reference numeral 14 denotes a P-type diffusion region 11 divided by these field oxide films 13.
Alternatively, the gate electrode is a gate electrode common to the plurality of divided source or drain regions connected so as to straddle the N-type diffusion region 12. Note that these gate electrodes 1
4, and the source region, the drain region, etc.
A transistor is formed on well region 9 and P well region 10.

FIGS. 3 to 5 are front views showing an example of a layout when a desired electric circuit is configured using FIG. 1 as a master. In the figure, reference numeral 15 denotes a source region shared by each transistor in the P-type diffusion region 11, and 16 denotes a drain region of each transistor in the P-type diffusion region 11 divided by the field oxide film 13. Reference numeral 17 denotes a drain region of one of the transistors in the N-type diffusion region 12 divided by the field oxide film 13, reference numeral 18 denotes a source / drain shared region shared by each transistor in the N-type diffusion region 12, and reference numeral 19 denotes a field. N divided by oxide film 13
This is the source region of the other transistor in the type diffusion region 12. Reference numeral 20 denotes a metal wiring such as an aluminum wiring for electrical connection in the electric circuit, reference numeral 21 denotes a well contact for connecting the metal wiring 20 to the VCC potential or VSS potential, and reference numeral 22 denotes the metal wiring 20. This is a wiring connection hole of the electric circuit.

Next, a specific example of the layout will be described. Here, in the electric circuits shown in FIGS. 3 to 5, transistors are arranged by a gate isolation method using the layout on the semiconductor substrate shown in FIG. 1 as a master, and a metal wiring 20 and a wiring connection hole are formed in a slicing process. 2
2, by connecting the gate electrode 14, the source regions 15, 19, and the drain regions 16, 17 to each other.

In the layout shown in FIG. 3, since a gate isolation method is adopted for the transistor arrangement, a desired electric circuit can be separated from an adjacent transistor. The VDD potential is supplied from the well contact 21 via the metal wiring 20 and the wiring connection hole 22 to the source region 15 shared by the transistors to which the signals “A” and “B” of the P-type diffusion region 11 are distributed. And one drain region 16 of each of these transistors.
Is connected to one drain region 17 of the transistor of the N-type diffusion region 12 to which the signal “B” is distributed by the metal wiring 20 and the wiring connection hole 22. In the N-type diffusion region 12, the source region of the transistor to which the signal “B” is distributed is shared with the drain region of the transistor to which the signal “A” is distributed to form the common source / drain region 18. . This N-type diffusion region 12
A desired electric circuit is formed by connecting one source region 19 of the transistor to which the signal “A” is distributed to the VSS potential through the metal wiring 20 and the wiring connection hole 22 by the well contact 21. ing.

FIGS. 4 and 5 have the same structure as the electric circuit shown in FIG. 3, but FIG.
Each of the two drain regions 16 of each transistor to which the “A” and “B” signals of “1” are distributed receives the signal “B” of the N-type diffusion region 12 through the metal wiring 20 and the wiring connection hole 22. "A" of the N-type diffusion region 12
Is connected to the VSS potential via the metal wiring 20, the wiring connection hole 22, and the well contact 21 to form a desired electric circuit. In FIG. 5, three drain regions 16 of each transistor to which the signals “A” and “B” of the P-type diffusion region 11 are distributed are connected to the metal wiring 20.
"B" of the N-type diffusion region 12
Is connected to the three drain regions 17 of the transistor to which the signal "A" is distributed, and the three source regions 19 of the transistor to which the signal "A" of the N-type diffusion region 12 is distributed.
Is connected to the VSS potential through the metal wiring 20, the wiring connection hole 22, and the well contact 21, thereby forming a desired electric circuit.

As described above, even if the same master substrate as shown in FIG. 1 is used, the selection of the connection by the metal wiring 20 causes the source regions 15 and 19 and the drain regions 16 and
17 can be changed, and the size of the transistor can be changed. In the example shown,
FIG. 3 shows one drain region 16 and 17 and one source region 19.
4 is a × 2 size transistor with two drain regions 16, 17 and source region 19, and FIG. 5 is a × 3 size transistor with three drain regions 16, 17 and source region 19. . As described above, as long as the number of field oxide films 13 dividing P-type diffusion region 11 and N-type diffusion region 12 can be increased, a multiple-fold transistor size can be realized. As described above, by giving variations to the sizes of the transistors to be combined, it is possible to optimize the balance between the P-type field effect transistor and the N-type field effect transistor, and the threshold value is a potential obtained by dividing the VDD potential by two. Can be approached.

As described above, according to the first embodiment, it is possible to efficiently arrange transistors by changing the areas of the source region 19 and the drain regions 16 and 17, thereby increasing the density and Low power consumption can be expected, and the threshold value is set to VD by optimally combining the P-type field effect transistor and the N-type field effect transistor.
Since it is possible to approach the potential of Ｄ of the D potential, an effect is obtained such that an error is reduced and high accuracy can be expected.

Embodiment 2 FIG. FIG. 6 is a front view showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a second embodiment of the present invention. FIG. 6 has substantially the same structure as FIG. 1 in the first embodiment, and the same reference numerals are given to the corresponding portions as in the first embodiment, and the description thereof will be omitted. As shown, the semiconductor device according to the second embodiment is different from the semiconductor device of the second embodiment in that a gate electrode 14 is separated at a field oxide film 13 which divides a P-type diffusion region 11 and an N-type diffusion region 12 into two. This is different from that of the first embodiment.

Next, a specific example of the layout will be described. 7 and 8 are front views showing an example of a layout when a desired electric circuit is configured using FIG. 6 as a master.
The same reference numerals as in FIGS. 3 to 5 denote the same parts, and a description thereof will be omitted. In the electric circuit shown in FIGS. 7 and 8, transistors are arranged by a gate isolation method using the layout on the semiconductor substrate shown in FIG. 6 as a master, and gates are formed by metal wiring and wiring connection holes in a slicing process. Although it is formed by connecting the electrode, the source region, and the drain region, the connecting portion is different from that of the first embodiment.

In the layout shown in FIG. 7, the VDD potential is supplied to the source region 15 of the P-type diffusion region 11 which is shared by the transistors to which the signals “A” and “B” are distributed, and each of the transistors is connected to one source. Each drain region 16 is connected to the drain region 17 of the N-type diffusion region 12 which has only one transistor to which the signal “B” is distributed. Also, the N-type diffusion region 1
In FIG. 2, the source region of the transistor to which the signal “B” is distributed is shared with the drain region of the transistor to which the signal “A” is distributed to form the common source / drain region 18. By connecting the source region 19 of the N-type diffusion region 12 having only one transistor to which the signal “A” is distributed to the VSS potential,
A desired electric circuit is configured.

In the layout shown in FIG. 8, the drain region 16 of each of the two transistors to which the signals "A" and "B" of the P-type diffusion region 11 are distributed has an N-type diffusion region. The two transistors to which the signal “B” is distributed in the region 12 are connected to the drain region 17 each having one transistor.
The source region 19 where each of the two transistors to which the signal “A” is distributed has one VSS.
By connecting to a potential, a desired electric circuit is formed.

As described above, even if the same master substrate as shown in FIG. 6 is used, the area of the source region 19 and the drain regions 16 and 17 can be changed by selecting the connection of the metal wiring 20. The point that the size can be changed is the same as in the first embodiment. In the illustrated example, FIG. 7 shows a × 1 size, and FIG. 8 shows a × 1 size.
The transistor is a two-size transistor, and by switching the combination of the connection between the gate electrode 14 and the source and drain regions, it is possible to realize a transistor size that is many times larger.

As described above, according to the second embodiment, similarly to the first embodiment, the transistors can be efficiently arranged by changing the areas of the source region 19 and the drain regions 16 and 17. Therefore, high density and low power consumption can be expected.
By optimally combining type field effect transistors,
It is possible to bring the threshold value closer to a half of the VDD potential, so that an effect is obtained such that an error is reduced and higher accuracy can be expected.

Embodiment 3 FIG. 9 is a front view showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by the ECA method according to Embodiment 3 of the present invention.
FIG. 9 shows an example of a layout of an electric circuit on a semiconductor substrate serving as a master when a plurality of diffusion regions exist in each well region. The same reference numerals are given and the description is omitted. In the semiconductor device according to the third embodiment, a plurality of P-type diffusion regions 11 are present in N-well region 9 and
This is different from that of the first embodiment in that a plurality of N-type diffusion regions 12 also exist therein. In FIG. 9, one P-type diffusion region 11 or one N-type diffusion region 12 is typically shown in each of the N-well region 9 and the P-well region 10, and the other is not shown.

In the third embodiment, the P-type diffusion region 11 and the N-type diffusion region 12 are deformed into a “king” shape as shown in FIG. The connection is made so as to straddle these P-type diffusion regions 11 or N-type diffusion regions 12. In this way, "king"
The P-type diffusion regions 11 and N
The type diffusion region 12 is divided by the gate electrode 14 into a plurality (three in this case) of source and drain regions. That is, the number of divisions can be changed depending on the deformation of the shapes of the P-type diffusion region 11 and the N-type diffusion region 12. Further, in FIG. 9, by separating each P-type diffusion region 11 of N-well region 9 and each N-type diffusion region 12 of P-well region 10 by field oxide film 13, a desired electric circuit Is disconnected.

Next, a specific example of the layout will be described. FIGS. 10 to 12 are front views showing an example of a layout when a desired electric circuit is configured using the layout on the semiconductor substrate shown in FIG. 9 as a master. This shows a configuration example of a desired electric circuit formed by connecting a gate electrode, a source region, and a drain region by a metal wiring and a wiring connection hole in a slicing step.

In the layout shown in FIG. 10, the VDD potential is supplied to the source region 15 of the P-type diffusion region 11 which is shared by the transistors to which the signals "A" and "B" are distributed, and each of the transistors has Is connected to one of the drain regions 16 of the transistor of the N-type diffusion region 12 to which the signal “B” is distributed. The N-type diffusion region 12
The source / drain region of the transistor to which the signal “B” is distributed and the drain region of the transistor to which the signal “A” is distributed are shared to form the source / drain shared region 18. A desired electric circuit is formed by connecting one of the source regions 19 of the transistor to which the signal “A” of the N-type diffusion region 12 is distributed to the VSS potential.

FIGS. 11 and 12 both have the same configuration as the electric circuit shown in FIG. 10, but in FIG. 11, each of the signals "A" and "B" of the P-type diffusion region 11 to which the signals are distributed is shown. Each two drain regions 16 of the transistor are connected to two drain regions 17 of the transistor to which the signal “B” of the N-type diffusion region 12 is distributed, and the transistor to which the signal “A” of the N-type diffusion region 12 is distributed. By connecting the two source regions 19 to the VSS potential, a desired electric circuit is formed. In FIG. 12, three drain regions 16 of each transistor to which the signals “A” and “B” of the P-type diffusion region 11 are distributed correspond to three transistors of the transistor to which the signal “B” of the N-type diffusion region 12 is distributed. The three source regions 1 of the transistor connected to the three drain regions 17 and to which the signal “A” of the N-type diffusion region 12 is distributed
9 is connected to the VSS potential to form a desired electric circuit.

As described above, even if the same master substrate as shown in FIG. 9 is used, the area of the source region 19 and the drain regions 16 and 17 can be changed by selecting the connection of the metal wiring 20. Size can be changed. Speaking of the illustrated example, FIG. 10 shows a × 1 size transistor, FIG. 11 shows a × 2 size transistor, and FIG. 12 shows a × 3 size transistor. As described above, a multiple-fold transistor size can be realized depending on the deformation of the shapes of the P-type diffusion region 11 and the N-type diffusion region 12. By giving variations to the sizes of the transistors to be combined in this manner, it becomes possible to optimize the balance between the P-type field effect transistor and the N-type field effect transistor, and the threshold value becomes VDD.
The potential can be approximated to a half of the potential.

As described above, according to the third embodiment, similar to the first and second embodiments,
By changing the area of the source region 19 and the drain regions 16 and 17, it is possible to arrange transistors efficiently, high density and low power consumption can be expected, and a P-type field effect transistor and an N-type By optimally combining the field effect transistors, the threshold value can be approximated to a half of the VDD potential, so that an effect is obtained such that an error is reduced and high accuracy can be expected.

Embodiment 4 FIG. 13 to 16 are front views showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a fourth embodiment of the present invention. FIG. This is an example of a layout of an electric circuit on a semiconductor substrate serving as a master when a diffusion region exists, and a P-type diffusion region 11 and an N-type diffusion region 12 are formed by a gate electrode 14 itself.
Each is divided into three source regions or drain regions. In FIG. 13, each P-type diffusion region 11 of N well region 9 and P
By separating the N-type diffusion regions 12 of the well region 10 from each other, a desired electric circuit can be separated from an adjacent transistor. 14 to 16 correspond to FIG.
3 shows an example of a layout in which a desired electric circuit is formed by connecting a gate electrode 14 and a source region and a drain region by a metal wiring 20 in a slicing step, using 3 as a master.

The semiconductor device according to the fourth embodiment is different from the third embodiment shown in FIGS. 9 to 12 in the shape of the P-type diffusion region 11, the N-type diffusion region 12, and the gate electrode 14. It is just different. That is, a plurality of P-type diffusion regions 11 are present in the N-well region 9, and a plurality of N-type diffusion regions 12 are present in the P-well region 10. As shown in FIG. 13, the diffusion region 12 is divided into three portions on both sides of a portion serving as a shared source region 15 or a shared source / drain region 18 to form a source region 19 or a drain region 16, 17. It has a shape in which a character-shaped portion is added. The gate electrode 14 has a shape that can divide the “T” -shaped portion of the P-type diffusion region 11 and the N-type diffusion region 12 into three.

As described above, the semiconductor device of the fourth embodiment shown in FIGS. 14 to 16 is different from the first to third embodiments in the connection points, but is the same as that shown in FIG. The metal wiring 2 can be
0, the source region 19 and the drain region 1 are selected.
This is the same as in the above embodiments in that the areas 6 and 17 can be changed and the size of the transistor can be changed. In the example shown in FIG.
4 is a × 1 size transistor, FIG. 15 is a × 2 size transistor, and FIG. 16 is a × 3 size transistor. Thus, the gate electrode 14 depends on the deformation of the P-type diffusion region 11 and the N-type diffusion region 12.
, It is possible to realize a multiple-fold transistor size. The effect obtained by such a configuration is the same as that of the first to third embodiments.

Embodiment 5 FIG. In the fifth embodiment, the P-type diffusion region 11, the N-type diffusion region 12, and the gate electrode 1
The only difference is the shape of 4. 17 to 19 are front views showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a fifth embodiment of the present invention. As shown in FIG. 17, the shapes of the P-type diffusion region 11 and the N-type diffusion region 12 are divided into two on both sides of a portion to be a shared source region 15 or a shared source / drain region 18. Alternatively, the shape is such that an “L” -shaped portion serving as the drain regions 16 and 17 is added. The gate electrode 14 has such a shape that the “L” -shaped portion of the P-type diffusion region 11 and the N-type diffusion region 12 can be divided into two.

FIG. 17 shows another example of the layout of a master electric circuit in the case where a plurality of diffusion regions exist in each well region. FIGS.
Is an example in which a gate electrode, a source region, and a drain region are connected by metal wiring in a slicing process, and a desired electric circuit is formed. Also in FIGS. 18 and 19, the area of the source region or the drain region can be changed by selecting the connection of the metal wiring, and the size of the transistor can be changed. Thus, the same effects as those of the above embodiments can be obtained. Can be

Embodiment 6 FIG. FIG. 20 is a front view showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a sixth embodiment of the present invention.
20 has substantially the same structure as that of FIG. 9 in the third embodiment, and the same reference numerals are given to the corresponding parts as in the third embodiment, and the description is omitted. As shown, the semiconductor device according to the sixth embodiment has a P-type diffusion region 11.
And the gate electrode 14 which divides the N-type diffusion region 12 into two parts is separated at the field oxide film 13 divided by the gate electrode 14 itself. I have.

Next, a specific example of the layout will be described. FIGS. 21 and 22 are front views showing an example of a layout when a desired electric circuit is configured using FIG. 20 as a master. The same reference numerals as in FIGS. Is omitted. In the electric circuits shown in FIGS. 21 and 22, transistors are arranged by a gate isolation method using the layout on the semiconductor substrate shown in FIG. 20 as a master, and gates are formed by metal wiring and wiring connection holes in a slicing process. Although it is formed by connecting the electrode, the source region, and the drain region, the connecting portion is different from that of the third embodiment.

In the layout shown in FIG. 21, the VDD potential is supplied to the source region 15 of the P-type diffusion region 11 which is shared by the transistors to which the signals "A" and "B" are distributed, and one of each transistor is provided. Is connected to the drain region 17 of the N-type diffusion region 12 which has only one transistor to which the signal “B” is distributed. In the N-type diffusion region 12, the source region of the transistor to which the signal "B" is distributed and the drain region of the transistor to which the signal "A" is distributed are shared.
The drain common region 18 is formed. A desired electric circuit is configured by connecting the source region 19 of the N-type diffusion region 12 having only one transistor to which the signal “A” is distributed to the VSS potential.

In the layout shown in FIG. 22, the drain region 16 of each of the two transistors to which the signals "A" and "B" of the P-type diffusion region 11 are distributed is provided.
To the drain region 17 where each of the two transistors to which the signal “B” of the N-type diffusion region 12 is distributed has one transistor.
, And the VSS potential is connected to the source region 19 of each of the two transistors to which the signal “A” of the N-type diffusion region 12 is distributed, thereby forming a desired electric circuit.

As described above, even if the same master substrate as shown in FIG. 20 is used, depending on the selection of the connection of the metal wiring 20, the source regions 15, 19 and the drain regions 16, 1 are selected.
7 is the same as in the first to third embodiments in that the area of the transistor 7 can be changed and the size of the transistor can be changed. Speaking of the illustrated example, FIG. 21 shows a transistor of × 1 size, and FIG. 22 shows a transistor of × 2 size. By switching the connection combination of the gate electrode 14 and the source region and the drain region, the transistor size can be increased by many times. It can be realized.

As described above, according to the sixth embodiment, similarly to the first to third embodiments, the areas of the source region 19 and the drain regions 16 and 17 are changed, thereby improving the efficiency. Since a transistor can be arranged, high density and low power consumption can be expected. In addition, by optimally combining a P-type field effect transistor and an N-type field effect transistor, the threshold value is reduced to the VDD potential. It is possible to bring the potential closer to 電位, to reduce the error, and to obtain effects such as expecting higher accuracy.

Embodiment 7 FIG. FIG. 23 is a front view showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a seventh embodiment of the present invention.
FIG. 23 has a structure substantially similar to that of FIG. 17 in the fifth embodiment, and the same reference numerals are given to the corresponding portions as in the fifth embodiment, and the description thereof will be omitted. As shown,
The semiconductor device according to the seventh embodiment includes an N well region 9
Alternatively, the P-well region 10 includes a plurality of P-type diffusion regions 11 or N-type diffusion regions 12, and each of the P-type diffusion regions 11 or N-type diffusion regions 12 has an independent source or drain region. It differs from that of the fifth embodiment in that it is divided into a plurality of source regions or drain regions. Therefore, each of the N-type diffusion region 11 and the P-type diffusion region 12 is formed of an independent source region or drain region having an L-shaped shape, and the source region and the drain region shared by them. There is no area. The shape of gate electrode 14 is the same as that of the fifth embodiment shown in FIG.

Next, a specific example of the layout will be described. FIGS. 24 and 25 are front views showing an example of a layout when a desired electric circuit is configured using the layout on the semiconductor substrate shown in FIG. 23 as a master, in which transistors are arranged by a gate isolation method. 3 shows a configuration example of a desired electric circuit formed by connecting a gate electrode, a source region, and a drain region by a metal wiring and a wiring connection hole in a slicing step.

In the layout shown in FIG. 24, VDD potential is supplied to the source region 15 of each transistor to which the signals “A” and “B” of the P-type diffusion region 11 are distributed, and the drain region 16 of each transistor is provided. One is connected to one of the drain regions 17 of the transistor to which the signal “B” of the N-type diffusion region 12 is distributed. In the N-type diffusion region 12, the source region 23 of the transistor to which the signal “B” is distributed and the drain region 24 of the transistor to which the signal “A” is distributed are connected to form a common source / drain region. I have. A desired electric circuit is formed by connecting one of the source regions 19 of the transistor to which the signal “A” is distributed to the VSS potential.

In the layout shown in FIG. 25, two drain regions 16 of each transistor to which signals "A" and "B" of P-type diffusion region 11 are distributed are connected to signal "B" of N-type diffusion region 12 respectively. Is connected to the two drain regions 17 of the transistor to which the signal "A" is distributed, and the two source regions 19 of the transistor to which the signal "A" of the N-type diffusion region 12 is distributed are connected to the VSS potential. Is composed.

As described above, even when the same master substrate as shown in FIG. 23 is used, the area of the source region 19 and the drain regions 16 and 17 can be changed by selecting the connection of the metal wiring 20. The size of the transistor can be changed. Speaking of the illustrated example, FIG. 24 shows a x1 size transistor, and FIG. 25 shows a x2 size transistor. Thus, the P-type diffusion region 11
Depending on the shape of the N-type diffusion region 12 and the deformation of the N-type diffusion region 12, a multiple-fold transistor size can be realized. In addition, by providing variations in the transistor sizes to be combined, it is possible to optimize the balance between the P-type field effect transistor and the N-type field effect transistor, and to make the threshold value approach a potential obtained by dividing the VDD potential by two. Can be.

As described above, according to the seventh embodiment, as in the first to fourth embodiments, the source region 1
9 and the areas of the drain regions 16 and 17, it is possible to efficiently arrange transistors, and it is possible to expect higher density and lower power consumption. By optimally combining the effect transistors, it becomes possible to bring the threshold value closer to a half of the VDD potential, and it is possible to obtain such effects that errors can be reduced and high accuracy can be expected.

Embodiment 8 FIG. 26 to 29 are front views showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by the ECA method according to an eighth embodiment of the present invention. FIG. This is an example of a layout of an electric circuit on a semiconductor substrate serving as a master when a diffusion region exists, and a P-type diffusion region 11 and an N-type diffusion region 12 are respectively connected to three source regions or drain regions by a gate electrode 14. Divided.
27 to 29 use FIG. 26 as a master, and form a gate electrode, a source region,
An example of an electric circuit in which drain regions are connected to form a desired electric circuit is shown.

The eighth embodiment is different from the above-described FIGS.
Embodiment 7 shown in FIG. 25 is different from P-type diffusion region 1 in FIG.
The only difference is that the shapes of the first and N-type diffusion regions 12 and the gate electrode 14 are different. That is, a plurality of P-type diffusion regions 11 exist in N-well region 9 and
26, a plurality of N-type diffusion regions 12 are present. The P-type diffusion region 11 and the N-type diffusion region 12 are each independently formed by a gate electrode 14 as shown in FIG. It is divided into two, and has a “T” shape without a shared region, which becomes the source region 19 or the drain regions 16 and 17. Also, the gate electrode 1
4 has the same shape as that of the fourth embodiment shown in FIG.
The character-shaped part can be divided into three parts.

As described above, in the semiconductor device of the eighth embodiment shown in FIGS. 27 to 29, even if the same master substrate shown in FIG. Alternatively, the area of the drain region can be changed, so that the size of the transistor can be changed. Speaking of the illustrated example, FIG.
It is possible to realize a transistor having a size of × 2 in FIG. 28 and a transistor having a size of × 3 in FIG. The effect obtained by such a configuration is the same as that of the first to seventh embodiments.

Embodiment 9 In the ninth embodiment, a P-type diffusion region 11, an N-type diffusion region 12, and a gate electrode 1
The only difference is the shape of 4. 30 to 33 are front views showing a layout of an electric circuit on a semiconductor substrate of a semiconductor device formed by an ECA method according to a ninth embodiment of the present invention. As shown in FIG. 30, the shapes of the P-type diffusion region 11 and the N-type diffusion region 12 are each divided into four parts to form the source region 19 or the drain region 1.
6 and 17 which are independent of each other without having a shared area. Also, the gate electrode 14
Each of the P-type diffusion regions 11 and the N-type diffusion region 12 has a shape having a “mouth” -shaped portion that divides the “cross-shaped” portion into four.

FIG. 30 shows another example of the layout of a master electric circuit in the case where a plurality of diffusion regions exist in each well region. FIGS.
Is an example in which a gate electrode, a source region, and a drain region are connected by metal wiring in a slicing process, and a desired electric circuit is formed. Also in FIGS. 31 to 33, P-type diffusion region 11 and N-type diffusion region 12 can be divided into four source regions or drain regions by gate electrode 14, respectively. The area can be changed, the size of the transistor can be changed, and the same effect as in the above embodiments can be obtained.

[0062]

As described above, according to the present invention, a diffusion region in each well region where a transistor is formed is divided into a plurality of source regions or drain regions, and each divided source region or drain region is divided. The number of transistors is selected according to the transistor size and connected by metal wiring, so the area of the source and drain regions can be changed as necessary by selecting the connection of the metal wiring. Because we can arrange efficiently,
Not only high density and low power consumption can be achieved, but also by optimally combining a P-type field effect transistor and an N-type field effect transistor,
Since it is possible to approach the potential of 1/2 of the D potential and the error is reduced, there is an effect that a semiconductor device which can be expected to have higher accuracy can be obtained.

[Brief description of the drawings]

FIG. 1 is a front view showing a layout of an ECA master in a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a cross section taken along line aa of the ECA-type master according to the first embodiment.

FIG. 3 is a front view showing a layout of an electric circuit configured in FIG. 1 as a master in the first embodiment.

FIG. 4 is a front view showing a layout of an electric circuit configured in FIG. 1 as a master in the first embodiment.

FIG. 5 is a front view showing a layout of an electric circuit configured in FIG. 1 as a master in the first embodiment.

FIG. 6 is a front view showing a layout of an ECA master in a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a front view showing a layout of an electric circuit configured in FIG. 6 as a master in the second embodiment.

FIG. 8 is a front view showing a layout of an electric circuit configured with FIG. 6 as a master in the second embodiment.

FIG. 9 is a front view showing a layout of an ECA master in a semiconductor device according to a third embodiment of the present invention;

FIG. 10 is a front view showing a layout of an electric circuit configured in FIG. 9 as a master in the third embodiment.

FIG. 11 is a front view showing a layout of an electric circuit configured in FIG. 9 as a master in the third embodiment.

FIG. 12 is a front view showing a layout of an electric circuit in which FIG. 9 is used as a master in the third embodiment.

FIG. 13 is a front view showing a layout of an ECA master in a semiconductor device according to a fourth embodiment of the present invention;

FIG. 14 is a front view showing a layout of an electric circuit configured in FIG. 13 as a master in the fourth embodiment.

FIG. 15 is a front view showing a layout of an electric circuit configured in FIG. 13 as a master in the fourth embodiment.

FIG. 16 is a front view showing a layout of an electric circuit configured in FIG. 13 as a master in the fourth embodiment.

FIG. 17 is a front view showing a layout of an ECA master in a semiconductor device according to a fifth embodiment of the present invention;

FIG. 18 is a front view showing a layout of an electric circuit configured with FIG. 17 as a master in the fifth embodiment.

FIG. 19 is a front view showing a layout of an electric circuit in which FIG. 17 is used as a master in the fifth embodiment.

FIG. 20 is a front view showing a layout of an ECA master in a semiconductor device according to a sixth embodiment of the present invention;

FIG. 21 is a front view showing a layout of an electric circuit in which FIG. 20 is used as a master in the sixth embodiment.

FIG. 22 is a front view showing a layout of an electric circuit configured with FIG. 20 as a master in the sixth embodiment.

FIG. 23 is a front view showing a layout of an ECA master in a semiconductor device according to a seventh embodiment of the present invention;

FIG. 24 is a front view showing a layout of an electric circuit configured with FIG. 23 as a master in the seventh embodiment.

FIG. 25 is a front view showing a layout of an electric circuit configured with FIG. 23 as a master in the seventh embodiment.

FIG. 26 is a front view showing a layout of an ECA master in a semiconductor device according to an eighth embodiment of the present invention.

FIG. 27 is a front view showing a layout of an electric circuit configured with FIG. 26 as a master in the eighth embodiment.

FIG. 28 is a front view showing a layout of an electric circuit configured with FIG. 26 as a master in the eighth embodiment.

FIG. 29 is a front view showing a layout of an electric circuit configured in FIG. 26 as a master in the eighth embodiment.

FIG. 30 is a front view showing a layout of an ECA-type master in a semiconductor device according to a ninth embodiment of the present invention.

FIG. 31 is a front view showing a layout of an electric circuit in which FIG. 30 is used as a master in the ninth embodiment.

FIG. 32 is a front view showing a layout of an electric circuit configured in FIG. 30 as a master in the ninth embodiment.

FIG. 33 is a front view showing a layout of an electric circuit configured with FIG. 30 as a master in the ninth embodiment.

FIG. 34 is a front view showing a chip layout in a conventional gate array type semiconductor device.

FIG. 35 is a partially enlarged front view showing a part of the chip layout of FIG. 34 in an enlarged manner.

FIG. 36 is a front view showing an example of automatic arrangement and wiring of an electric circuit in a transistor formation region of a conventional semiconductor device.

FIG. 37 is a front view showing a chip layout in a conventional ECA-based semiconductor device.

[Explanation of symbols]

9 N well region, 10 P well region, 11 P type diffusion region, 12 N type diffusion region, 13 field oxide film, 14 gate electrode, 15 source region, 16 drain region, 17 drain region, 18 source / drain shared region, 19 source region, 20 metal wiring, 21 well contact, 22 wiring connection hole, 23 source region, 24 drain region.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Junko Tajima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F064 AA03 DD02 DD05 DD09 EE02 EE05 EE27 EE33

Claims (6)

[Claims] 1. A semiconductor device in which a plurality of transistors are formed on a semiconductor substrate by a gate array method or an embedded cell array method, and the plurality of transistors are interconnected based on wiring information to form a desired electric circuit. A diffusion region provided in each well region of the semiconductor substrate on which the transistor is formed and divided into a plurality of source regions or drain regions; a gate electrode forming the transistor together with the source region or the drain region; A metal wiring for selecting the number of the divided source regions or drain regions corresponding to the size of the transistor, connecting them, and interconnecting the transistors based on the wiring information. apparatus. 2. The semiconductor device according to claim 1, wherein each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares a source region or a drain region, and is simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided in common for the plurality of divided source regions or drain regions. 3. The semiconductor device according to claim 1, wherein each well region of the semiconductor substrate has one diffusion region, and the diffusion region shares a source region or a drain region, and is simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided for each of said divided source regions or drain regions. 4. Each of the well regions of the semiconductor substrate has a plurality of diffusion regions, and each of the diffusion regions shares a source region or a drain region, and is simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided in common for the plurality of divided source regions or drain regions. 5. Each of the well regions of a semiconductor substrate has a plurality of diffusion regions, and each of the diffusion regions shares a source region or a drain region, and is simultaneously divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided for each of said divided source regions or drain regions. 6. The semiconductor device according to claim 1, wherein each well region of the semiconductor substrate has a plurality of diffusion regions, and each of the diffusion regions has an independent source region or drain region, which are divided into a plurality of source regions or drain regions. 2. The semiconductor device according to claim 1, wherein a gate electrode is provided in common for said plurality of divided source regions or drain regions.