JP2002023998A - Multiplier and multiplication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems that the addition results of an adder located at a lower stage and a carrier level (potential) are unstable and shift until the addition results of an adder on the preceding stage are determined and that power for driving an output transistor Tr is uselessly consumed or the like because the adder located at the lower stage can not determine its addition results until the addition results of the adder of the preceding stage are determined and the addition results of the adder on the preceding stage and carrier input timing are different. SOLUTION: An output timing control circuit C is provided in order to prevent the addition results and a carrier output until the addition results of a half adder HA and a full adder FA are determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication device and a multiplication method for outputting a result of multiplication of a multiplier bit and a multiplicand bit using a carry save method.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional multiplying device. In the drawing, HA is a half adder which inputs two partial products of a multiplier and a multiplicand, and outputs a result of addition of two partial products and a carry. , FA receives two inputs of the partial product of the multiplier and the multiplicand, or inputs the partial product of the multiplier and the multiplicand and the addition result of the previous-stage adder, or inputs two results of the addition of the previous-stage adder,
A full adder that adds the values of these two inputs and the carry of the previous-stage adder and outputs the addition result and the carry, x1
X5 is a multiplicand, y1 to y5 are multipliers, and p1 to p10 are multiplication results.

FIG. 6 is a block diagram showing the internal configuration of a full adder FA, and FIG. 7 is a block diagram showing the internal configuration of a half adder HA. In the figure, Tr is an output transistor, AI,
BI is an input terminal for inputting the partial product or the addition result of the previous-stage adder, CI is an input terminal for inputting the carry of the previous-stage adder, SO is an output terminal for outputting the addition result, and CO is the carry for the adder. Output terminal.

Next, the operation will be described. FIG. 5 shows an implementation of a 5-bit × 5-bit multiplication device using the carry save method. In the figure, the half adder H located at the uppermost stage
A inputs two partial products of the multiplier and the multiplicand, and outputs an addition result of two partial products and a carry. For example, the rightmost half adder HA has a partial product of x1y2 and x2y
The partial product of 1 is input, and p is the result of adding the two partial products.
2 (= x1y2 + x2y1) is output as a part of the multiplication result. If there is a carry associated with the addition of the two partial products, the carry of "1" is output to the lower full adder FA. If there is no carry, the carry of "0" is output to the lower full adder FA. Output to

When the full adder FA at the second stage from the top receives the addition result and the carry from the half adder HA at the uppermost stage, the full adder FA adds the addition result, the carry and the partial product (the full adder on the leftmost side). The FA does not receive the addition result from the top half adder HA, and thus adds the two partial products and the carry), and outputs the addition result and the carry. For example, the full adder FA located on the rightmost side is the second half adder H
The first carry from the top right of the addition result of A and x1
A partial product of y3 is input, and p3, which is the result of addition, is output as a part of the multiplication result. If there is a carry due to the addition, a carry of "1" is output to the lower full adder FA, and if there is no carry, a carry of "0" is output to the lower full adder FA. .

As for the full adders FA of the third and subsequent stages from the top, similarly to the full adders FA of the second stage from the top, the addition result and the carry are output to obtain the multiplication results of p1 to p10. .

[0007]

Since the conventional multiplication device is constructed as described above, the lower adder determines the addition result until the addition result of the preceding adder is determined. Cannot be performed, and the addition result of the preceding adder and the output timing of the carry are also different. Therefore, until the addition result of the preceding-stage adder is determined, the addition result of the lower-stage adder and the level (potential) of the carry transition without being stabilized, so that power for driving the output transistor Tr is wasted. There was a problem such as consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a multiplication device and a multiplication method capable of preventing wasteful power consumption.

[0009]

SUMMARY OF THE INVENTION A multiplication apparatus according to the present invention operates until a result of addition of a half adder and a full adder is determined.
An output control circuit for preventing the output of the addition result and the carry is provided.

The multiplication method according to the present invention blocks the addition result and the carry output until the addition result of the adder is determined, so that the addition result and the carry level of the adder located below the adder are determined. Is to be stabilized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a multiplication apparatus according to Embodiment 1 of the present invention. In the figure, HA is a half-adder which inputs two partial products of a multiplier and a multiplicand, and outputs an addition result of two partial products and a carry. The FA and the FA receive two inputs of the partial product of the multiplier and the multiplicand, or input the addition result of the partial product of the multiplier and the multiplicand and the previous-stage adder, or input two results of the addition of the previous-stage adder. Is added to the carry of the previous adder, and the addition result and the carry are output. The full adder C is attached to each adder, and the addition result of the half adder FA and the full adder HA is determined. Output timing control circuit (output control circuit) for preventing the addition result and carry output until
5 is a multiplicand, y1 to y5 are multipliers, p1 to p10 are multiplication results, and TC1 to TC5 are timing control signals.

FIG. 2 is a block diagram showing the internal configuration of the full adder FA and the output timing control circuit C.
Is a half adder HA and an output timing control circuit C
FIG. 2 is a configuration diagram showing an internal configuration of the device. In the figure, Tr is an output transistor, AI and BI are input terminals for inputting a partial product or the addition result of the previous-stage adder, CI is an input terminal for inputting a carry of the previous-stage adder, and SO is an output for outputting the addition result. The terminal CO is an output terminal for outputting the carry of the adder, and TG is a transfer gate for preventing the output of the addition result or the carry.

Next, the operation will be described. FIG. 1 shows an implementation of a 5-bit by 5-bit multiplication device using the carry save method. In the figure, the half adder H located at the uppermost stage
A inputs two partial products of the multiplier and the multiplicand, and outputs an addition result of two partial products and a carry. For example, the rightmost half adder HA has a partial product of x1y2 and x2y
The partial product of 1 is input, and p is the result of adding the two partial products.
2 (= x1y2 + x2y1) is output as a part of the multiplication result. If there is a carry associated with the addition of the two partial products, the carry of "1" is output to the lower full adder FA. If there is no carry, the carry of "0" is output to the lower full adder FA. Output to

When the full adder FA at the second stage from the top receives the addition result and the carry from the upper half adder HA, it adds the addition result, the carry and the partial product (the leftmost full adder FA). The FA does not receive the addition result from the top half adder HA, and thus adds the two partial products and the carry), and outputs the addition result and the carry. For example, the full adder FA located on the rightmost side is the second half adder H
The first carry from the top right of the result of addition of A and x1
A partial product of y3 is input, and p3, which is the result of addition, is output as a part of the multiplication result. If there is a carry due to the addition, a carry of "1" is output to the lower full adder FA, and if there is no carry, a carry of "0" is output to the lower full adder FA. .

As for the full adders FA of the third and subsequent stages from the top, similarly to the full adder FA of the second stage from the top, the addition result and the carry are output to obtain the multiplication results of p1 to p10. .

In the first embodiment, until the addition result of the preceding-stage adder is determined, the addition result of the lower-stage adder and the level of the carry transit without being stabilized, and the output transistor Tr is switched. In order to prevent the driving power from being wastefully consumed, the output timing control circuit C determines the addition result of the adder and the carry output until the addition result of the preceding half adder HA or full adder FA is determined. Block.

Specifically, for example, when the multiplication device is composed of five stages of adders, as shown in FIG. 4, the output timing control circuit C attached to each stage of the adder , The timing control signals TC1 to TC1
Give TC5.

For example, when there is a request to update the multiplication result at a frequency of 50 MHz, an H-level timing control signal TC1 is supplied to the uppermost adder in the first 10 MHz synchronization, and the adder of the adder is added. Although the output of the result and the carry is permitted, the L-level timing control signals TC2 to TC
5 is supplied, and the addition result of the adder and the output of the carry are blocked. In the next 10 MHz synchronization, H-level timing control signals TC1 and TC2 are supplied to the uppermost and second-stage adders, and the addition result and carry output of the adders are permitted. The L-level timing control signal TC3
To TC5, and the addition result of the adder and the output of the carry are blocked.

In the next 10 MHz synchronization, H-level timing control signals TC1 to TC3 are supplied to the adders at the uppermost stage and the second and third stages, and the addition results of the adders and the output of the carry are permitted. However, the L-level timing control signal TC
4, TC5, and the addition result of the adder and the output of the carry are blocked. In the next 10MHz synchronization,
H-level timing control signals TC1 to TC4 are supplied to the adders at the uppermost stage and the second to fourth stages, and the addition result of the adder and the output of the carry are permitted.
The L-level timing control signal TC5 is supplied to the adder of the stage, and the addition result of the adder and the output of the carry are prevented.

In the next 10 MHz synchronization, the H level timing control signals TC1 to TC
C5 is supplied, and the addition result of the adder and the output of the carry are permitted. As a result, the multiplication results of p1 to p10 can be obtained.

As is apparent from the above, the first embodiment
According to the configuration, the output timing control circuit C for preventing the output of the addition result and the carry is provided until the addition result of the half adder HA and the full adder FA is determined. Useless drive of the output transistor Tr can be prevented. Therefore, there is an effect that unnecessary power consumption can be prevented.

[0022]

As described above, according to the present invention, an output control circuit is provided to block the addition result and carry output until the addition result of the half adder and full adder is determined. Therefore, there is an effect that unnecessary power consumption can be prevented.

According to the present invention, the addition result and the carry output are blocked until the addition result of the adder is determined, thereby stabilizing the addition result and the carry level of the adder located below the adder. With such a configuration, useless power consumption can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a multiplication device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an internal configuration of a full adder FA and an output timing control circuit C;

FIG. 3 is a configuration diagram showing an internal configuration of a half adder HA and an output timing control circuit C;

FIG. 4 is a timing control signal TC1 to TC5.
FIG. 4 is an explanatory diagram showing an example of the timing of FIG.

FIG. 5 is a configuration diagram showing a conventional multiplication device.

FIG. 6 is a configuration diagram showing an internal configuration of a full adder FA.

FIG. 7 is a configuration diagram showing an internal configuration of a half adder HA.

[Explanation of symbols]

AI, BI Addition result input terminal, C output timing control circuit (output control circuit), CI carry input terminal, CO carry output terminal, FA full adder,
HA half adder, output terminal of SO addition result, TC1
TC5 timing control signal, Tr output transistor, TG transfer gate, p1 to p10
Multiplication result, x1 to x5 multiplicand, y1 to y5 multiplier.

Claims (2)

[Claims] 1. A multiplication device in which a half adder and a full adder are arranged in an array and outputs a result of multiplication of a multiplier bit and a multiplicand bit. A multiplication device comprising an output control circuit for preventing the output of the addition result and the carry. 2. A multiplication method for performing multiplication by a carry-save method using an adder, wherein the addition result and the carry output are blocked until the addition result of the adder is determined, whereby the adder is positioned at a lower stage. A multiplication method characterized by stabilizing an addition result of an adder and a carry level.