JP2004093667A - Liquid crystal driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress wasteful power consumption including occurrence of through current as much as possible in a liquid crystal driving circuit for driving a liquid crystal display panel of a simple matrix type. <P>SOLUTION: The liquid crystal driving circuit is provided with a first detection circuit 44 which detects a variation point of a frame reverse clock CKF for carrying out AC drive of the liquid crystal display panel, a second detection circuit 40 which detects a variation point of column display signals SEGDATA given to column electrodes and a third detection circuit 60 which detects a variation point of row scanning signals COMDATA given to row electrodes. Corresponding to respective detection signals in the first to third detection circuits, supply of driving voltage to the column electrodes and the row electrodes is temporarily stopped. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal drive circuit for driving a simple matrix type liquid crystal display panel.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a circuit for driving a simple matrix type liquid crystal display panel such as a TN (Twisted Nematic) or STN (Super Twisted Nematic) mode, an AC inversion drive is provided at the last stage of each circuit for driving a row electrode and a column electrode. Two pairs of MOS transistors corresponding to the ON / OFF voltages are provided, and a switching voltage VSS is applied to the gate of the MOS transistor at an appropriate timing to turn on the MOS transistor, so that a liquid crystal drive applied to the source is provided. Is supplied to the row electrode or the column electrode.
[0003]
However, each pair of MOS transistors may be turned on at the same time due to a slight timing shift, and a through current is generated between the liquid crystal driving voltage and the switching voltage VSS, so that current consumption is unnecessarily increased. Was one of the causes.
[0004]
Therefore, a circuit was considered in which a period in which both pairs of MOS transistors were turned off was provided at the application timing of the liquid crystal drive voltage so that the above simultaneous ON did not occur.
[0005]
FIG. 3 partially illustrates the configuration of such a circuit. Here, a circuit for driving one column electrode and one row electrode will be described.
In the figure, the column display signal SEGDATA is input to the EX NOR circuit 11, while the row scanning signal COMDATA is input to the EX NOR circuit 12. A clock CKF synchronized with frame inversion is input to each of the EX NOR circuits 11 and 12, and the output of the EX NOR circuit 11 is supplied to a flip-flop (hereinafter, referred to as “F / F”) 13 and the EX NOR circuit 12. The output is input to F / F14.
[0006]
The F / Fs 13 and 14 both output signals corresponding to the input contents based on the clock CKLCD synchronized with the data rewriting timing. The output of the F / F 13 is to the AND circuit 15 and the output of the F / F 14 is The signal is input to the AND circuit 16.
[0007]
A clock CKOFFB for temporarily turning off each MOS-FET to be described later is input to each of these AND circuits 15 and 16, and the output of the AND circuit 15 is sent to the level shifter 17 and the output of the AND circuit 16 is sent to the level shifter 18. Is done.
[0008]
The level shifter 17 boosts the signal voltage VDD supplied from the AND circuit 15 to a voltage VLCD suitable for the operation of the MOS-FET described later, and directly increases the boosted voltage VLCD to the n-channel MOS-FET 22 and the p-channel MOS-FET 23 , While being inverted via an inverter 19 and applied to the gates of a p-channel MOS-FET 21 and an n-channel MOS-FET 24.
[0009]
A voltage SEGVON for driving the column electrode on is applied to both sources of the MOS-FETs 21 and 22, and a voltage SEGVOFF for driving the column electrode off is applied to both sources of the MOS-FETs 23 and 24.
[0010]
Thus, the drains of the MOS-FETs 21 to 24 are connected collectively and output the display signal SEGOUT to the column electrode.
[0011]
On the other hand, the level shifter 18 boosts the signal voltage VDD supplied from the AND circuit 16 to a voltage VLCD suitable for the operation of the MOS-FET described later, and directly raises the boosted voltage VLCD to the n-channel MOS-FET 26 and the p-channel MOS -Apply to each gate of the FET 27 while inverting via the inverter 20 and apply to each gate of the P-channel MOS-FET 25 and the N-channel MOS-FET 28.
[0012]
A voltage COMVON for driving the row electrode on is applied to both sources of the MOS-FETs 25 and 26, and a voltage COMVOFF for driving the row electrode off is applied to both sources of the MOS-FETs 27 and 28.
[0013]
Thus, the drains of the MOS-FETs 25 to 28 are connected collectively, and the scanning signal COMOUT to the row electrode is output.
[0014]
In such a configuration, by providing AND circuits 15 and 16 for performing gate control based on a clock CKOFFB for temporarily turning off the MOS-FETs 21 to 28, the MOS-FETs 21 to 28 can be relatively easily mounted. A period in which both are turned off is provided to prevent simultaneous turning on of each FET. Therefore, it is possible to reliably prevent the flow of a through current that wastes current.
[0015]
[Problems to be solved by the invention]
However, in the case of the circuit configuration as described above, the AND circuits 15 and 16 continuously repeat the on / off operation even in a state where the drive waveforms of the column electrodes and the row electrodes do not change and a through current does not occur. As a result, power is consumed wastefully.
[0016]
This point becomes more prominent in recent years when the number of pixels of the liquid crystal display panel is increased and when column and row electrodes are driven by switching three or more voltage values such as multi-level driving.
[0017]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal drive circuit capable of minimizing wasteful power consumption including generation of a through current.
[0018]
[Means for Solving the Problems]
The invention according to claim 1 is a liquid crystal drive circuit for driving a simple matrix type liquid crystal display panel, wherein the first detection means detects a change point of an AC signal for AC driving the liquid crystal display panel. A second detecting means for detecting a changing point of a display signal applied to a column electrode of the liquid crystal display panel; a third detecting means for detecting a changing point of a scanning signal applied to a row electrode of the liquid crystal display panel; And a drive control means for temporarily stopping supply of a drive voltage to the column electrode and the row electrode in accordance with each detection signal of the first to third detection means.
[0019]
With such a configuration, useless power consumption including generation of a through current is suppressed, and the power supply can be used effectively.
[0020]
According to a second aspect of the present invention, in the first aspect of the present invention, the drive control means temporarily supplies a drive voltage to the column electrode and the row electrode in response to a detection signal of the first detection means. And the supply of the driving voltage to the column electrode is temporarily stopped in response to the detection signal of the second detection means, and the row electrode is stopped in response to the detection signal of the third detection means. The method is characterized in that the supply of the driving voltage to is temporarily stopped.
[0021]
With such a configuration, in addition to the operation of the first aspect of the present invention, the column electrode and the row electrode can be driven and controlled for each necessary system in accordance with the content of each detection signal. It can be suppressed as much as possible.
[0022]
According to a third aspect of the present invention, in the first aspect of the invention, at least one of the first to third detecting means is constituted by a differentiating circuit for differentiating a change point of an input signal. And
[0023]
With such a configuration, the detection circuit can be realized with a simple configuration in addition to the operation of the first aspect of the present invention.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a liquid crystal drive circuit according to the present invention will be described with reference to the drawings.
[0025]
FIG. 1 partially illustrates the circuit configuration. Here, a circuit for driving one column electrode and one row electrode is shown.
In the figure, a column display signal SEGDATA is input to a flip-flop (hereinafter, referred to as “F / F”) 31.
[0026]
The F / F 31 outputs a signal corresponding to the input content based on the clock CKLCD synchronized with the data rewriting timing. The output signal a is transmitted to the F / F 32, the EX OR circuit 33, and the AND circuit 34. In addition, the signal is inverted by the inverter 35 and then sent to the AND circuit 36.
[0027]
The F / F 32 also outputs a signal corresponding to the input content based on the clock CKLCD, and the output signal b is sent to the EX OR circuit 33.
The output signal c of the EX OR circuit 33 is directly sent to the NAND circuit 37, is also delayed for a predetermined time via a delay circuit 38, and is sent to the NAND circuit 37 as a signal d inverted by an inverter 39.
[0028]
The F / F 32, the EX OR circuit 33, the delay circuit 38, the inverter 39, and the NAND circuit 37 output a pulse synchronized with the change point when the column display signal SEGDATA changes. The output of the NAND circuit 37, which is a detection signal of the second detection circuit 40, is sent to the AND circuit 41.
[0029]
On the other hand, the frame inversion clock CKF synchronized with the frame period for AC driving of the liquid crystal display panel is directly input to the EX NOR circuit 42, and is also input to the EX NOR circuit 42 after being delayed by a delay circuit 43 for a predetermined time.
[0030]
The delay circuit 43 and the EX NOR circuit 42 constitute a first detection circuit 44 composed of a differentiating circuit that outputs a pulse synchronized with a change point when a change occurs in the frame inversion clock CKF for AC driving. The output of the EX NOR circuit 42, which is the detection signal, is sent to the AND circuits 41 and 45.
[0031]
The output signal e of the AND circuit 41 is sent to the AND circuit 34 and the AND circuit 36.
The output signal f of the AND circuit 34 is sent to the level shifter 46. The level shifter 46 boosts the voltage Ve of the signal f supplied from the AND circuit 34 to a voltage Vb suitable for the operation of the MOS-FET described later, and applies the boosted voltage Vb directly to the gate of the n-channel MOS-FET 47. On the other hand, it is inverted through an inverter 48 and applied to the gate of a p-channel MOS-FET 49.
[0032]
A voltage SEGVON for turning on the column electrode is applied to both sources of the MOS-FETs 47 and 49.
[0033]
The output signal g of the AND circuit 36 is sent to the level shifter 50. The level shifter 50 boosts the voltage Ve of the signal g supplied from the AND circuit 36 to a voltage Vb suitable for the operation of the MOS-FET described later, and applies the boosted voltage Vb directly to the gate of the n-channel MOS-FET 51. On the other hand, it is inverted through the inverter 52 and applied to the gate of the p-channel MOS-FET 53.
[0034]
A voltage SEGVOFF for driving the column electrode off is applied to both sources of the MOS-FETs 51 and 53.
[0035]
Thus, the drains of the MOS-FETs 47, 49, 51, and 53 are connected together and output a display signal SEGOUT to the column electrode.
[0036]
Further, the row scanning signal COMDATA is input to the F / F 54. The F / F 54 outputs a signal corresponding to the input content based on the clock CKLCD synchronized with the data rewriting timing. The output signal h is sent to the EX NOR circuit 55, the delay circuit 56, and the AND circuit 57. After being inverted by the inverter 58, the signal is sent to the AND circuit 59.
[0037]
The delay circuit 56 outputs the output signal h of the F / F 54 to the EX NOR circuit 55 with a predetermined delay. The EX NOR circuit 55 and the delay circuit 56 constitute a third detection circuit 60 that is a differentiation circuit that outputs a pulse synchronized with the change point when the row scanning signal COMDATA changes. The output of the EX NOR circuit 55, which is the detection signal, is sent to the AND circuit 45.
[0038]
The output signal i of the AND circuit 45 is sent to the AND circuits 57 and 59.
The output signal j of the AND circuit 57 is sent to the level shifter 61. The level shifter 61 boosts the voltage Ve of the signal j given from the AND circuit 57 to a voltage Vb suitable for the operation of the MOS-FET described later, and applies the boosted voltage Vb directly to the gate of the n-channel MOS-FET 62. On the other hand, it is inverted via the inverter 63 and applied to the gate of the p-channel MOS-FET 64.
[0039]
A voltage COMVON for turning on the row electrode is applied to both sources of the MOS-FETs 62 and 64.
[0040]
The output signal k of the AND circuit 59 is sent to the level shifter 65. The level shifter 65 boosts the voltage Ve of the signal k supplied from the AND circuit 59 to a voltage Vb suitable for the operation of the MOS-FET described later, and applies the boosted voltage Vb directly to the gate of the n-channel MOS-FET 66. On the other hand, it is inverted through the inverter 67 and applied to the gate of the p-channel MOS-FET 68.
[0041]
A voltage COMVOFF for turning off the row electrode is applied to both sources of the MOS-FETs 66 and 68.
[0042]
Thus, the drains of the MOS-FETs 62, 64, 66, and 68 are collectively connected to output a scanning signal COMOUT to the row electrode.
[0043]
Next, the operation of the above embodiment will be described.
[0044]
FIG. 2 shows the operation timing of each unit in FIG.
[0045]
In this figure, the voltages SEGVON and SEGVOFF for the column electrodes change as shown in FIGS. 2 (2) and (3) in synchronization with the frame inversion clock CKF shown in FIG. 2 (1). It is assumed that the voltages COMVON and COMVOFF for the row electrodes change as shown in FIGS.
[0046]
In addition, a clock CKLCD for operating the F / Fs 31, 32, 54 is given as shown in FIG. 2 (4).
[0047]
In the driving circuit of the column electrode system, the first detection circuit 44 operates so as to differentiate the change point of the frame inversion clock CKF. Therefore, the output of the EX NOR circuit 42 corresponds to each change point in FIG. This is as shown in (6), which is input to the AND circuit 41.
[0048]
On the other hand, when the column display signal SEGDATA to be applied to the column electrode is applied as shown in FIG. 2 (5), the output signal a of the F / F 31 operated by the clock CKLCD becomes as shown in FIG. 2 (7). Similarly, the output signal b of the F / F 32 in the second detection circuit 40 is further delayed by one cycle of the clock CKLCD, as shown in FIG.
[0049]
Therefore, the output signal c of the EX OR circuit 33 becomes as shown in FIG. 2 (9) by these signals a and b, and its delayed and inverted output signal d becomes as shown in FIG. 2 (10).
[0050]
By these signals c and d, the output signal of the NAND circuit 37, which is the detection output of the second detection circuit 40, corresponds to that shown in FIG. Become.
[0051]
As a result, the output signal e of the AND circuit 41 detects the change point of the frame inversion clock CKF from the output of the first detection circuit 44 and the output of the second detection circuit 40 as shown in FIG. When the column display signal SEGDATA changes, it always reacts when it occurs.
[0052]
This is supplied to the AND circuits 34 and 36 as a gate signal, and the column display signal SEGDATA is appropriately made valid for the signal a via the F / F 31 so that the output signals f and g are changed to those shown in FIGS. ), The gates of the MOS-FETs 47, 49, 51, and 53 are supplied as signals that turn off the gates corresponding to the detection results of the first detection circuit 44 and the second detection circuit 40.
[0053]
As a result, as shown in FIG. 2 (15), the display signal SEGOUT actually applied to the column electrode is temporarily and discretely provided at each change point of the potential in accordance with the pulse width of the signal e. Become.
[0054]
On the other hand, also in the row electrode drive circuit, the output of the EX NOR circuit 42, which is the detection output of the first detection circuit 44, is input to the AND circuit 45.
[0055]
On the other hand, when a row scanning signal COMDATA to be applied to the row electrodes is applied as shown in FIG. 2 (18), the output signal h of the F / F 54 operated by the clock CKLCD becomes as shown in FIG. 2 (19). The output signal of the EX NOR circuit 55, which is a detection signal of the third detection circuit 60, is as shown in FIG. 2 (20), which also corresponds only when a change occurs in the preceding and following data.
[0056]
As a result, the output signal i of the AND circuit 45 detects the change point of the frame inversion clock CKF from the output of the first detection circuit 44 and the output of the third detection circuit 60 as shown in FIG. When the row scanning signal COMDATA changes, it always responds to the change.
[0057]
This is supplied to AND circuits 57 and 59 as a gate signal, and the row scanning signal COMDATA is made effective as appropriate to the signal h via the F / F 54, so that the output signals j and k are changed as shown in FIGS. ), The gates of the MOS-FETs 62, 64, 66, and 68 are supplied as signals that turn off the gates in accordance with the detection results of the first detection circuit 44 and the third detection circuit 60.
[0058]
As a result, as shown in FIG. 2 (24), the scanning signal COMOUT actually applied to the row electrode is temporarily discretely provided according to the pulse width of the signal i at each change point of each potential. Become.
[0059]
As described above, at the changing point of the frame inversion clock CKF which is a signal for AC driving the liquid crystal display panel, since all the electrode voltages change, the first detection circuit 44 detects this and detects the column electrode system. , And the MOS-FETs 62, 64, 66, and 68 of the row electrode system are always turned off.
[0060]
In addition, at the changing point of the column display signal SEGDATA, a change in data before and after the change is detected by the second detection circuit 40, so that the MOS-FETs 47, 49, 51, 53 of the column electrode system are appropriately turned off. It was taken.
[0061]
Similarly, at the changing point of the row scanning signal COMDATA, a change in data before and after the changing point is detected by the third detection circuit 60, so that the MOS-FETs 62, 64, 66, and 68 of the row electrode system are appropriately turned off. did.
[0062]
Therefore, if a through current can be generated in accordance with the contents of the frame inversion clock CKF, the column display signal SEGDATA, and the row scanning signal COMDATA, the MOS-FET of the electrode drive system is turned off during the period without fail. Therefore, when it is considered that a through current does not occur, useless circuit operation is suppressed. Therefore, even when a battery having a limited capacity is used as a power source, the supply of the battery can be performed more efficiently for a long time. Power can be used.
[0063]
In the above-described embodiment, the first detection circuit 44, the second detection circuit 40, and the third detection circuit 60 are all described as being constituted by differentiating circuits. The circuit configuration of the present invention is not limited to the present embodiment, and may be configured by a circuit other than the differentiating circuit.
[0064]
In addition, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof.
[0065]
Further, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and the problem described in the column of the effect of the invention can be solved. If at least one of the effects described above can be obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.
[0066]
【The invention's effect】
According to the first aspect of the present invention, it is possible to suppress wasteful power consumption including generation of a through current and to effectively use a power supply.
[0067]
According to the second aspect of the present invention, in addition to the effect of the first aspect of the present invention, the driving of the column electrode and the row electrode can be controlled for each necessary system according to the content of each detection signal, so that wasteful power is consumed. Consumption can be minimized.
[0068]
According to the third aspect of the invention, in addition to the effects of the first aspect of the invention, the detection circuit can be realized with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a partial configuration of a liquid crystal drive circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart showing a signal processing state according to the embodiment;
FIG. 3 is a diagram showing a partial configuration of a liquid crystal drive circuit for a general simple matrix type liquid crystal display panel.
[Explanation of symbols]
11, 12 EX NOR circuits 13, 14 Flip-flop (F / F)
15, 16 AND circuits 17, 18, level shifters 19, 20 inverters 21, 23 (p-channel) MOS-FETs
22, 24 ... (n-channel) MOS-FET
31, 32 ... Flip-flop (F / F)
33 EX OR circuits 34, 36, 41, 45 AND circuits 35, 39, 48, 52 inverter 37 NAND circuit 38 delay circuit 40 second detection circuit 42 EX NOR circuit 43 delay circuit 44 First detection circuits 46, 50... Level shifters 47, 51... (N-channel) MOS-FET
49, 53 ... (p-channel) MOS-FET
54 ... Flip-flop (F / F)
55 EX NOR circuit 56 delay circuits 57, 59 AND circuits 58, 63, 67 inverter 60 third detection circuits 61, 65 level shifters 62, 66 (n-channel) MOS-FET
64, 68 ... (p-channel) MOS-FET

Claims (3)

A liquid crystal drive circuit for driving a simple matrix type liquid crystal display panel,
First detecting means for detecting a change point of an AC signal for AC driving the liquid crystal display panel;
Second detection means for detecting a change point of a display signal applied to a column electrode of the liquid crystal display panel;
Third detection means for detecting a change point of a scanning signal applied to a row electrode of the liquid crystal display panel;
A liquid crystal drive circuit comprising: drive control means for temporarily stopping supply of a drive voltage to the column electrode and the row electrode in response to each detection signal of the first to third detection means. . The drive control means includes:
Temporarily stopping the supply of the drive voltage to the column electrodes and the row electrodes in response to the detection signal of the first detection means,
Temporarily stopping the supply of the drive voltage to the column electrodes in response to the detection signal of the second detection means,
2. The liquid crystal drive circuit according to claim 1, wherein supply of a drive voltage to said row electrodes is temporarily stopped in response to a detection signal of said third detection means. 2. The liquid crystal driving circuit according to claim 1, wherein at least one of said first to third detecting means is constituted by a differentiating circuit for differentiating a change point of an input signal.

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