JP2002016449A - Switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching circuit capable of performing exact input switching by reducing a shock noise. SOLUTION: Concerning the switching circuit for selecting and outputting any one of the signals of plural systems while switching them through switching means (SW1-SWN), this circuit has a filter circuit (13) for lowering a cutoff frequency at the switching timing of the switching means (SW1-SWN) so that the shock noise generated in an output signal can be reduced and exact input switching can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit, and more particularly, to a switching circuit that switches and selects a plurality of signals by switching means and outputs the selected signal.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration diagram of an example of a conventional switching circuit. This switching circuit 30 is used as a selector of an audio device.

[0003] In the figure, for example, a radio audio signal, an audio signal reproduced by a CD, an audio signal reproduced by an MD, and the like are input to input terminals IN1 to INN, respectively, and supplied to switches SW1 to SWN, respectively. Is done. Switch SW1
The other ends of SWN to SWN are commonly connected, and are connected to one end of the resistor R1 and the output terminal OUT1. The other end of the resistor R1 is grounded. One of the switches SW1 to SWN is turned on by a switching control signal from the control terminal 31. When the switch SW2 is turned on as shown in FIG. 4, an audio signal is output from the output terminal OUT1.

FIG. 5 is a configuration diagram of an example of an analog switch used as the switches SW1 to SWN. FIG.
The analog switch 37 shown in FIG.
Let it be W2. The analog switch 37 has a control terminal CONT to which a switching control signal is input, an input terminal IN2 to which a signal is input, and an output terminal OUT2.

[0005] The analog switch 37 comprises an inverter 35 and a transmission gate 36. The switching control signal is supplied from the control terminal CONT to the inverter 35, and the supplied switching control signal is inverted and supplied to the transmission gate 36.

The transmission gate 36 turns on and off in response to a switching control signal and an inversion control signal supplied from the inverter 35. When the switching control signal is at a high level, the transmission gate 36 is turned on.
The signal supplied from the input terminal IN2 to the output terminal OU
Supply to T2.

By the way, the transmission gate 36
Are present between the gate and the source of the MOS transistor constituting. Since the resistance R1 shown in the figure is connected to the output terminal OUT2, a differentiating circuit is equivalently constituted by the parasitic capacitances C2 and C3 and the resistance R1.

FIG. 6 is a signal waveform diagram of each part of the analog switch. When the switching control signal shown in FIG. 6A is supplied from the control terminal CONT, the differential waveform shown in FIG. 6B appears at the output terminal OUT2, and the output terminal OUT2
2 is output as shock noise.

FIG. 7 is a block diagram showing another example of a conventional switching circuit. The mute switching circuit 40 is used as a mute selector for switching the mute state of the audio device.

In FIG. 1, for example, a radio audio signal, an audio signal reproduced on a CD, an audio signal reproduced on an MD, and the like are input to input terminals IN1 to INN, respectively, and supplied to switches SW1 to SWN, respectively. Is done. Switch SW1
The other ends of .about.SWN are commonly connected, connected to the contact a of the mute switch, and grounded via the resistor R1. One of the switches SW1 to SWN is turned on by a switching control signal from the control terminal 41.

The mute switch 42 has a contact b grounded and a movable contact connected to the output terminal OUT1. The mute switch 42 includes switches SW1 to S
When the WN is switched, it is switched to be grounded.

[0012]

In the analog switch shown in FIG. 5, it is necessary to increase the size of the MOS transistor constituting the switch in order to suppress the on-resistance when the switch is turned on. for that reason,
When the transistor size is increased, the parasitic capacitances C2, C2
3 increases. In the switching circuit illustrated in FIG. 4 including the analog switch including the transistor having the large parasitic capacitance, the time constant of the differentiation circuit based on the parasitic capacitance of the transistor and the load resistor R1 provided in the switching circuit is large. However, there is a problem that a large shock noise is generated.

In the mute switching circuit 40 shown in FIG. 7, shock noise due to switching of the mute switch 42 is likely to occur.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-mentioned conventional problems, to provide a switching circuit capable of reducing shock noise and performing appropriate input switching.

[0015]

According to a first aspect of the present invention, there is provided a switching circuit for selectively selecting and outputting a plurality of signals by switching means (SW1 to SWN). A filter circuit (13) for lowering the cutoff frequency at the switching timing is provided.

According to the first aspect of the present invention, the filter circuit (13) includes a switching unit (S) for switching a plurality of signals.
By outputting a low cutoff frequency at the switching timing of W1 to SWN), it is possible to reduce shock noise generated in a signal and perform an appropriate input switching.

According to a second aspect of the present invention, the filter circuit (13) has a conductance amplifier (11), a capacitor (C1), and a buffer amplifier (12), and switches the conductance of the conductance amplifier (11). And a signal switching means (SWM) for switching the cutoff frequency.

According to the second aspect of the present invention, by using a filter circuit (13) having a conductance amplifier (11), a buffer amplifier (12), and a capacitor (C1) for switching a cutoff frequency by switching a conductance. In addition, shock noise generated at the time of switching can be reduced.

The reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0020]

FIG. 1 is a block diagram showing an embodiment of a switching circuit according to the present invention. This switching circuit 10 is used as a selector of an audio device.

In FIG. 1, for example, a radio audio signal, an audio signal reproduced by a CD, an audio signal reproduced by an MD, and the like are input to input terminals IN1 to INN, respectively, and supplied to switches SW1 to SWN, respectively. Is done. Switch SW1
SWN are commonly connected to one end of the resistor R1 and one end of the filter circuit 13. The other end of the resistor R1 is grounded, and the other end of the filter circuit 13 is connected to an output terminal O
Connected to UT1. The switches SW1 to SWN are
Either one is turned on by the switching control signal from the control terminal 15. When the switch SW2 is turned on as shown in FIG. 1, an audio signal is output from the output terminal OUT1 via the filter circuit 13.

The filter circuit 13 includes a conductance amplifier 11, a capacitor C1, and a buffer amplifier 12. The conductance amplifier 11 has one end of the resistor R1 connected to the non-inverting input terminal, the output terminal of the buffer amplifier 12 connected to the inverting input terminal, and the output terminal of the conductance amplifier 11 grounded via the capacitor C1. It is connected to the input terminal of the buffer amplifier 12. The conductance amplifier 11 is supplied with an audio signal switched and selected by the switches SW1 to SWN to a non-inverting input terminal. The output terminal of the buffer amplifier 12 is connected to the output terminal OUT1.

The conductance amplifier 11 is supplied with a switching control signal from a control terminal 14, and the conductance amplifier 11 switches the mutual conductance gm in accordance with the switching control signal. The cutoff frequency is switched. Here, when the gm of the conductance amplifier 11 is large, the internal resistance of the conductance amplifier 11 is small, and the cutoff frequency of the low-pass filter equivalently constituted by the internal resistance and the capacitor C1 is high. When gm becomes small, the cutoff frequency of the low-pass filter becomes low.

In the present invention, when the switches SW1 to SWN are switched, the cutoff frequency of the filter circuit 13 is switched to reduce the shock noise generated in the output signal.

FIG. 2 shows output timings of the switches SW1 to SWN and the filter circuit 13. The switching signal in FIG. 2A rises at time t2, falls at time t5, and for example, switches SW1 are turned on at times t2 to t5. At time t1 before the switching signal in FIG. 2A rises from off to on at time t2, the switching control signal in FIG. 2C changes from high level to low level. FIG.
The conductance amplifier 11 is operated by the switching control signal (C).
Is switched from the value g2 to the value g1 as shown in FIG.

The switching signal shown in FIG.
At time t3 after rising at step 2, the switching control signal in FIG. 2C changes from low level to high level. The gm value of the conductance amplifier 11 is switched from the value g1 to the value g2 as shown in FIG. 2B by the switching control signal of FIG.

Similarly, the switching signal shown in FIG. 2A is turned on at time t4 before falling from on to off at time t5.
Thus, the switching control signal in FIG. 2C changes from the high level to the low level. The gm value of the conductance amplifier 11 is switched from the value g2 to the value g1 by the switching control signal of FIG. 2C, as shown in FIG. 2B.

The switching signal shown in FIG.
At time t6 after falling at 5, the switching control signal in FIG. 2C goes from low to high. The gm value of the conductance amplifier 11 is switched from the value g1 to the value g2 as shown in FIG. 2B by the switching control signal of FIG.

As described above, the gm is largely switched by the switching control signal supplied to the filter circuit 13 when the switches SW1 to SWN for switching the audio signal are turned on and off, so that the cut-off frequency of the low-pass filter is reduced, and Can be reduced.

FIG. 3 is a diagram showing a filter circuit according to one embodiment of the present invention. In the figure, a pnp transistor Q1
2, Q13 forms a differential circuit. The base of the pnp transistor Q12 is connected to the input terminal 130,
The base of the transistor Q13 is connected to the output terminal 131. The emitters of the transistors Q12 and Q13 are connected by a resistor R8, and the current sources 20 and
21. The current sources 20 and 21 are connected to the power source Vc
c, and the current Is is applied to the transistors Q12 and Q13.
Supplied to The collectors of the transistors Q12 and Q13 are connected to the bases and collectors of the npn transistors Q10 and Q11. Transistors Q10, Q in diode configuration with base and collector short-circuited
The eleventh emitter is grounded via a resistor R9.

The pnp transistors Q18, Q1
9, Q52, Q53, and npn transistor Q54 are configured to remove offset. Transistor Q5
The reference voltage Vref is supplied to the base of the reference numeral 4.
The bases of the transistors Q52 and Q53 are commonly connected,
The current mirror circuit is formed by being connected to the collector of the transistor Q54. The emitters of the transistors Q52 and Q53 are connected to the collectors of the transistors Q18 and Q19. Transistors Q18, Q1
The bases 9 are commonly connected and connected to the emitter of the transistor Q53 to form a current mirror circuit.
The emitters of the transistors Q18 and Q19 are connected to a resistor R1.
0 and R11 are connected to the power supply Vcc.

The collector of the transistor Q53 is grounded via the capacitor C1, and connected to the base of the pnp transistor Q58 via the resistor R38. The emitter of the transistor Q54 is connected to the base of a pnp transistor Q57 for offset compensation, the emitter of the transistor Q57 is connected to the current source 23, supplied with the current I1, and the collector is grounded to form an emitter follower circuit. ing.

The emitter of the transistor Q58 is connected to the current source 24, supplied with the current I1, and the collector is grounded to form an emitter follower circuit.

The emitter of the transistor Q58 is
Connected to the base of npn transistor Q21, the collector of transistor Q21 is connected to power supply V via resistor R33.
Connected to cc. The emitter of the transistor Q21 is connected to the current source 27 to form an emitter follower circuit, and is also connected to the output terminal 131. The transistors Q57 and Q58 correspond to the buffer amplifier 1 of FIG.
Corresponds to 2.

The collectors of the transistors Q12 and Q13 are connected to the bases of npn transistors Q17 and Q16 forming a differential circuit. The emitters of the transistors Q16 and Q17 are connected to the collectors of npn transistors Q36 and Q20. The emitters of the transistors Q36 and Q20 are connected to a resistor R
16, grounded via R12.

The bases of the transistors Q36 and Q20 are
It is connected to bases and collectors of npn transistors Q23 and Q22. The transistors Q36 and Q23 form a current mirror circuit.
Q22 forms a current mirror circuit. The collector of the transistor Q22 is connected to the current source 25, and the current I2
Is supplied. The collector of the transistor Q23 is connected to one end of the switch SWM. Switch SWM
The other end is connected to the current source 26, and the current I2 is supplied from the current source 26. This switch SWM has a switching terminal 1
4 is switched according to the switching control signal from the control unit 4.

As described above, when the switch SWM is switched, the value of gm changes. The value of gm is represented by the following equation.

[0038]

(Equation 1) In the above equation, q is a charge, k is a Boltzmann constant, T is an absolute temperature [° C.], Ix is an emitter current of the transistors Q16 and Q17, that is, a collector current of the transistors Q20 and Q36, and Is is a current source 20, 21. , R8 indicates a resistor R8.

When the switch SWM is on, the current source 25,
The current I2 from 26 flows to the emitters of the transistors Q22 and Q23, and the same amount of current I2
0, 36, the transistor Q1
6, the current Ix flowing through the differential circuit constituted by Q17 is determined.

On the other hand, when the switch SWM is off, only the current I2 from the current source 25 flows to the collector of the transistor Q22 and the emitter of the transistor Q20, and the current Ix is lower than when the switch SWM is on.

As described above, when the current Ix changes due to the on / off switching of the switch SWM, the value of gm shown in Expression 1 also changes.

As described above, the signal supplied to the filter circuit 13 can be output while changing the value of gm by switching the switch SWM.

[0043]

As described above, according to the switching circuit of the first aspect, the filter circuit generates a signal by outputting a low cutoff frequency at the switching timing of the switching means for switching a plurality of signals. Shock noise can be reduced and accurate input switching can be performed.

Further, as described above, according to the switching circuit of the second aspect, by using the filter circuit having the conductance amplifier, the buffer amplifier, and the capacitor for switching the cutoff frequency by switching the conductance, a shock generated at the time of the switching is achieved. Noise can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a switching circuit according to the present invention.

FIG. 2 shows output timings of switches SW1 to SWN and a filter circuit 13.

FIG. 3 is a diagram showing a filter circuit according to an embodiment of the present invention.

FIG. 4 shows a configuration diagram of an example of a conventional switching circuit.

FIG. 5 is a configuration diagram of an example of an analog switch used as switches SW1 to SWN.

6 is a signal waveform diagram of each part of the analog switch shown in FIG.

FIG. 7 shows a configuration diagram of another example of a conventional switching circuit.

[Explanation of symbols]

10, 30, 40 Switching circuit 11 Conductance amplifier 12 Buffer amplifier 13 Filter circuit 20-27 Current source 42 Mute switch R8-12, R16, R33, R38 Resistance Q10-13, Q16-21, Q36, Q38, Q52
-54, Q57, Q58 Transistor IN1-INN input terminal SW1-SWN, M switch OUT1 output terminal

Continued on the front page F term (reference) 5J092 AA02 AA51 CA41 FA20 HA08 HA19 HA25 HA29 HA38 KA02 KA03 KA05 KA09 KA41 MA01 MA21 SA05 TA01 TA06 5J098 AA02 AA04 AA11 AB02 AB03 AB12 AB13 AC02 AC10 AC20 AC22 AC27 AD11 AD14 CA02

Claims (2)

[Claims] 1. A switching circuit for switching and selecting a signal of a plurality of systems by a switching unit and outputting the signal, comprising a filter circuit for lowering a cutoff frequency at a switching timing of the switching unit. 2. The filter circuit according to claim 1, wherein the filter circuit includes a conductance amplifier, a capacitor, and a buffer amplifier, and further includes signal switching means for switching the conductance of the conductance amplifier to switch the cutoff frequency. Switching circuit.