JP2002016364A - Capacitor-containing ceramic multilayer board and its manufacturing method - Google Patents

Capacitor-containing ceramic multilayer board and its manufacturing method

Info

Publication number
JP2002016364A
JP2002016364A JP2000200063A JP2000200063A JP2002016364A JP 2002016364 A JP2002016364 A JP 2002016364A JP 2000200063 A JP2000200063 A JP 2000200063A JP 2000200063 A JP2000200063 A JP 2000200063A JP 2002016364 A JP2002016364 A JP 2002016364A
Authority
JP
Japan
Prior art keywords
capacitor
dielectric
dielectric layer
ceramic multilayer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000200063A
Other languages
Japanese (ja)
Inventor
Masato Nakamura
真人 中村
Shosaku Ishihara
昌作 石原
Nobuhito Katsumura
宣仁 勝村
Bunichi Tagami
文一 田上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000200063A priority Critical patent/JP2002016364A/en
Publication of JP2002016364A publication Critical patent/JP2002016364A/en
Pending legal-status Critical Current

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  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress characteristics from deteriorating due to the mutual reaction of a ceramic multilayer wiring board with a sintering atmosphere and process it to contain fine capacitors at a high positional accuracy. SOLUTION: Fine capacitors each composed of an electrode foil held on a film and a dielectric on the electrode and a counter electrode are formed. The capacitor has a structure sealed at the side faces with an atmosphere sealing material. The capacitors are positioned and transferred to green sheets, and they are sintered after laminating and compression bonding them. Thus a multilayer board containing the capacitors is manufactured at a high positional accuracy.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、外来ノイズや不要
輻射による半導体の誤動作を防止するためのコンデンサ
を内蔵した機能モジュールを構成するのに好適な多層回
路基板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board suitable for forming a functional module having a built-in capacitor for preventing malfunction of a semiconductor due to external noise and unnecessary radiation, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】半導体素子収納用パッケージでは、半導
体集積回路は外来ノイズや不要輻射により誤動作を生じ
易いために、例えば大形計算機では10nF程度の容量を
持ったセラミックコンデンサを電源側と接地側との間に
挿入する事により、ノイズを吸収し誤動作を防止してい
た。従来はこのコンデンサの接続をパッケージとは別に
外付けにより行っていた。しかしながら、従来では、上
記したように外来ノイズや不要輻射による誤作動を防止
するためのセラミックコンデンサを外付けしていたた
め、基板やパッケージの実装密度の向上を図る事が出来
なかった。
2. Description of the Related Art In a semiconductor device housing package, a semiconductor integrated circuit is liable to malfunction due to external noise or unnecessary radiation. For example, a large-sized computer has a ceramic capacitor having a capacitance of about 10 nF between a power supply side and a ground side. By inserting between them, noise was absorbed and malfunction was prevented. Conventionally, this capacitor was connected externally separately from the package. However, conventionally, as described above, a ceramic capacitor for preventing malfunction due to extraneous noise or unnecessary radiation is externally attached, so that the mounting density of a substrate or a package cannot be improved.

【0003】そこで、基板やパッケージの実装密度の向
上を可能とする方法として、基板内にコンデンサを形成
し内蔵する方法が有る。従来この種のノイズ対策が施さ
れたセラミック多層基板として、セラミック多層基板の
下部にコンデンサ部が形成されたものが提案されている
(特開昭59−145536号公報)。
Therefore, as a method for improving the mounting density of a substrate or a package, there is a method of forming a capacitor in a substrate and incorporating the capacitor therein. Hitherto, as a ceramic multilayer substrate which has been provided with this kind of noise countermeasure, a ceramic multilayer substrate in which a capacitor portion is formed below a ceramic multilayer substrate has been proposed (Japanese Patent Application Laid-Open No. 59-145536).

【0004】こうしたコンデンサを内蔵したセラミック
多層回路基板の製造方法としては、特開平9−9298
3号や特開平9−139578号がある。前者は導体ペ
ースト及び誘電体ペーストをグリーンシートに印刷し、
後者は導体ペーストをグリーンシートに印刷し電極を形
成し、誘電体のグリーンシートを挟持し、その後積層圧
着し同時焼結してコンデンサを内蔵したセラミック多層
回路基板形成する方法である。
A method of manufacturing a ceramic multilayer circuit board having such a built-in capacitor is disclosed in Japanese Patent Application Laid-Open No. 9-9298.
No. 3 and JP-A-9-139578. The former prints conductor paste and dielectric paste on green sheets,
The latter is a method in which a conductor paste is printed on a green sheet to form an electrode, a dielectric green sheet is sandwiched, laminated and pressed, and simultaneously sintered to form a ceramic multilayer circuit board with a built-in capacitor.

【0005】しかし、基板材料であるセラミック材料と
コンデンサを形成する誘電体材料では、組成が異なり焼
成収縮特性も相違するため、両者を積層して同時焼成す
ると、両者の焼成収縮特性の相違により基板に反りやク
ラック、歪みが発生しやすい。更に、セラミック材料の
焼結終了温度と誘電体材料の焼結終了温度が一致しない
場合には、どちらかの材料の焼結層の緻密度が低下す
る。この場合、セラミック材料の焼結層の緻密度が低下
した場合には、基板内の配線導体間の絶縁特性が低下し
たり、セラミック絶縁部の機械強度が著しく低下する。
逆に、誘電体材料の焼結層の緻密度が低下した場合に
は、コンデンサの誘電体の絶縁特性や誘電率が低下す
る。さらに導体金属の融点以上の焼結温度を有する誘電
体材料を適用する事が出来ない。例えば、融点が108
3℃である銅を導体に用いた銅/ガラスセラミック基板
では焼結に1200℃程度の高温が必要なPZTを誘電
体に用いる事は不可能である。
However, since the ceramic material as the substrate material and the dielectric material forming the capacitor have different compositions and different firing shrinkage characteristics, when both are laminated and fired simultaneously, the substrate shrinks due to the difference in firing shrinkage characteristics. Warpage, cracks and distortion are likely to occur. Further, when the sintering end temperature of the ceramic material does not match the sintering end temperature of the dielectric material, the density of the sintered layer of either material is reduced. In this case, when the denseness of the sintered layer of the ceramic material is reduced, the insulation characteristics between the wiring conductors in the substrate are reduced, and the mechanical strength of the ceramic insulating portion is significantly reduced.
Conversely, when the denseness of the sintered layer of the dielectric material decreases, the insulating properties and the dielectric constant of the dielectric of the capacitor decrease. Furthermore, a dielectric material having a sintering temperature equal to or higher than the melting point of the conductor metal cannot be used. For example, the melting point is 108
In the case of a copper / glass ceramic substrate using copper at 3 ° C. as a conductor, it is impossible to use PZT, which requires a high temperature of about 1200 ° C. for sintering, as a dielectric.

【0006】また、コンデンサの電気容量Cはコンデン
サ面積S(m2)、誘電体の比誘電率εs、真空の誘電率ε0
(F/m)誘電体厚さt(m)からC=εsε0S/ tで与え
られる。したがってコンデンサを微細化するためには高
誘電率の誘電体を用いるか、誘電体厚さを小さくする必
要がある。例えば1mm角のコンデンサで、C=10n
Fを得るためには比誘電率ε=1000の誘電体を用い
ても、誘電体厚さt=1.13μmとしなければならな
い。しかしながら前記の従来技術であるグリーンシート
法では、取り扱い時の破れ等の問題が生じない強度を得
るためにグリーンシート数十μm以上の厚さが必要であ
り、焼結体の厚さを数μmにする事は困難である。また
誘電体ペースト法ではグリーンシート法に比べ誘電体厚
さを小さくする事は可能だが、印刷膜厚が薄くなるほど
印刷のかすれやピンホールが発生し、焼結後にショート
が発生しやすくなるという問題がある。
The capacitance C of the capacitor is determined by the capacitor area S (m2), the dielectric constant εs of the dielectric, and the dielectric constant ε0 of the vacuum.
(F / m) From the dielectric thickness t (m), it is given by C = εsε0S / t. Therefore, in order to miniaturize the capacitor, it is necessary to use a dielectric having a high dielectric constant or to reduce the thickness of the dielectric. For example, a 1 mm square capacitor, C = 10n
In order to obtain F, the dielectric thickness t must be 1.13 μm even if a dielectric having a relative permittivity ε = 1000 is used. However, in the above-mentioned conventional green sheet method, the thickness of the green sheet is required to be several tens μm or more in order to obtain a strength that does not cause a problem such as breakage during handling. It is difficult to do. In addition, the dielectric paste method can reduce the dielectric thickness compared to the green sheet method, but the thinner the printed film thickness, the more blurred the print or pinholes, and the more likely it is that short circuits will occur after sintering. There is.

【0007】ところが、形成されたコンデンサの例えば
ショート等の不良は焼結が終了するまで評価する事は不
可能であり、製造コスト上昇の原因となる。
However, a defect such as a short circuit of the formed capacitor cannot be evaluated until the sintering is completed, which causes an increase in manufacturing cost.

【0008】そこで、あらかじめコンデンサを焼成し、
この焼成済のコンデンサをグリーンシートに挟み込んで
加圧焼結する方法として特開平5−163072に示す
方法がある。
Therefore, the capacitor is fired in advance,
As a method of sandwiching the fired capacitor between green sheets and sintering under pressure, there is a method disclosed in JP-A-5-163072.

【0009】[0009]

【発明が解決しようとする課題】しかしながら半導体素
子上の回路の高密度化にともなう半導体素子の端子数の
増大と半導体素子の基板への実装密度の高密度化を図る
ためには、コンデンサの微細化の他に、微細なコンデン
サを高位置精度で基板に内蔵させる必要がある。さら
に、前記従来技術では、焼結中に導体金属が酸化するの
を抑止する必要であるが、その様な雰囲気では誘電体の
特性が劣化する場合がある。例えばPZTの様な鉛系の
誘電体材料は一般に非酸化性雰囲気での焼成で誘電特性
は著しく低下する。
However, in order to increase the number of terminals of the semiconductor element and increase the mounting density of the semiconductor element on the substrate with the increase in the density of circuits on the semiconductor element, it is necessary to reduce the size of the capacitor. In addition to this, it is necessary to incorporate a fine capacitor into the substrate with high positional accuracy. Furthermore, in the above-mentioned conventional technology, it is necessary to prevent the conductive metal from being oxidized during sintering. However, in such an atmosphere, the characteristics of the dielectric may be deteriorated. For example, the dielectric properties of a lead-based dielectric material such as PZT generally deteriorate significantly when fired in a non-oxidizing atmosphere.

【0010】本発明は前記従来技術の課題を解決するた
めにコンデンサの微細化が可能で、予め不良を除去する
事ができ、焼成時の雰囲気の影響を抑制するコンデンサ
内蔵セラミック多層配線基板の製造方法を開発したもの
である。この方法はあらかじめフィルム上に保持した電
極箔と該電極上の誘電体及び対極電極と、側面を雰囲気
シール材で封止した構造を有するコンデンサを一括して
作成し、該コンデンサを位置合わせし、グリーンシート
に転写し、積層圧着後に焼結し、コンデンサ内蔵多層基
板を製造する方法である。
In order to solve the above-mentioned problems of the prior art, the present invention makes it possible to miniaturize a capacitor, remove defects beforehand, and manufacture a ceramic multilayer wiring board with a built-in capacitor that suppresses the influence of the atmosphere during firing. The method was developed. In this method, an electrode foil previously held on a film, a dielectric and a counter electrode on the electrode, and a capacitor having a structure in which the side surfaces are sealed with an atmosphere sealing material are collectively created, and the capacitors are aligned. This is a method of producing a multilayer substrate with a built-in capacitor by transferring the image to a green sheet, sintering after laminating and pressing.

【0011】[0011]

【課題を解決するための手段】本発明者はこれらの課題
に対して検討を行った結果、フィルム上に保持した金属
箔上に誘電体層を形成し、該誘電体層上に電極を形成
し、該誘電体層の側面を例えばアルミナ(Al2O3)
マグネシア(MgO)シリカ(SiO2)等の高融点酸
化物等のシール材で封止して製造したコンデンサの特性
を評価し、位置合わせし、グリーンシートに転写し、積
層焼結を行うことにより、所望の特性を持つ多数の微細
コンデンサを高位置精度で基板内に配置する事によっ
て、外来ノイズや不要輻射による半導体素子の誤動作を
防止できる事を見出し、本発明に至った。
Means for Solving the Problems As a result of studying these problems, the present inventors formed a dielectric layer on a metal foil held on a film, and formed an electrode on the dielectric layer. Then, the side surface of the dielectric layer is made of, for example, alumina (Al2O3)
By evaluating the characteristics of the capacitor manufactured by sealing with a sealing material such as a high melting point oxide such as magnesia (MgO) silica (SiO2), aligning, transferring to a green sheet, and performing lamination sintering, By arranging a large number of fine capacitors having desired characteristics in a substrate with high positional accuracy, it has been found that malfunction of a semiconductor element due to external noise and unnecessary radiation can be prevented, and the present invention has been accomplished.

【0012】誘電体層、電極、シール層は電子ビーム蒸
着法、活性化反応性蒸着(ARE)法、スパッタ法、ク
ラスタイオンビーム(ICB)法、イオンビームスパッ
タ(IBS)法、化学気相結晶成長(CVD)法、原子
層エピタキシャル(ALE)成長法、分子線エピタキシ
ャル(MBE)成長法、ガスソース(MBEまたはCB
E)法、エレクトロンサイクロトロン共鳴(ECR)等
の既知の結晶成長技術及び非結晶薄膜形成技術を用いて
真空中や各種の制御雰囲気下で形成する事ができる。
The dielectric layer, electrode and seal layer are formed by electron beam evaporation, activated reactive evaporation (ARE), sputtering, cluster ion beam (ICB), ion beam sputtering (IBS), and chemical vapor deposition. Growth (CVD), atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source (MBE or CB)
It can be formed in a vacuum or under various control atmospheres by using a known crystal growth technique such as E), electron cyclotron resonance (ECR) or the like, and an amorphous thin film forming technique.

【0013】コンデンサのパターン形成は、該コンデン
サの材料、及び形成条件に応じて、如何なるタイミング
で行っても良い。例えば、フィルム上に保持した金属箔
をフォトエッチ法でパターン形成し、次いで誘電体層、
対極電極、誘電体層、側面の雰囲気封止層を形成した
り、誘電体層を形成し、次に該誘電体層をマスクとして
エッチングによりパターン形成したり、対極電極、誘電
体層、側面の雰囲気封止層の全てを形成した後、フォト
エッチ法でパターン形成する事が可能である。
The pattern formation of the capacitor may be performed at any timing according to the material of the capacitor and the forming conditions. For example, a metal foil held on a film is patterned by a photoetch method, and then a dielectric layer,
A counter electrode, a dielectric layer, an atmosphere sealing layer on the side surface is formed, a dielectric layer is formed, and then a pattern is formed by etching using the dielectric layer as a mask, and a counter electrode, a dielectric layer, and a side surface are formed. After forming the entire atmosphere sealing layer, it is possible to form a pattern by a photoetching method.

【0014】また誘電体層は誘電体結晶を電極上に直接
生成させる他に、同一組成の非晶質膜を形成し、焼結時
の熱履歴や焼結プロファイルに非晶質膜の結晶化段階を
取り入れる事によって結晶化させ、高誘電率の誘電体層
を得る事が可能である。
In addition to forming a dielectric crystal directly on the electrode, the dielectric layer also forms an amorphous film having the same composition, and the heat history and sintering profile at the time of sintering cause the crystallization of the amorphous film. It is possible to obtain a dielectric layer having a high dielectric constant by crystallizing by incorporating steps.

【0015】[0015]

【発明の実施の形態】以下、本発明の実施例により具体
的に説明するが、本発明はこれら実施例に限定されな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.

【0016】実施例1 ガラスセラミック多層配線基板の製造方法は、図1に示
す様に、まず厚さ9μmの銅箔1上に鉛βジケトン錯体
Pb(C11H19O2)2、Zr(O・t−C4H
9)、4Ti(O・i−C3H7)、O2を原料とし、
全圧660Pa、620℃で厚さ1μmの所望のパター
ンのPZT誘電体層2をMOCVD法で形成する。
Example 1 As shown in FIG. 1, a method for manufacturing a glass ceramic multilayer wiring board is as follows. First, a lead β-diketone complex Pb (C11H19O2) 2 and Zr (Ot-C4H) are formed on a copper foil 1 having a thickness of 9 μm.
9) Using 4Ti (OiC3H7) and O2 as raw materials,
A PZT dielectric layer 2 having a desired pattern with a total pressure of 660 Pa and a thickness of 1 μm at 620 ° C. is formed by MOCVD.

【0017】次にCuの対極電極3を形成し、さらにM
gOの側面雰囲気シール層4をプラズマスパッタ法を用
いて形成する。
Next, a Cu counter electrode 3 is formed.
A side atmosphere sealing layer 4 of gO is formed by using a plasma sputtering method.

【0018】次に厚さ200μmのポリエステルフィル
ム5に軟化温度200℃の熱可塑性のフィルム6を用
い、該銅箔を、200℃で10kg/cm2で30分保
持し熱圧着する。
Next, using a thermoplastic film 6 having a softening temperature of 200 ° C. on a polyester film 5 having a thickness of 200 μm, the copper foil is held at 200 ° C. at 10 kg / cm 2 for 30 minutes and thermocompression-bonded.

【0019】次に余分な銅箔部をフォトエッチ処理にて
除去し、電極パターンを形成する。この電極パターンは
コンデンサ電極部とその端部に特性評価を行うための取
り出し電極を備えた形状にすると、形成されたコンデン
サの評価が容易であった。
Next, an excess copper foil portion is removed by photoetching to form an electrode pattern. When this electrode pattern was formed into a shape having a capacitor electrode portion and an extraction electrode for evaluating the characteristics at the end thereof, the formed capacitor was easily evaluated.

【0020】次に形成したコンデンサの電気容量を測定
し、ショート不良や電気容量が10nF以下であったコ
ンデンサを機械的に除去した。
Next, the electric capacity of the formed capacitor was measured, and the short-circuit failure and the capacitor whose electric capacity was 10 nF or less were mechanically removed.

【0021】次にグリーンシートを作成するためのスラ
リーをつくる。
Next, a slurry for forming a green sheet is prepared.

【0022】スラリーの製造方法は平均粒径3μmの軟
化温度820℃のホウケイ酸ガラス粉末63重量部に平
均粒径3μmのムライト粒子37重量部、アクリル系バ
インダ17重量部を加えボールミルで24h湿式混合し
て作製する。
The slurry is prepared by adding 37 parts by weight of mullite particles having an average particle diameter of 3 μm and 17 parts by weight of an acrylic binder to 63 parts by weight of borosilicate glass powder having an average particle diameter of 3 μm and a softening temperature of 820 ° C., and wet-mixing with a ball mill for 24 hours. To make.

【0023】次に真空脱泡して適度に粘度を調節する。
次にこのスラリーをドクターブレードを用いて、ポリエ
ステルフィルム上に0.5μmの厚さに塗布しその後乾燥
してグリーンシートを作製した。
Next, the viscosity is adjusted appropriately by vacuum degassing.
Next, this slurry was applied on a polyester film to a thickness of 0.5 μm using a doctor blade and then dried to produce a green sheet.

【0024】次にこのグリーンシートにポンチで直径1
60μmの穴を450μm間隔で明け、銅ペーストを印
刷充填し、さらに銅ペーストの印刷により表面層、電源
層、配線層を形成した。
Next, the green sheet is punched with a diameter of 1 mm.
Holes of 60 μm were drilled at 450 μm intervals, copper paste was printed and filled, and a surface layer, a power supply layer, and a wiring layer were formed by printing the copper paste.

【0025】銅ペーストは平均粒径3μmの還元銅粉1
00重量部にバインダとしてエチルセルロース10重量
部と溶剤90重量部を混合し作製したビヒクル10重量
部加えたものを、らいかい機で30分混合し、さらに3
本ロールを数回通して混練し適当な粘度に調節し、穴埋
め印刷及びスクリーン印刷した。
The copper paste is a reduced copper powder 1 having an average particle size of 3 μm.
10 parts by weight of ethyl cellulose as a binder and 90 parts by weight of a solvent were added to 00 parts by weight, and 10 parts by weight of a vehicle prepared was added thereto.
The roll was kneaded several times, kneaded and adjusted to an appropriate viscosity, and then filled and printed.

【0026】このようにして作製したグリーンシートの
うちコンデンサ搭載を行うグリーンシートと先に作成し
た電気特性の評価を終えた、コンデンサが搭載されたポ
リエステルフィルムを位置合わせしてから200℃で1
0kg/cm2で30分保持し熱圧着し、次いでポリエ
ステルフィルムを剥離しコンデンサをグリーンシートに
転写する。不良で除去されたコンデンサが存在する場合
は、同様にして作製したコンデンサを欠損部にさらに転
写する。
Of the green sheets thus prepared, the green sheet on which the capacitor is mounted and the polyester film on which the capacitor has been evaluated after the evaluation of the electrical characteristics have been completed are aligned at 200.degree.
After holding at 0 kg / cm 2 for 30 minutes and thermocompression bonding, the polyester film is peeled off and the capacitor is transferred to a green sheet. If there is a defective capacitor that has been removed, the capacitor manufactured in the same manner is further transferred to the defective portion.

【0027】このようにして作製したグリーンシートを
50枚位置合わせした後熱間プレスにより圧着した。圧
着は、温度130℃、圧力150kgf/cm2とし
た。
After aligning 50 sheets of the green sheets thus prepared, they were pressed by a hot press. The pressure bonding was performed at a temperature of 130 ° C. and a pressure of 150 kgf / cm 2.

【0028】圧着したグリーンシートは脱脂のため、1
00℃/h以下の昇温速度で昇温し、850℃で10時
間保持した。雰囲気はバインダカーボンの除去が可能
で、かつ銅が酸化しないN2+H2O+H2雰囲気で行
った。その後雰囲気をN2に切り替え1000℃で2h
保持し、焼結緻密化させた。焼結中は、基板の反りを抑
え、また基板のXY方向の収縮率を制御するために2k
gf/cm2で加圧した。
The pressed green sheet is degreased to obtain 1
The temperature was raised at a temperature rising rate of 00 ° C./h or less and maintained at 850 ° C. for 10 hours. The atmosphere was an N2 + H2O + H2 atmosphere in which binder carbon could be removed and copper was not oxidized. After that, the atmosphere was switched to N2 at 1000 ° C for 2 hours.
Hold and sinter densify. During sintering, 2k is used to control the warpage of the substrate and to control the shrinkage of the substrate in the X and Y directions.
Pressure was applied at gf / cm2.

【0029】このようにして作製したセラミック多層回
路基板の裏面導体パッドに置換金メッキ後AuSnはんだを
用い、CuZr製の電気信号入出力用ピンを1.6mm径の導
体パッドにろう付けし、次いで、LSIチップをはんだ
8により装着したところ、良好な動作特性を得る事がで
きた。このようにして製造したモジュールの概略図を図
2に示す。
After replacing the conductive pads on the back surface of the ceramic multilayer circuit board thus prepared with AuSn solder, the CuZr electrical signal input / output pins are brazed to the 1.6 mm diameter conductive pads, and then the LSI is mounted. When the chip was mounted with the solder 8, good operating characteristics could be obtained. FIG. 2 shows a schematic diagram of the module manufactured in this manner.

【0030】実施例2 厚さ200μmのポリエステルフィルム及び軟化温度2
00℃の熱可塑性のフィルム及び厚さ18μmの銅箔を
重ね、200℃で10kg/cm2で30分保持し熱圧
着する。
Example 2 Polyester film having a thickness of 200 μm and softening temperature 2
A thermoplastic film at 00 ° C. and a copper foil with a thickness of 18 μm are overlaid, held at 200 ° C. at 10 kg / cm 2 for 30 minutes, and thermocompression bonded.

【0031】次いでフォトエッチ処理を行いコンデンサ
電極パターンを形成する。次に該電極上にスパッタリン
グにより厚さ1μmのPZT組成の非晶質薄膜層を形成
する。次に同じく、スパッタリングにより非晶質薄膜層
上に、Cuの対極電極を形成する。次に形成したコンデ
ンサ側面に、同じくスパッタリングによりMgO側面雰
囲気シール層を形成する。
Next, a photo-etching process is performed to form a capacitor electrode pattern. Next, an amorphous thin film layer having a PZT composition having a thickness of 1 μm is formed on the electrode by sputtering. Next, similarly, a counter electrode of Cu is formed on the amorphous thin film layer by sputtering. Next, an MgO side atmosphere sealing layer is similarly formed on the side surface of the formed capacitor by sputtering.

【0032】次に該コンデンサをショート不良を評価し
た後、実施例1に示した条件でグリーンシートに転写、
積層、圧着、焼結を行った。初め低誘電率であったPZ
T組成の非晶質薄膜層は焼結プロセスの途中で結晶化
し、高誘電率のPZT結晶層となり、実施例1と同等の
コンデンサ特性が得られた。
Next, after the capacitor was evaluated for short-circuit failure, it was transferred to a green sheet under the conditions shown in Example 1.
Lamination, pressure bonding, and sintering were performed. PZ with low dielectric constant at the beginning
The amorphous thin film layer having the T composition crystallized during the sintering process, and became a PZT crystal layer having a high dielectric constant. Thus, capacitor characteristics equivalent to those of Example 1 were obtained.

【0033】[0033]

【発明の効果】多量の微細なコンデンサを高位置精度で
基板内に内蔵する事ができるとともに、誘電体の側面を
雰囲気シール層、上下面を緻密な電極金属で保護する事
で、焼結雰囲気との相互作用による誘電特性の劣化を防
ぐ事が出来る。
According to the present invention, a large amount of fine capacitors can be built in the substrate with high positional accuracy, and the side surfaces of the dielectric are protected by an atmosphere sealing layer, and the upper and lower surfaces are protected by dense electrode metals, thereby achieving a sintering atmosphere. The degradation of the dielectric characteristics due to the interaction with the substrate can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】コンデンサ形成プロセスの断面概要図である。FIG. 1 is a schematic sectional view of a capacitor forming process.

【図2】本発明の1実施例を示すガラスセラミック多層
回路基板の断面概要図である。
FIG. 2 is a schematic cross-sectional view of a glass ceramic multilayer circuit board showing one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…銅箔、2…誘電体層、3…対極電極、4…側面雰囲
気シール層、5…ポリエステルフィルム、6…熱可塑性
接着剤フィルム、7…グリーンシート、8…スルーホー
ル、9…はんだ、10…電源層、11…ガラスセラミッ
ク、12…接続パッド。
DESCRIPTION OF SYMBOLS 1 ... Copper foil, 2 ... dielectric layer, 3 ... counter electrode, 4 ... side atmosphere sealing layer, 5 ... polyester film, 6 ... thermoplastic adhesive film, 7 ... green sheet, 8 ... through hole, 9 ... solder, 10: power supply layer, 11: glass ceramic, 12: connection pad.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01G 4/30 301 H01G 4/30 311F 311 C23C 14/08 J // C23C 14/08 14/34 A 14/34 16/18 16/18 H01G 1/035 E (72)発明者 勝村 宣仁 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 田上 文一 神奈川県秦野市堀山下1番地 株式会社日 立製作所エンタープライズサーバー事業部 内 Fターム(参考) 4K029 AA02 AA04 AA25 BA43 BA46 BC05 CA05 DC05 4K030 AA11 BA42 BB12 CA02 HA03 LA02 5E001 AB03 AC09 AE00 AE03 AG00 AH03 AH05 AH09 AJ01 AJ02 AZ01 5E082 AB03 BC40 EE03 EE23 EE41 FG26 FG27 FG42 FG54 HH43 JJ15 JJ23 LL02 MM22 MM24 5E346 CC16 CC32 DD04 DD15 DD44 EE13 EE23 EE29 FF45 GG09 GG18 GG19 GG28 HH01 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference) H01G 4/30 301 H01G 4/30 311F 311 C23C 14/08 J // C23C 14/08 14/34 A14 / 34 16/18 16/18 H01G 1/035 E (72) Inventor Nobuhito Katsumura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.Hitachi, Ltd.Production Technology Research Laboratory, Hitachi, Ltd. (72) Inventor Bunichi Tagami Hatano, Kanagawa Prefecture No. 1 Ichihori Yamashita F-term (reference) 4K029 AA02 AA04 AA25 BA43 BA46 BC05 CA05 DC05 4K030 AA11 BA42 BB12 CA02 HA03 LA02 5E001 AB03 AC09 AE00 AE03 AG00 AH03 AH05 AH01 AJ01 AB02 BC40 EE03 EE23 EE41 FG26 FG27 FG42 FG54 HH43 JJ15 JJ23 LL02 MM22 MM24 5E346 CC16 CC32 DD04 DD15 DD44 EE13 EE23 EE29 FF45 GG09 GG18 GG19 GG28 HH01

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 フィルム上に保持した金属箔上に誘電体
層を形成し、その上に対極電極を形成し、側面を例えば
アルミナ(Al2O3)マグネシア(MgO)シリカ
(SiO2)等の高融点酸化物のシール材で封止し、グ
リーンシートに転写し、積層圧着し、焼結を行う事で製
造される事を特徴とするコンデンサ内蔵セラミック多層
基板。
1. A dielectric layer is formed on a metal foil held on a film, a counter electrode is formed on the dielectric layer, and a side surface of the dielectric layer is formed of a high melting point oxide such as alumina (Al2O3) magnesia (MgO) silica (SiO2). A ceramic multilayer substrate with a built-in capacitor, which is manufactured by sealing with a sealing material, transferring to a green sheet, laminating and pressing, and sintering.
【請求項2】 請求項1に記載のコンデンサ内蔵セラミ
ック多層基板の製造方法。
2. The method of manufacturing a ceramic multilayer substrate with a built-in capacitor according to claim 1.
【請求項3】 フィルム上に保持した金属箔上に誘電体
層を形成し、その上に対極電極を形成し、側面を例えば
アルミナ(Al2O3)マグネシア(MgO)シリカ
(SiO2)等の高融点酸化物のシール材で封止して製
造される事を特徴とするコンデンサ。
3. A dielectric layer is formed on a metal foil held on a film, a counter electrode is formed on the dielectric layer, and a side surface of the dielectric layer is formed of a high melting point oxide such as alumina (Al2O3) magnesia (MgO) silica (SiO2). A capacitor characterized by being manufactured by sealing with a sealing material.
【請求項4】 請求項3に記載のコンデンサの製造方
法。
4. A method for manufacturing a capacitor according to claim 3.
【請求項5】 請求項3に記載のコンデンサを転写した
グリーンシート。
5. A green sheet on which the capacitor according to claim 3 is transferred.
JP2000200063A 2000-06-28 2000-06-28 Capacitor-containing ceramic multilayer board and its manufacturing method Pending JP2002016364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000200063A JP2002016364A (en) 2000-06-28 2000-06-28 Capacitor-containing ceramic multilayer board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000200063A JP2002016364A (en) 2000-06-28 2000-06-28 Capacitor-containing ceramic multilayer board and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002016364A true JP2002016364A (en) 2002-01-18

Family

ID=18697982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000200063A Pending JP2002016364A (en) 2000-06-28 2000-06-28 Capacitor-containing ceramic multilayer board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002016364A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115551195A (en) * 2022-11-28 2022-12-30 四川斯艾普电子科技有限公司 SRD comb spectrum generator based on thick-film multilayer circuit and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115551195A (en) * 2022-11-28 2022-12-30 四川斯艾普电子科技有限公司 SRD comb spectrum generator based on thick-film multilayer circuit and preparation method thereof
CN115551195B (en) * 2022-11-28 2023-03-14 四川斯艾普电子科技有限公司 Thick-film multilayer circuit based SRD comb spectrum generator and preparation method thereof

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