JP2002014141A - Testing circuit for lsi provided with functional block, and testing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing circuit capable of testing functional blocks individually from the outside or a CPU, irrespective of the number of functional blocks included in an LSI and the number of terminals thereof. SOLUTION: Test data and test sequence required for test operation are set in a register, in an input signal region of the functional block to be tested from the outside of the LSI or the CPU. A test input signal is given to the functional block due to the setting into the register in the input signal region, and the functional block performs testing operations, so that a test output signal outputted from the functional block is set as output data in a register in an output signal region. The output data set in the register in the output signal region is read sequentially and is compared with an expected value to verify the operation of the functional block from the outside or from the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an LSI test circuit, and more particularly to an IP (Intellectual Property).
The present invention relates to an LSI test circuit having a function block as a test circuit.

[0002]

2. Description of the Related Art In a conventional LSI test circuit having a functional block as an IP, an input / output terminal of each functional block provided in the LSI is connected to an external pin of the LSI, and a multiplexer is used to input and output each functional block. In some cases, IP functions are verified by selecting an output signal.

However, if this method is used, if the number of external pins of the LSI is smaller than the number of input / output terminals of the functional blocks provided in the LSI, there is a problem that a test of each functional block cannot be performed. . In addition, when the number of function blocks incorporated in one chip LSI is large, there is a problem that it is difficult to select input / output signals of the function block by a multiplexer and test the signals from external pins.

There is also a method in which a boundary scan design is applied to each functional block to facilitate the test, and a test of each functional block alone is performed. However, according to this method, the time required for the test becomes longer. But not
It has not been possible to verify the function of the functional block by providing a sequence for the test data of the functional block from the CPU, setting the test data, and comparing the test result with an expected value.

[0005]

As described above, in a conventional LSI test circuit having a functional block as an IP, the number of terminals of each functional block built in the LSI is L.
If the number of external pins exceeds the number of external pins of the SI, it is impossible to test each functional block alone. If the number of functional blocks built in the LSI is large, select a multiplexer to test from the external pins of the LSI. There was a problem that it became difficult.

The present invention has been made to solve the above problems, and a sequence is provided from outside the LSI or from the CPU irrespective of the number of function blocks as IP built in the LSI and the number of terminals of the function blocks. It is an object of the present invention to provide an LSI test circuit provided with a functional block capable of setting test data by using the LSI.

[0007]

According to the present invention, an LSI test circuit having a function block as an IP includes an input section and an output section of the function block to be tested. A register for temporarily storing test output data is provided. CP from outside of LSI or embedded in LSI
U. The function block is tested by using the test data written from the memory to the register of the input unit, the test result is temporarily stored in the register of the output unit, and the result is compared with an expected value. The function of the block can be verified.

More specifically, an LSI test circuit having a functional block according to the present invention includes a first register connected to an input section of the functional block, and a second register connected to an output section of the functional block. Wherein the first and second registers are each accessible from an external bus, and the first register temporarily stores test data of the functional block input from the outside, A function of inputting the test data to the function block in accordance with a given sequence given from the outside; the second register temporarily stores a test result of the function block based on the test data output from the function block; Verification of the operating state of the functional block by comparing the test result temporarily stored in the second register with an expected value. And wherein the Rukoto.

An LS having a functional block according to the present invention is also provided.
The I test circuit includes a CPU and a memory for storing input / output data of the CPU, a functional block controlled by the CPU, a first register connected to an input unit of the functional block, A second register connected to an output unit, wherein the first and second registers are accessible from the CPU, and the first register is a fixed register from the memory by the CPU. A function of temporarily storing test data of the functional block read in accordance with a sequence, and then inputting the test data to the functional block, wherein the second register stores the test data output from the functional block And temporarily stores the test result temporarily stored in the second register using the CPU. It characterized by verification of the operating state of the function block by comparing the expected value stored in the memory Te.

Preferably, the test circuit of the LSI records the test data for testing the functional block, a sequence of the test data, and an expected value of the test result as program information on the memory, so that the CPU can It is characterized in that it is possible to activate a test circuit of an LSI, read out program information in the memory, and automatically perform a test of the functional block to be tested.

Preferably, in the LSI test circuit, a test result of the functional block temporarily stored in the second register is held in the second register during a normal operation period of the LSI, and The test result of the functional block can be verified during the normal operation period and after the normal operation period.

According to a method of testing an LSI having a functional block according to the present invention, a first register connected to an input section of a functional block and a second register connected to an output section of the functional block are connected via a bus line. Accessing the test block; temporarily storing test data of the functional block in the first register; reading the test data temporarily stored in the first register in accordance with a test sequence of the functional block; Inputting to the functional block, temporarily storing the test result of the functional block output from the functional block in the second register, and storing the test result temporarily stored in the second register in the functional block. And comparing the test result with an expected value of the test result.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram illustrating a configuration of an LSI including a plurality of functional blocks as a CPU and an IP according to an embodiment of the present invention. Here, IP is
This is the intellectual property of functional blocks with specific functions built into the LSI, and all materials related to the design, manufacture and testing of functional blocks that require a long development time when developing LSI and its derivatives are intellectual assets. It has been taken over and reused in the development of new products.

In particular, the intellectual assets of a functional block as an IP in this specification include test data and a test sequence for verifying the function of the functional block, and expected values of the test result. When the functional block test apparatus and the test method of the present invention described in the embodiments are used, when an IP functional block is reused in the development of an LSI and its derivatives, effective use of known intellectual assets inherited with respect to the test can be effectively performed. Utilization can contribute to reduction of development costs.

FIG. 1A shows a state where a CPU is connected via a data bus.
FIG. 2 is a diagram showing a configuration part of the present invention composed of a plurality of IPs such as IP1, IP2, IP3, etc. Where IP
1, IP2, IP3, etc. are each a functional block as IP. FIG. 1B shows a register area of the IP1 accessed in the normal operation, and an input signal area and an output signal area used in the test of the IP1.
Is shown as a partially enlarged view of FIG. In addition, IP2, IP
3 and the like are similarly configured.

FIG. 1C shows a first register including a flip-flop FF1 in the input signal area, a second register including a flip-flop FF2 in the output signal area, a multiplexer MUX, and a main body of IP1. Each is shown.

In the test operation of IP1, test data is input from input terminal 1 in a fixed sequence, and a test result of IP1 is output from output terminal 2.
The input terminal 3 and the output terminal 4 are input / output terminals in the normal operation of the IP1, and the multiplexer MUX switches between the test operation and the normal operation of the IP1.

As described above, in the LSI test circuit and test method including the functional blocks according to the present invention, each functional block as an IP includes a register area of the IP accessed during normal operation of the LSI and a test of each functional block. A test area to be accessed during operation; the test area includes an input signal area and an output signal area; a first register including FF1 in the input signal area; and FF2 in an output signal area. And a second register comprising:

In the test operation of the LSI, for example, a test data is set from outside the LSI in a sequence so that the IP1 operates in the first register FF1 in the input signal area of the IP1 to be tested.

A first external signal from the LSI via the input terminal 1
The test data set in the register FF1 causes the IP1 to perform a test operation in a fixed sequence, and the second register FF
2, the test result is set as output data.

The output data set in the second register is read from the outside via the output terminal 2 and is compared with an expected value to verify the function of IP1. By repeating the same test operation for IP2, IP3, and the like, it is possible to verify the functions of all the function blocks as IP built in the system LSI.

In this way, the test input signal of the functional block built in the LSI can be set in the input signal area, and the state of the output signal in the test operation of the functional block is verified by examining the output signal area. Therefore, the target functional block can be tested regardless of the number of pins of the LSI chip or the number of terminals of the functional block.

In the above embodiment, the case where the test data and the test sequence are provided from outside the LSI has been described. However, the test of the functional blocks incorporated in the LSI is not necessarily performed by the outside of the LSI.

Next, as a modification of the above embodiment, L
A case where a test of a functional block built in an LSI is internally performed using a CPU and a memory constituting the SI will be described.

In the test operation of the LSI shown in FIG.
First register FF1 of IP1 to be tested by CPU
Then, test data is set in a sequence so that IP1 operates. At this time, the test data and the test sequence may be those previously written as program information in a memory area (not shown) of the LSI.

The test data set in the first register FF1 by the CPU activates the main body of IP1, and its output signal is set in the second register FF2 of IP1 as output data indicating the test result.

The CPU verifies the operation of IP1 by reading out the output data set in the two registers and comparing it with the expected value written in the memory area. By repeating the same test operation for IP2, IP3, and the like, it is possible to verify the functions of all the function blocks as IP built in the LSI.

As described above, if the test data, the test sequence, and the expected value of the test result are programmed in the memory area in advance, the CPU starts the test,
The test of the function block as the IP can be automatically performed while fully utilizing the test information inherited as the IP.

Further, the second signal FF2 in the output signal area
The register stores the output signal data of the functional block, and holds the output signal data during and after the normal operation period of the LSI. Therefore, even after the functional block is actually incorporated in the LSI, By checking the output signal area, the operation state of each functional block can be confirmed again.

The present invention is not limited to the above embodiment. In the embodiments described above, the test circuit and the test method for verifying the operation of the functional block in the LSI having the functional block as the IP have been described. However, the functional block to be tested is not necessarily the IP. No need to be. The same can be applied to general functional blocks built in a normal LSI. In addition, various modifications can be made without departing from the scope of the present invention.

[0031]

As described above, according to the test circuit of the system LSI incorporating the function block as the IP of the present invention, the following effects can be obtained.

(1) The test data for operating the functional block, the test sequence, and the expected value of the test result are programmed in the memory, so that the CPU activates the test circuit and automatically tests the target functional block. Since it can be executed, intellectual assets related to the test of the functional block inherited as IP can be easily utilized.

(2) The input signals of the functional blocks can be set by using the input signal areas included in each functional block, and the state of the output signals can be confirmed by using the output signal areas. Therefore, the target functional block can be tested regardless of the number of pins of the chip.

(3) Since the output signal data of the functional block is stored in the output signal area, the output signal area is checked by checking the output signal area even after the functional block is actually incorporated in the LSI. Since the operation state can be reconfirmed, particularly when the LSI does not operate as specified, it is easy to identify a defect by checking the output signal area of each functional block.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a system LSI incorporating a CPU and a plurality of function blocks according to an embodiment of the present invention, wherein (a) shows a plurality of function blocks connected to the CPU via a data bus; The figure which shows the component part of this invention which consists of. FIG. 3B is a diagram illustrating a configuration of a register area of IP1 accessed during a normal operation of the system LSI, and an input signal area and an output signal area used during a test operation. (C)
FIG. 3 is a diagram showing connections between the input / output signal area, registers FF1 and FF2, a multiplexer MUX, and a main body of IP1.

[Explanation of symbols]

 1: Input terminal during test operation 2: Output terminal during test operation 3: Input terminal during normal operation 4: Output terminal during normal operation

Claims (5)

[Claims] A first block connected to an input section of the functional block;
And a second register connected to an output unit of the functional block, wherein the first and second registers are each accessible from an external bus, and the first register is Having a function of temporarily storing test data of the functional block input from the outside, and then inputting the test data to the functional block according to a fixed sequence given from the outside; A test result of the functional block based on the test data output from the functional block is temporarily stored, and the operation result of the functional block is verified by comparing the test result temporarily stored in the second register with an expected value. An LSI test circuit comprising a functional block. 2. A CPU and a memory for storing input / output data of the CPU, a function block controlled by the CPU, a first register connected to an input section of the function block, and an output of the function block And a second register connected to the unit, wherein the first and second registers are accessible from the CPU, and the first register is a fixed sequence from the memory by the CPU. Has a function of temporarily storing test data of the functional block read in accordance with the above, and then inputting the test data to the functional block. The test result of the functional block is temporarily stored, and the test result temporarily stored in the second register is used by the CPU. A test circuit for verifying an operation state of the function block by comparing the operation state of the function block with an expected value stored in the memory. 3. The test circuit of the LSI records test data for testing the functional block, a sequence of test data, and an expected value of the test result as program information on the memory, so that the CPU can 3. The method according to claim 2, wherein a test circuit of an LSI is started to read out program information on the memory, and a test of the functional block to be tested is automatically performed.
An LSI test circuit comprising the functional blocks described above. 4. In the LSI test circuit, a test result of the functional block temporarily stored in the second register is held in the second register during a normal operation period of the LSI, and a normal operation of the LSI is performed. 4. The LSI test circuit according to claim 1, wherein a test result of the functional block can be verified during a period and after a normal operation period. 5. A first circuit connected to an input of a functional block.
Accessing a second register connected to an output unit of the functional block and a register of the functional block via a bus line; temporarily storing test data of the functional block in the first register; Reading the test data temporarily stored in the first register and inputting the test data to the functional block according to the test sequence of the following; and storing the test result of the functional block output from the functional block in the second register. Temporarily storing the test result, and comparing the test result temporarily stored in the second register with an expected value of the test result of the functional block. .