JP2002010220A - Scan line converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan line converting device which can reduce flicker visually without deterioration of resolution. SOLUTION: A scan line converting device provides a converting means, a limiting means and a generating means. The converting means converts a non-interlaced scan signal composed of R, G and B signals into a luminance signal and a chrominance difference signal. The limiting means limits amplitudes of a high frequency component in the vertical direction and a low frequency component in the horizontal direction. The generating means thins out predetermined lines of the luminance signal and the chrominance difference signals whose amplitudes of the high frequency component in the vertical direction and the low frequency component in the horizontal direction are limited and generates an interlaced scan signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts a non-interlaced image output from a personal computer (hereinafter, referred to as a personal computer) into an interlaced image, and converts the image into a television (hereinafter, referred to as a television or a TV). The present invention relates to a scanning line conversion device for displaying on a display device.

[0002]

2. Description of the Related Art In recent years, demand for personal computers has been growing rapidly in various countries around the world. However, many of the personal computers that are now in widespread use are purchased by businesses or individuals for business use. Therefore, in the future, the spread to homes will be the biggest issue. In order to spread the personal computer in the home, it is desired to develop a product that can be used by family members, in addition to simplifying the operation and reducing the price. Recently, many personal computer manufacturers have released integrated personal computers that take operability into account. These product groups are configured so that a user does not need to connect devices by integrating a personal computer main body, a display, a hard disk, a floppy (registered trademark) disk, a CD-ROM, and the like. In addition, each company is trying to improve the operability of personal computers by devising the initial installation software (software such as menu display and operation explanation).

[0003] However, the integrated personal computers of each company are aimed at individuals, not at home (family). The above-mentioned integrated personal computer is operated in the same manner as a conventional personal computer by a user operating a keyboard or a mouse in front of a display of about 15 inches in a CD-RO.
M or a game. On the other hand, in product development targeting the home (family), it is necessary to display a personal computer screen on a large display in order for the whole family to view fine images or sounds of the personal computer. For operation, instead of using a conventional keyboard and mouse, a personal computer can be operated from a remote place using a wireless remote controller or the like used for home appliances such as audio visual equipment (hereinafter, referred to as AV equipment). I need to be able to do it.

[0004] The development of a display monitor for home use has the following problems. Generally, when a display for a personal computer is used as a display device, the price of the display is about four times that of a television of the same size. This price difference (price) poses a serious problem in disseminating personal computers for home use. On the other hand, there is a method of displaying the output (display image) of a personal computer on a conventional home television screen. At this time, while the display screen of the personal computer is sequentially scanned (hereinafter referred to as non-interlaced scanning), the display on the television is interlaced scanning, so that the image data transmitted by non-interlaced scanning (hereinafter referred to as non-interlaced scanning) is used. It is necessary to convert a non-interlaced image into an interlaced scan image (hereinafter, referred to as an interlaced image). In that case,
Flickers occur on the TV screen, resulting in very unsightly images. Hereinafter, a screen display method of a personal computer and a television, a cause of flicker generation, and a conventional scanning line conversion device including a flicker removal circuit will be described.

First, a screen display method (screen display mode) of a personal computer will be briefly described. There are a plurality of screen display modes of the personal computer. Among them, a frequently used VGA standard will be briefly described. In the VGA standard, the number of effective images per line is 64
The number of effective scanning lines in one frame is defined as 480 lines with 0 pixels. The image is displayed on the display in a non-interlaced manner. Note that there is no clear definition regarding the frame frequency. (It is often output at a frame frequency of about 60 Hz.) Next, a screen display method (screen display mode) of the television will be described. ITU-R Recommendation BT. 601 (system 5
According to 25), the number of effective pixels in the horizontal direction of the TV screen is 7
20 pixels (at the time of 13.5 MHz sampling), the number of effective scanning lines in one frame is 486 lines. Also,
The television is displayed on the display as an interlaced image having a field frequency of 59.94 Hz. Therefore, when the VGA output from the personal computer is simply converted into an interlaced image and displayed on a television screen, flicker occurs and the image becomes very unsightly.

Next, a process of generating flicker which occurs when a non-interlaced image is converted to an interlaced image will be briefly described with reference to FIGS.
FIG. 15 is a diagram showing the spatial frequency characteristics of a non-interlaced image. In other words, the characteristics on the spatial frequency of the non-interlaced image in the case of 525 scanning lines and a frame frequency of 60 Hz (hereinafter, referred to as a frequency spectrum). Is shown. In the figure, the horizontal axis represents the spatial frequency in the time axis direction, and the vertical axis represents the spatial frequency in the vertical direction. In the case of a non-interlaced image, a frequency spectrum appears repeatedly at intervals of 60 Hz in the time axis direction and at intervals of 525 lines in the vertical direction. (See Fig. 15)

FIG. 16 is a diagram showing the spatial frequency characteristics of an interlaced image. In other words, the spatial frequency when the non-interlaced image having the frequency spectrum shown in FIG. 15 is converted into an interlaced image having a field frequency of 60 Hz and 525 scanning lines. The upper characteristic (frequency spectrum) is shown. In the figure, the horizontal axis represents the spatial frequency in the time axis direction, and the vertical axis represents the spatial frequency in the vertical direction.
Flicker that occurs when a non-interlaced image is converted to an interlaced image occurs because a high-frequency component in the vertical direction returns to a low-frequency component in the vertical direction when viewed from the time axis direction. The hatched portion in the figure corresponds to a folded portion (flicker component) of the high frequency component in the vertical direction when viewed from the time axis direction.

FIG. 17 is a diagram showing characteristics (frequency spectrum) on the two-dimensional frequency of the interlaced image shown in FIG. In the figure, the horizontal axis is the horizontal spatial frequency,
The vertical axis indicates the spatial frequency in the vertical direction. In the figure, the hatched portion is the above-described vertical aliasing component (flicker component) on a two-dimensional frequency. Therefore, flicker can be eliminated by suppressing the high frequency component in the vertical direction.

FIG. 18 is a block diagram of a conventional scanning line converter. In this conventional example, a case where a VGA signal based on the VGA standard is converted into an NTSC signal will be described. In the figure, reference numerals 1a to 1c denote input terminals for VGA signals (R, G, B signals based on the VGA standard), 2 denotes input terminals for VGA signal synchronization signals, and 3a to 3c denote input analog video signals as digital video signals. A / D conversion circuit (hereinafter referred to as an A / D conversion circuit or A / D) 4 is a VG input from an input terminal 2
A first synchronization detection circuit for detecting a vertical synchronization signal and a horizontal synchronization signal from the synchronization signal of the A signal, and a first synchronization detection circuit for generating a clock based on a synchronization signal output from the first synchronization detection circuit. PLL circuits 6a to 6c extract a first low frequency component of the input digital video signal in a vertical direction.
And a vertical memory low-pass filter (hereinafter referred to as a first VLPF) 7a to 7c are frame memories for storing digital video signals output from the first VLPFs 6a to 6c.

Reference numeral 8 denotes a line memory for the line memories 23a to 23b in the first VLPFs 6a to 6c (the structure of the first VLPF 6 is shown in FIG. 19 but will be described later in detail) and to the frame memories 7a to 7c. A first memory control circuit 9a to 9c for generating a digital video signal write / read control signal is provided with a digital / analog conversion circuit (hereinafter, referred to as a digital / analog conversion circuit) for converting a digital video signal output from the frame memories 7a to 7c into an analog video signal. D / A conversion circuit or D / A.) 10 denotes the input R, G and B signals as a luminance signal (hereinafter referred to as Y signal) and two color difference signals (hereinafter referred to as RY). Matrix circuit for converting the signal into a signal and a BY signal.)
Reference numeral 11 denotes a second PLL circuit that generates a clock based on a synchronization signal output from the second synchronization detection circuit 12;
Reference numeral 2 denotes a second synchronization detection circuit that detects a vertical synchronization signal, a horizontal synchronization signal, and the like from a TV-side synchronization signal input from the input terminal 16.

Reference numeral 13 denotes a synchronization adding circuit for adding a vertical synchronizing signal and a horizontal synchronizing signal to the Y signal output from the matrix circuit 10, and 14 denotes two color difference signals (RY signals, RY signals, And BY signal)
Are converted into a modulated color signal (hereinafter, referred to as a C signal), 15a and 15b are output terminals for a Y signal and a C signal, and 16 is an input terminal for a synchronization signal on the TV side.

FIG. 19 is a block diagram of the first VLPF 6 of the related art. In the figure, reference numeral 20 denotes an input terminal of a digital video signal, 21 denotes an input terminal of a memory control signal output from the first memory control circuit 8, 22 denotes output terminals of digital video signals, and 23a and 23b denote input digital signals. A line memory for delaying a video signal by one line,
24a and 24b are multiplication circuits for multiplying the input digital video signal by 0.25, 25 is a multiplication circuit for multiplying the input digital video signal by 0.5, and 26 is an addition circuit. FIG. 20 is a diagram illustrating a frequency characteristic of the first VLPF 6. In the figure, the horizontal axis represents the spatial frequency in the vertical direction, and the vertical axis represents the amplitude characteristics.

The operation of the conventional scanning line converter will be described below with reference to FIGS. In this conventional example, VG
A case in which a non-interlaced image input based on the A standard is converted into an interlaced image and output will be described. The R, G, and B signals input via the input terminals 1a to 1c are converted into digital signals by A / D conversion circuits 3a to 3c. On the other hand, the synchronization signal of the VGA signal input via the input terminal 2 is separated into a vertical synchronization signal and a horizontal synchronization signal by the first synchronization detection circuit 4. The horizontal synchronization signal separated by the first synchronization detection circuit 4 is input to the first PLL circuit 5. The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronization signal. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the first memory control circuit 8. Note that the vertical synchronization signal and the horizontal synchronization signal detected by the first synchronization detection circuit 4 are also input to the first memory control circuit 8.

The first memory control circuit 8 uses the horizontal synchronization signal of the VGA signal output from the first synchronization detection circuit 4 to use the line memories 23a and 23a in the first VLPF 6
3b to generate a digital video signal write control signal and a read control signal. For example, when a FIFO (first-in first-out) memory is used for the line memories 23a and 23b, the first memory control circuit 8 outputs a line address reset signal at the time of writing and reading, a write and read enable signal (ENABL signal). ), And write and read clock signals are output. The first memory control circuit 8 uses the vertical synchronizing signal and the horizontal synchronizing signal output from the first synchronizing
7c are also generated. The specific control method of the frame memories 7a to 7c will be described later. In the conventional example, the FIFO memory is used as the line memories 23a and 23b in the first VLPF 6.

The R, G, and B signals converted to digital signals by the A / D conversion circuits 3a to 3c are converted into first VLPFs.
6a to 6c. Hereinafter, the operation of the first VLPF 6 will be described with reference to FIG. The digital video signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input digital video signal by one line and outputs it. The digital video signal output from the line memory 23a is input to the multiplication circuit 25 and the line memory 23b. In the line memory 23b, the line memory 23a
And outputs the input digital video signal with one line delay. The output of the line memory 23b is a multiplication circuit 2
4b.

The digital video signals input to the multiplication circuits 24a and 24b are multiplied by 0.25 and output.
(Specifically, the data is shifted by 2 bits and output.) Further, the digital video signal input to the multiplication circuit 25 is multiplied by 0.5 and output. (Specifically, data is shifted by one bit and output.) Multiplication circuit 24
a and 24b and the output of the multiplying circuit 25 are added by an adding circuit 26 to remove high-frequency components in the vertical direction and output to the frame memory 7 via the output terminal 22. FIG. 20 shows the frequency characteristics of the first VLPF 6. The line memories 23a and 23b write and read the digital video signal into the memory based on the data write control signal and the data read control signal output from the first memory control circuit 8 via the input terminal 21. Performs read control.

The digital video signals from which high-frequency components in the vertical direction have been removed by the first VLPFs 6a to 6c are input to frame memories 7a to 7c. Hereinafter, the operation of writing the digital video signal into the frame memory 7 will be described. The first memory control circuit 8 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal having a field frequency of 60 Hz. Specifically, the frame memory 7
A digital video signal input in a frame structure is converted into a field structure and written when writing to the device.

Hereinafter, a method of generating a data write control signal to the frame memory 7 output from the first memory control circuit 8 will be described. First, when a vertical synchronization signal is input from the first synchronization detection circuit 4, the first memory control circuit 8 sets a field of a digital video signal to be written to the frame memory 7 next. If the field setting result is the first field, a control signal for writing only odd lines to the frame memory 7 is generated. If the field setting result is the second field, a control signal for writing only even lines to the frame memory 7 is generated. appear. The above control is performed by using the horizontal synchronization signal output from the first synchronization detection circuit 4 to determine the even / odd lines. At this time, in this conventional example, control is performed such that only the effective video signal portion of the VGA signal is written into the frame memory 7.

The non-interlaced digital video signals input to the frame memories 7a to 7c are field-structured digital video signals (interlaced digital video signals) based on the write control signal output from the first memory control circuit 8. And stored in the frame memories 7a to 7c. In this conventional example, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field. Therefore, when writing the non-interlaced digital video signal into the frame memory 7, the field memory used alternately is switched for each field. At that time, a switching control signal for the field memory is also output from the first memory control circuit 8 based on the field determination result.

On the other hand, T input through the input terminal 16
From the V-side synchronization signal, a vertical synchronization signal and a horizontal synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. In the second PLL circuit 11, the second synchronization detection circuit 1
A reference clock on the television side is generated based on the horizontal synchronization signal detected in step 2. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the first memory control circuit 8. Note that the vertical synchronization signal, the horizontal synchronization signal, and the field determination result detected by the second synchronization detection circuit 12 are also input to the first memory control circuit 8.

In the first memory control circuit 8, a read control signal for reading an interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the field discrimination result on the television side. (A switching signal for the field memory, a data read address, a read control signal, etc.). In the frame memories 7a to 7c, the first memory control circuit 8
A digital video signal having an interlaced structure is read from the memory based on the read control signal output from the memory.

The interlaced digital video signals read from the frame memories 7a to 7c are input to D / A conversion circuits 9a to 9c. D / A conversion circuits 9a to
In step 9c, the input interlaced digital video signal is converted into an interlaced analog video signal. R output from the D / A conversion circuits 9a to 9c,
The G and B signals are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10.
Is converted to The Y signal output from the matrix circuit 10 is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronizing circuit 13. Note that the synchronization adding circuit 13 is a second synchronization detecting circuit 12.
A synchronization signal is generated based on the vertical synchronization signal, the horizontal synchronization signal, and the result of the field discrimination, and added to the Y signal.

The two color difference signals (RY signal and BY signal) are converted into a modulated color signal (C signal) by the chroma encoder circuit 14 and output via an output terminal 15b. At the time of chroma encoding (when two color difference signals are converted into modulated color signals), two chroma signals are output from the second sync detection circuit 12 based on the vertical sync signal, the horizontal sync signal, and the field determination result. Modulates the color difference signal. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

[0024]

Since the conventional scanning line conversion apparatus is configured as described above, flicker generated when converting a non-interlaced image to an interlaced image can be removed, but the frequency band in the vertical direction is reduced. Due to the limitation, the resolution in the vertical direction deteriorates. That is, the flicker component removed by the conventional scanning line conversion device includes a high frequency component in the vertical direction, and simply limiting the vertical band lowers the vertical resolution, and in particular, the fine resolution on the display Problems such as the inability to read characters and the like arise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a scanning line conversion device capable of visually reducing flicker and suppressing a decrease in vertical resolution. And

[0026]

According to a first aspect of the present invention, there is provided a scanning line conversion apparatus for converting a non-interlaced signal composed of R, G, and B signals into a luminance signal and a color difference signal. Means for limiting the amplitude of the vertical high-horizontal low-frequency component of the luminance signal to a predetermined amplitude or less; and Means for generating an interlace signal by thinning out lines.

Further, in the scanning line conversion apparatus according to claim 1, means for detecting an amplitude of a horizontal high-frequency component of the luminance signal, and a vertical high-frequency component when the amplitude of the horizontal high-frequency component is smaller than a predetermined amplitude. Means for limiting the amplitude of the horizontal low-frequency component to be equal to or less than the first amplitude, and when the amplitude of the horizontal high-frequency component exceeds the predetermined value, the amplitude of the vertical high-frequency component is reduced to Means for restricting the amplitude to a value equal to or less than a second amplitude smaller than the first amplitude.

The scanning line conversion apparatus according to claim 1, further comprising means for detecting a DC component in a horizontal direction of the luminance signal, wherein when the DC component is detected, a vertical high-frequency component of the luminance signal is detected. The amplitude of the horizontal low-frequency component is set to 0.

The scanning line converter according to claim 1, further comprising means for reducing the amplitude of the vertical high-frequency component of the luminance signal, wherein the amplitude of the vertical high-frequency component is reduced. An interlace signal is generated based on the reduced luminance signal.

Further, in the scanning line converter according to claim 1, the signal band of the color difference signal is limited to less than half of the signal band of the luminance signal, and the color difference signal having the restricted signal band is reduced to half of the luminance signal. The apparatus further includes means for sampling at the following clock frequency, and generates an interlace signal based on the sampled color difference signal.

Further, the scanning line conversion device according to claim 6, further comprising means for converting a non-interlace signal comprising R, G, and B signals into a luminance signal and a color difference signal, and a horizontal high-frequency component of the luminance signal. Means for outputting a horizontal low-frequency component of the luminance signal by subtracting the horizontal high-frequency component from the luminance signal, and limiting an amplitude of a vertical high-frequency component included in the horizontal high-frequency component. A first band limiting means for limiting the amplitude of a vertical high frequency component included in the horizontal low frequency component so as to be smaller than the amplitude of a vertical high frequency component included in the horizontal high frequency component. Limiting means, and means for generating an interlaced signal by thinning out predetermined lines of the luminance signal and the color difference signal whose vertical high frequency component amplitude is limited by the first and second band limiting means. It is those with a.

In the scanning line converter according to claim 6, the signal band of the color difference signal is limited to less than half of the signal band of the luminance signal, and the color difference signal having the restricted signal band is reduced to half of the luminance signal. The apparatus further includes means for sampling at the following clock frequency, and generates an interlace signal based on the sampled color difference signal.

Further, the scanning line converter according to the present invention further comprises means for converting a non-interlaced signal consisting of R, G, and B signals into a luminance signal and a color difference signal, and a vertical high frequency component of the luminance signal. And means for generating an interlaced signal by thinning out predetermined lines of the luminance signal and the color difference signal whose amplitude of the vertical high-frequency component is limited.

Further, in the scanning line conversion device according to the present invention, only the vertical high frequency component exceeding a predetermined amplitude value is removed.

In the scanning line converter according to claim 1, the signal band of the color difference signal is limited to less than half of the signal band of the luminance signal, and the color difference signal having the restricted signal band is reduced to half of the luminance signal. The apparatus further includes means for sampling at the following clock frequency, and generates an interlace signal based on the sampled color difference signal.

[0036]

The scanning line converter according to the first aspect generates an interlace signal based on a luminance signal in which the amplitude of the vertical high-frequency component is limited.

The scanning line conversion device according to the second aspect is arranged such that when the amplitude of the horizontal high frequency component is lower than a predetermined amplitude, the vertical high frequency component
The amplitude of the horizontal low-frequency component is limited to be equal to or less than the first amplitude, and if it is larger, the amplitude is limited to be equal to or less than a second amplitude smaller than the first amplitude.

According to the scanning line converter of the third aspect, when the horizontal DC component of the luminance signal is detected, the amplitude of the vertical high band-horizontal low band component of the luminance signal is set to 0.

According to the scanning line converter of the fourth aspect, the interlace signal is generated based on the luminance signal in which the amplitude of the vertical high band-horizontal high band component and the vertical high band-horizontal low band component is reduced.

According to the scanning line converter of the fifth aspect, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half the luminance signal.

According to the scanning line converter of the sixth aspect, the amplitude of the vertical high frequency component included in the horizontal low frequency component is limited to be smaller than the amplitude of the vertical high frequency component included in the horizontal high frequency component. I do.

According to the scanning line converter of the present invention, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half of a luminance signal.

According to the scanning line converter of the eighth aspect, an interlace signal is generated based on the luminance signal in which the amplitude of the vertical high frequency component is limited.

According to the ninth aspect, only the vertical high-frequency component exceeding a predetermined amplitude value is removed.

According to the scanning line converter of the tenth aspect, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half the luminance signal.

[0046]

[Embodiment 1] FIG. 1 is a block diagram of a scanning line conversion apparatus according to the first embodiment of the present invention. In the first embodiment as well, a case will be described in which a VGA signal based on the VGA standard is converted into an NTSC signal (interlace signal) as in the conventional example. In the figure, 1a to 1c are VGA
Input terminals for signals (R, G, B signals based on VGA standard), 2 for VGA signal synchronization signal input terminals, 3a to 3c
Is a luminance signal (Y signal) in the matrix circuit 10, and 2
An A / D conversion circuit for converting an analog video signal converted into two color difference signals into a digital video signal;
A first synchronization detection circuit for detecting a vertical synchronization signal and a horizontal synchronization signal from a synchronization signal of a VGA signal input from the
Are first PLL circuits for generating a clock based on a synchronization signal output from the first synchronization detection circuit 4, 7a to 7
c is the luminance signal (Y
Signal) and two color difference signals (RY signal and BY signal) output from the A / D conversion circuits 3b and 3c.

Reference numerals 9a to 9c denote D / A conversion circuits for converting digital video signals output from the frame memories 7a to 7c into analog video signals, and 10 denotes input R, G, B.
A matrix circuit 11 converts the signal into a Y signal and two color difference signals (RY signal and BY signal). Reference numeral 11 denotes a TV-side synchronization signal output from a second synchronization detection circuit 12 as a reference. A second PLL circuit for generating a clock, 1
Reference numeral 2 denotes a second synchronization detection circuit that detects a vertical synchronization signal, a horizontal synchronization signal, and the like from a TV-side synchronization signal input from the input terminal 16.

13 is a synchronizing circuit for adding a vertical synchronizing signal and a horizontal synchronizing signal to the Y signal output from the D / A conversion circuit 9a, and 14 is two color difference signals output from the D / A conversion circuits 9b and 9c. (RY signal and BY signal
Signal) to a modulated color signal (C signal), 15a and 15b are output terminals for a Y signal and a C signal, respectively, and 16 is an input terminal for a synchronizing signal on the TV side.

Reference numerals 30a and 30b denote band-limiting filters (hereinafter, referred to as LPFs) for limiting the horizontal signal band of the RY signal and the BY signal output from the matrix circuit 10, and 31 is input. A flicker elimination circuit 32 for eliminating a flicker component in the Y signal includes line memories 23a and 23b in the flicker elimination circuit 31;
43 (the configuration of the flicker removal circuit 31 is shown in FIG. 2 but will be described later in detail), and the frame memory 7
and a second memory control circuit for outputting a digital video signal write / read control signal to / from a to 7c.
Note that the first VLPF 6 in the flicker removal circuit 31 is
As in the conventional example, it is assumed that the configuration is as shown in FIG.

FIG. 2 shows a flicker removing circuit 31 in FIG.
FIG. 3 is a block diagram of the configuration of FIG. In the figure, reference numeral 6 denotes a first VLPF for extracting a low-frequency component of a digital video signal (Y signal) in the vertical direction; 40, an input terminal of the Y signal; 41, a memory control output from the second memory control circuit 32; Signal input terminal, 42 is a Y signal output terminal, 43 is the input Y
A line memory 44 for delaying the signal by one line, and a subtraction circuit 44 for subtracting the vertical low frequency component output from the first VLPF 6 from the Y signal delayed by one line output from the line memory 43, are provided. By subtracting the output of the first VLPF 6 from the output of the line memory 43, the vertical high frequency component of the input Y signal is separated. Reference numeral 45 denotes a first horizontal high-pass filter (hereinafter, referred to as a first HHPF) that separates a horizontal high-frequency component from a vertical high-frequency component output from the subtraction circuit 44. The register 47 is an addition circuit.

FIG. 3 is a block diagram of the first HHPF 45 in FIG. In the figure, reference numeral 50 denotes an input terminal of a digital video signal (a vertical high-frequency component of a Y signal);
51 is an output terminal, 52a and 52b are registers for delaying the input high-frequency component of the Y signal in the vertical direction by one clock, and 53a and 53b are -0. Multiplication circuit for multiplying 25, 5
4 is 0 in the vertical high-frequency component of the input Y signal.
A multiplication circuit for multiplying 5 and 55 is an addition circuit. FIG. 4 is a diagram for explaining the basic concept of the flicker removal circuit 31 according to the first embodiment of the present invention. FIG.
2 shows a characteristic (frequency spectrum) on a two-dimensional frequency. In the figure, the horizontal axis represents the spatial frequency in the horizontal direction, and the vertical axis represents the spatial frequency in the vertical direction.

Hereinafter, the concept of the first embodiment will be briefly described. As described in the conventional example, the vertical high-frequency component shown by hatching in FIG. 17 includes a vertical resolution component in addition to the flicker component. In the conventional scanning line conversion device, since the vertical high-frequency component is also removed together with the flicker component, the resolution in the vertical direction is reduced, and there has been a problem that fine characters on a display cannot be read.

Hereinafter, the concept of the first embodiment will be described with reference to FIG. Generally, flicker occurring in a large area is much more visually noticeable than flicker occurring in a small area. That is,
While flicker occurring in a fine character portion or the like is not visually noticeable, flicker occurring in a horizontal line portion of a figure or a table is visually noticeable. When human eyes visually detect flicker, it is detected that flicker has occurred up to an image around the flicker, and it appears that flicker has occurred in a large area.

In the first embodiment, the vertical resolution component in which the flicker is visually inconspicuous is separated from the vertical high-frequency component, which is a cause of the large-area flicker. Then, the vertical resolution component is improved by adding the separated vertical resolution component to the image from which the vertical high frequency component has been removed. The above operation adds a vertical resolution component in which visual flicker is inconspicuous to the output image, so that the occurrence of flicker can be suppressed, and the vertical resolution in fine character portions is improved, so that fine characters can be recognized. it can. FIG. 4 shows frequency characteristics on a two-dimensional frequency of the first embodiment. In the figure, the hatched portion is the flicker component that is very noticeable visually. In the first embodiment, as shown in FIG. 4, a horizontal high-frequency component that is visually inconspicuous of flicker is separated from the separated vertical high-frequency component, and the separated horizontal high-frequency component is output to an output image. The feedback (addition) improves the resolution in the vertical direction.

The operation of the scanning line conversion apparatus according to the first embodiment will be described below with reference to FIGS. 1 to 4 and FIG. In addition,
Also in the first embodiment, a case will be described in which a non-interlaced image input based on the VGA standard is converted into an interlaced image and output as in the conventional example. The R, G, and B signals input through the input terminals 1a to 1c are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10. The two color difference signals (R-
YF and BY signals) are supplied to LPFs 30a and 30
At 0b, the horizontal band is limited to half. (Because the color difference signal is less noticeable than the luminance signal (Y signal), the image quality hardly deteriorates even if the signal band is limited to half.) The Y signal output from the matrix circuit 10 and the LPFs 30a and 30b RY output from
And BY signals are converted into digital video signals (digital signals) by A / D conversion circuits 3a to 3c. At this time, the signal band of the two color difference signals is LP as described above.
Since the signal is limited to half of the Y signal in F30a and F30b, the sampling clock at the time of A / D conversion is set to half of the sampling clock of the Y signal and converted to a digital video signal.

On the other hand, the VG input through the input terminal 2
The vertical synchronization signal and the horizontal synchronization signal are detected by the first synchronization detection circuit 4 from the synchronization signal of the A signal. The horizontal synchronization signal detected by the first synchronization detection circuit 4 is supplied to a first PLL circuit 5
Is input to The first PLL circuit 5 generates a VGA-side reference clock based on the input horizontal synchronization signal. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the second memory control circuit 32. At that time, as described above, the clock used for processing the two color difference signals is frequency-divided and output to half the frequency of the clock used for processing the Y signal. The vertical synchronization signal and the horizontal synchronization signal detected by the first synchronization detection circuit 4 are also input to the second memory control circuit 32.

The second memory control circuit 32 uses the horizontal synchronizing signal of the VGA signal outputted from the first synchronizing detection circuit 4 to use the line memory 23a in the flicker removing circuit 31.
23b and a digital video signal write control signal and a read control signal for the line memory 43 are generated. For example, when the line memories 23a to 23b and the line memory 43 are configured using FIFO memories as in the conventional example, the second memory control circuit 32 outputs a line address reset signal for writing and reading, a writing and reading operation. Enable signal (ENABL signal),
Also, write and read clock signals are output. The second memory control circuit 32 also generates a control signal for writing a digital video signal to the frame memories 7a to 7c using the vertical synchronization signal and the horizontal synchronization signal output from the first synchronization detection circuit 4. The specific control method of the frame memories 7a to 7c will be described later.

The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker elimination circuit 31.
Hereinafter, the operation of the flicker removal circuit 31 will be described with reference to FIG. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. Here, the operation of the first VLPF 6 will be described with reference to FIG. The Y signal input via the input terminal 20 is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input Y signal by one line and outputs it. The Y signal output from the line memory 23a is input to the multiplication circuit 25 and the line memory 23b. In the line memory 23b, similarly to the line memory 23a, the input Y signal is delayed by one line and output. The output of the line memory 23b is input to the multiplication circuit 24b. The line memories 23a and 23b are controlled using the data write and read control signals output from the second memory control circuit 32 via the input terminal 21.

The Y signals input to the multiplication circuits 24a and 24b are each multiplied by 0.25 and output. The Y signal input to the multiplication circuit 25 is multiplied by 0.5 and output. The outputs of the multiplication circuits 24a and 24b and the multiplication circuit 25 are added by the addition circuit 26 to remove high-frequency components in the vertical direction, and output from the first VLPF 6 via the output terminal 22. On the other hand, the Y signal input to the line memory 43 shown in FIG. 2 is output after being delayed by one line. The control of the line memory 43 is as follows.
The operation is performed using the data write and read control signals output from the second memory control circuit 32 via the input terminal 41.

In the subtraction circuit 44, the first VLP is obtained from the Y signal delayed by one line output from the line memory 43.
The vertical high frequency component of the Y signal is separated by subtracting the vertical low frequency component of the Y signal output from F6.
(In the line memory 43, the Y signal is delayed by one line in order to match the phase of the input Y signal with the vertical low-frequency component output from the first VLPF 6.) The output of the subtraction circuit 44 The signal is input to the first HHPF 45.
Hereinafter, the operation of the first HHPF 45 will be described with reference to FIG.

The vertical high-frequency component of the Y signal input via the input terminal 50 is stored in the register 52a and the multiplication circuit 5
3a. The vertical high frequency component of the Y signal delayed by one clock in the register 52a is input to the register 52b and the multiplier 54. The vertical high frequency component of the Y signal delayed by one clock in the register 52b is added to the multiplication circuit 53
b. The vertical high frequency component of the Y signal input to the multiplication circuits 53 a and 53 b is multiplied by −0.25 and output to the addition circuit 55. Similarly, the vertical high frequency component of the Y signal input to the multiplication circuit 54 is multiplied by 0.5 and
5 is input. In the addition circuit 55, the multiplication circuits 53a,
The vertical high frequency components of the Y signal output from 3b and 54 are added to separate a high frequency component in the horizontal direction (vertical high frequency component-horizontal high frequency component of the Y signal). The vertical high band-horizontal high band component of the Y signal separated by the adding circuit 55 is output via the output terminal 51. The registers 52a and 52b in the first HHPF 45 and the flicker removal circuit 31
The clock is supplied from the first PLL circuit 5 to the register 46 inside.

The vertical high band-horizontal high band component of the Y signal separated by the first HHPF 45 is input to the adding circuit 47.
On the other hand, the vertical low frequency component of the Y signal output from the first VLPF 6 is delayed by one clock in the register 46 and input to the adding circuit 47. (In the register 46, the vertical low-frequency component of the Y signal output from the first VLPF 6 and the first
In order to match the phase with the vertical high-frequency component of the Y signal output from the HHPF 45, the vertical low-frequency component of the Y signal is delayed by one clock. ) The adding circuit 47 adds the output of the first HHPF 45 and the output of the register 46.

The Y signal from which the flicker component has been removed by the flicker removing circuit 31, and the A / D conversion circuits 3b and 3
Two color difference signals (RY signal and BY signal) output from c are input to the frame memories 7a to 7c. Hereinafter, the operation of writing the digital video signal into the frame memory 7 will be described. The second memory control circuit 32 outputs to the frame memory 7 a control signal for converting a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal at a field frequency of 60 Hz. Specifically, a digital video signal input in a frame structure at the time of writing to the frame memory 7 is converted into a field structure and written.

Hereinafter, a method of generating a data write control signal to the frame memory 7 output from the second memory control circuit 32 will be described. First, when a vertical synchronization signal is input from the first synchronization detection circuit 4, the second memory control circuit 32 sets a field to be written to the frame memory 7 next. If the field setting result is the first field, a control signal for writing odd lines to the frame memory 7 is generated. If the field setting result is the second field, a control signal for writing even lines to the frame memory 7 is generated. . The above control uses the horizontal synchronization signal output from the first synchronization detection circuit 4 to determine the even / odd line and generate the control signal. that time,
In the first embodiment, the frame memory 7 is used in the same manner as in the conventional example.
Is controlled so that only the effective video signal portion of the VGA signal is written.

The non-interlaced digital video signals input to the frame memories 7a to 7c are converted into field-structured digital video signals (interlaced digital video signals) based on the write control signal output from the second memory control circuit 32. ) And stored in the frame memories 7a to 7c. Example 1
In this case, as in the conventional example, it is assumed that the frame memory 7 is composed of two field memories for the first field and the second field. Therefore, the second memory control circuit 32 generates a switching signal between the two field memories based on the field discrimination result in order to write the digital video signal converted into the interlaced structure into the frame memory 7. Further, in the second memory control circuit 32, a data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 is detected by the first synchronization detection circuit 4. Generated based on the vertical and horizontal synchronization signals.

On the other hand, T input through the input terminal 16
The vertical synchronization signal and the horizontal synchronization signal of the V-side synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. The second PLL circuit 11 generates a television-side reference clock based on the horizontal synchronization signal detected by the second synchronization detection circuit 12. At this time, the frequency of the sampling clock of the color difference signal is divided to half the frequency of the sampling clock of the Y signal. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the second memory control circuit 32. Note that the vertical synchronization signal, the horizontal synchronization signal, and the field determination result detected by the second synchronization detection circuit 12 are also input to the second memory control circuit 32.

The second memory control circuit 32 reads out the interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the field discrimination result (the field control signal). Memory switching signal, data read address, read control signal, etc.). In the frame memories 7a to 7c, digital video signals having an interlaced structure are read from the memories based on the read control signals output from the second memory control circuit 32.

The digital video signal of the interlaced structure read from the frame memories 7a to 7c is D / A
The signals are input to the conversion circuits 9a to 9c. D / A conversion circuit 9a
In 9c, the input interlaced digital video signal is converted into an interlaced analog video signal. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronization adding circuit 13. It should be noted that the synchronization adding circuit 13 includes the second synchronization detecting circuit 1
A synchronization signal is generated based on a vertical synchronization signal, a horizontal synchronization signal, and a field discrimination result output from 2, and added to the Y signal.

The two color difference signals (RY signal and BY signal) output from the D / A conversion circuits 9b to 9c are converted into modulated color signals (C signals) by the chroma encoder circuit 14 and output. It is output via the terminal 15b. At the time of chroma encoding (when two color difference signals are converted into modulated color signals), two chroma signals are output from the second sync detection circuit 12 based on the vertical sync signal, the horizontal sync signal, and the field determination result. Modulates the color difference signal. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

In the first embodiment, the VGA signal input in the state of the R, G, B signals is converted into a Y signal and two color difference signals (RY signal and BY signal) in the matrix circuit 10 in advance. After that, the signal processing is performed. This is for the following two reasons.

The first reason is due to the flicker detection characteristics of the human eye. Human vision detects the flicker occurring in the Y signal very sensitively, but is less sensitive to the flicker occurring in the color difference signal. As a result of performing flicker removal on the two color difference signals by computer simulation based on the above algorithm, almost no effect was obtained with respect to flicker removal as compared with a case where flicker removal was not performed. On the other hand, in the image from which flicker has been removed, the vertical resolution of the color difference signal is significantly reduced.

As for the image (video) input in the state of the R, G, B signals, as shown in the conventional example,
Unless flicker removal is performed on all image data of the G and B signals, visually detectable flicker cannot be removed. Therefore, in the first embodiment, after the input image data (R, G, B signals) are converted into a Y signal and two color difference signals (RY signal and BY signal) by the matrix circuit 10, the Y signal is converted to the Y signal.
A flicker removing circuit 31 is provided only in the signal processing system of the signal to remove flicker components. As a result, flicker removal is not performed on a color difference signal in which a flicker component is visually inconspicuous, so that the number of flicker removal circuits 31 can be reduced from three to one as compared with a conventional scanning line conversion device. In addition, since the flicker is not removed from the color difference signal in which flicker is not noticeable, a sufficient resolution component in the vertical direction can be ensured, so that a reduction in the resolution of the output image can be minimized.

The second reason is due to the visual characteristics of the human to the color difference signal. This is because human vision is sensitive to changes in the Y signal, but not so sensitive to changes in the color difference signal. That is, the above 2
Even if the horizontal signal band of two color difference signals (RY signal and BY signal) is half of the Y signal, the difference (color signal band difference) cannot be detected by human eyes. Therefore, in the first embodiment, the two color difference signals output from the matrix circuit 10 are converted into the LPFs 30a and 30b.
To limit the horizontal signal band to half. When the two color difference signals output from the LPFs 30a and 30b are converted into digital signals (digital video signals) by the A / D conversion circuits 3b and 3c, the frequency of the sampling clock is half the frequency of the sampling clock of the Y signal. Do. Therefore, the number of data of the color difference signal per frame can be halved as compared with the conventional example, so that the memory capacities of the frame memories 7b and 7c can be halved and the circuit scale can be reduced. effective. Further, since the clock frequency of the processing system for the two color difference signals can be halved, when the scanning line converter or the flicker removing circuit 31 is formed into an LSI,
There is an effect that power consumption can be suppressed.

Since the scanning line conversion device of the first embodiment is configured as described above, a horizontal high-frequency component in which flicker is not visually noticeable is extracted from a vertical high-frequency component.
By feeding back (adding) to the output image (vertical low frequency component), the resolution in the vertical direction can be improved, and flicker can be sufficiently suppressed visually. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the scanning line conversion method by computer simulation,
Although flicker of a small area slightly occurred in a diagonal line portion such as a character (a position at a viewing distance of about 1H), the resolution in the vertical direction was improved, and the recognition of fine characters was also improved as compared with the conventional example. The detected small area flicker was not detected from a position about 3H away from the screen.

Further, the flicker elimination circuit 31 shown in the first embodiment can be realized only by adding a simple circuit to the first VLPF 6 of the prior art, and is excellent without greatly increasing the circuit scale. There is an effect that an output image can be obtained.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to FIGS. 1, 3 to 6, and FIG. FIG. 5 is a block diagram of the flicker removal circuit 31 of the scanning line conversion device according to the second embodiment of the present invention. In the drawings, components denoted by the same reference numerals as those in the first embodiment have the same configuration and operation, and thus detailed description is omitted. Reference numeral 60 denotes a register, 61 denotes a subtraction circuit, 62 denotes an amplitude limiting circuit (hereinafter, referred to as an
Described as a limiter circuit or a limiter. ) And 63 are addition circuits. FIG. 6 is a diagram illustrating input / output characteristics of the limiter 62 according to the second embodiment. In the figure, the horizontal axis is input,
The vertical axis corresponds to the output. The input / output characteristics of the limiter 62 are not limited to those shown in FIG.

Next, the concept of the second embodiment will be briefly described. In the first embodiment, as shown in FIG. 4, a horizontal high-frequency component in which visual flicker is inconspicuous is extracted from a vertical high-frequency component, and is fed back (added) to an output image to sufficiently suppress flicker. The direction resolution has been improved. The purpose of the second embodiment is to suppress the occurrence of flicker and further increase the resolution in the vertical direction. In the second embodiment, a vertical resolution component is further extracted from a horizontal low-frequency component in a vertical high-frequency component indicated by hatching in FIG.
By doing so, the resolution in the vertical direction is improved. Specifically, the flicker detected by human eyes depends on the amplitude of the high frequency component in the vertical direction in addition to the flicker occurrence area described in the first embodiment. That is, even if flicker occurs, a small amplitude component of a high-frequency component in the vertical direction is not visually noticeable (cannot be detected).

In the second embodiment, the vertical resolution component in which flicker is not visually noticeable is separated according to the amplitude of the high frequency component in the vertical direction. Then, the vertical resolution component is improved by adding the separated vertical resolution component to the image from which the vertical high frequency component has been removed. The above operation adds a vertical resolution component in which visual flicker is inconspicuous to the output image, thereby improving the vertical resolution particularly in fine character portions, suppressing occurrence of flicker, and recognizing fine characters. be able to. In the second embodiment, the resolution component in the vertical direction is separated and output from the hatched area in the figure in which the high frequency component in the vertical direction and the low frequency component in the horizontal direction on the two-dimensional frequency shown in FIG. The case of returning to an image will be described. Therefore,
In the second embodiment, the vertical resolution component is extracted from the vertical high band-horizontal low band component removed in the first embodiment and is fed back (added) to the output image, thereby further increasing the vertical resolution. Can be improved.

The operation of the scanning line conversion apparatus according to the second embodiment of the present invention will be described below with reference to FIGS. 1, 3 to 6, and 19. In the second embodiment, only the configuration of the flicker elimination circuit 31 is different, and the other circuit operations are the same. Also, in the second embodiment, a case will be described in which a non-interlaced image input based on the VGA standard is converted into an interlaced image and output as in the conventional example. The R, G, and B signals input via the input terminals 1a to 1c are converted into a Y signal and two color difference signals by the matrix circuit 10. The two color difference signals output from the matrix circuit 10 are L
The horizontal band is limited to half by the PFs 30a and 30b. A Y signal output from the matrix circuit 10,
The two color difference signals output from the LPFs 30a and 30b are converted into digital video signals by A / D conversion circuits 3a to 3c. At this time, the two color difference signals are Y
The signal is converted into a digital video signal by a half sampling clock of the signal.

On the other hand, VG input via input terminal 2
The vertical synchronization signal and the horizontal synchronization signal are detected by the first synchronization detection circuit 4 from the synchronization signal of the A signal. In the first PLL circuit 5, VG is determined based on the detected horizontal synchronizing signal.
A side reference clock is generated. The clock generated by the first PLL circuit 5 is input to the A / D conversion circuits 3a to 3c and the second memory control circuit 32. that time,
As described above, the two clocks for the color difference signals are frequency-divided and output to half the frequency of the clock for the Y signal.

The second memory control circuit 32 uses the horizontal synchronizing signal of the VGA signal output from the first synchronizing detection circuit 4 to control the line memory 23a in the flicker removing circuit 31.
23b and a digital video signal write control signal and a read control signal for the line memory 43 are generated. In the second embodiment, as in the first embodiment, the line memories 23a to 23b and the line memory 43 are
It is assumed to be configured using an IFO memory. Therefore, the line address reset signal at the time of writing and reading, a write and read enable signal (ENABL signal), and a write and read clock are output from the second memory control circuit 32 to the flicker removal circuit 31. The second memory control circuit 32 also generates a control signal for writing a digital video signal to the frame memories 7a to 7c using the vertical synchronization signal and the horizontal synchronization signal output from the first synchronization detection circuit 4.

The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31.
The operation of the flicker removal circuit 31 will be described below with reference to FIGS. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. FIG. 19 shows a block diagram of the first VLPF 6. The detailed operation of the first VLPF 6 is described in the first embodiment.
Therefore, the description is omitted. On the other hand, the Y signal input to the line memory 43 is output after being delayed by one line.

The subtraction circuit 44 subtracts the vertical low-frequency component of the Y signal output from the first VLPF 6 from the Y signal delayed by one line in the line memory 43 to separate the vertical high-frequency component of the Y signal. . The output of the subtraction circuit 44 is input to the first HHPF 45 and the register 60. FIG. 3 shows a block diagram of the first HHPF 45. The detailed operation of the first HHPF 45 is the same as that of the first embodiment, and a description thereof will be omitted. On the other hand, the vertical high frequency component of the Y signal input to the register 60 is output after being delayed by one clock. The subtraction circuit 61 subtracts the vertical high-frequency component of the Y signal output from the first HHPF 45 from the vertical high frequency component of the Y signal delayed by one clock in the register 60. The vertical high band-horizontal low band component (vertical high band-horizontal low band data) of the Y signal output from the subtraction circuit 61 is input to a limiter 62.

The limiter 62 limits the amplitude of the vertical high-frequency component and the horizontal low-frequency component of the input Y signal and outputs the resultant signal. FIG.
(A) shows the input / output characteristics of the limiter 62. Limiter 6
The vertical-high-horizontal-low-frequency component of the Y signal whose amplitude has been limited by 2 is added to the vertical-high-horizontal-high-frequency component of the Y signal output from the first HHPF 45 by the adding circuit 63. The output (vertical resolution component) of the addition circuit 63 is
At 7, it is added to the vertical low frequency component of the Y signal output from the register 46 and output. In the second embodiment, the limiter 62 separates a small amplitude component (vertical resolution component) in which flicker is inconspicuous from a vertical high band-horizontal low band component of the Y signal. In the second embodiment, the vertical resolution is improved by feeding back (adding) the vertical high resolution component separated by the first HHPF 45 and the limiter 62 to the output image (vertical low frequency component). (In the case of the second embodiment, as a result of the computer simulation,
The amplitude of the high frequency component in the vertical direction of the Y signal is -127 to 128
When the maximum value of the amplitude limit value was set to about ± 10 to ± 20, good results were obtained. ) Note that the first HH
A first PLL to PF 45, registers 46 and 60
It is assumed that a clock is supplied from the circuit 5.

The Y signal from which the flicker component has been removed by the flicker removal circuit 31, and the A / D conversion circuits 3b and 3
c are output from the frame memory 7
a to 7c. Note that writing and reading of the digital video signal to and from the frame memory 7 are the same as those in the first embodiment, and a detailed description of the operation will be omitted. The second memory control circuit 32 converts a non-interlaced digital video signal input at a frame frequency of 60 Hz into an interlaced digital video signal having a field frequency of 60 Hz, and
Write data to

In the second memory control circuit 32, when writing data to the frame memory 7, first, a field to be written to the frame memory 7 based on the vertical synchronization signal output from the first synchronization detection circuit 4 Set. When the field setting result is the first field, a control signal is generated so as to write an odd-numbered line to the frame memory 7 when the field setting result is the second field.
The control signal for switching the lines is generated by discriminating the even / odd lines using the horizontal synchronization signal output from the first synchronization detection circuit 4.

The non-interlaced digital video signal input to the frame memories 7a to 7c is converted into a field-structured digital video signal based on the write control signal output from the second memory control circuit 32. 7c. In addition,
In the second embodiment, as in the first embodiment, it is assumed that the frame memory 7 includes two field memories for a first field and a second field. The second memory control circuit 32 sends a data write control signal (data write address, field memory switching signal, write control signal, etc.) to the frame memory 7 in the first memory control circuit 32.
Is generated based on the vertical synchronization signal and the horizontal synchronization signal detected by the synchronization detection circuit 4.

On the other hand, the T input through the input terminal 16
The vertical synchronization signal and the horizontal synchronization signal of the V-side synchronization signal are detected by the second synchronization detection circuit 12. At this time, the field determination is also performed by the second synchronization detection circuit 12. The second PLL circuit 11 generates a television-side reference clock based on the horizontal synchronization signal detected by the second synchronization detection circuit 12. The clock generated by the second PLL circuit 11 is input to the D / A conversion circuits 9a to 9c and the second memory control circuit 32. In the second memory control circuit 32, a read control signal (switching of the field memory) for reading an interlaced image stored in the frame memory 7 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the field determination result. Signal, data read address, read control signal, etc.). In the frame memories 7a to 7c, digital video signals having an interlaced structure are read from the memories based on the read control signals output from the second memory control circuit 32.

The digital video signals of the interlaced structure read from the frame memories 7a to 7c are D / A
The conversion circuits 9a to 9c convert the signals into analog video signals having an interlaced structure. The Y signal output from the D / A conversion circuit 9a is output via the output terminal 15a after the vertical synchronizing signal and the horizontal synchronizing signal are added by the synchronization adding circuit 13. The synchronization adding circuit 13 outputs a vertical synchronization signal, a horizontal synchronization signal, and a vertical synchronization signal output from the second synchronization detection circuit 12.
The sync signal is generated based on the result of the field discrimination and added to the Y signal. Also, D / A conversion circuits 9b to 9c
The two color-difference signals output from the color conversion circuit 14 are converted into a modulated color signal (C signal) by the
b. At the time of chroma encoding, two color difference signals are modulated based on a vertical synchronization signal, a horizontal synchronization signal, and a field determination result output from the second synchronization detection circuit 12. The modulated color signal (C signal) subjected to the modulation is output via the output terminal 15b.

In the second embodiment, the VGA signal input in the state of the R, G, and B signals is
, A Y signal and two color difference signals (R
The signal processing is performed after the conversion into the (-Y signal and the BY signal). However, since this is the same as in the first embodiment, detailed description is omitted.

In the second embodiment, similarly to the first embodiment, the input R, G, and B signals are converted by the matrix circuit 10 into a Y signal and two color difference signals (RY signal and BY signal).
After the conversion, the flicker removal circuit 31 removes the flicker component only from the Y signal, and does not remove the flicker component from the color difference signal in which the flicker component is visually inconspicuous. Thus, the number of flicker removing circuits 31 can be reduced from three to one.
In addition, since flicker is not removed from a color difference signal in which flicker is not conspicuous, there is an effect that a vertical resolution component can be sufficiently secured and a decrease in resolution of an output image can be minimized.

In the second embodiment, as in the first embodiment, two color difference signals output from the matrix circuit 10 are converted to LP signals.
F30a and 30b limit the horizontal signal band to half. The outputs of the LPFs 30a and 30b are A
The frequency of the sampling clock at the time of conversion into a digital video signal by the / D conversion circuits 3b and 3c is set to half the frequency of the sampling clock of the Y signal. Therefore,
Since the number of data of the color difference signal per frame can be halved as compared with the conventional example, the frame memory 7b
And 7c can be halved in memory capacity, and the circuit size can be reduced.

Since the scanning line conversion apparatus of the second embodiment is configured as described above, the horizontal high-frequency component and the horizontal low-frequency component in which flicker is less visually noticeable than the vertical high-frequency component. By extracting a small amplitude component and feeding it back (added) to the output image (vertical high-frequency component), the resolution in the vertical direction can be improved, and flicker can be sufficiently suppressed visually. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the above scanning line conversion method by computer simulation, a small area flicker occurred slightly in a diagonal line portion of a character or the like (at a position at a viewing distance of about 1H). The discrimination was further improved as compared with the conventional example. (The resolution was further improved compared to Example 1.) The detected small area flicker was not detected from a position about 3H away from the screen.

In the second embodiment, the shape (characteristics) of the limiter 62 has been described as shown in FIG. 6A. However, the present invention is not limited to this, and the configuration as shown in FIG. May be adopted. When the limiter shape shown in FIG. 6A and the limiter shape shown in FIG. 6B are compared by computer simulation, the same amplitude limit value (the maximum amplitude value output from the limiter 62) is obtained. The resolution was slightly improved in the limiter shape shown in FIG. 6 (b).

In the second embodiment, the limiter 62
When the amplitude limit value is increased, the vertical resolution is improved, but the amount of flicker increases. Therefore, it goes without saying that a plurality of types of the shape of the limiter 62 may be prepared, and the amplitude limit value of the limiter 62 may be switched according to the viewing distance or the type of the output image.
The setting of the limiter shape may be manually input by the user, or may be set by recognizing the character size on the personal computer side.

Further, the flicker elimination circuit 31 shown in the second embodiment can be realized only by adding a simple circuit to the conventional first VLPF 6, and a good output can be obtained without extremely increasing the circuit scale. There is an effect that an image can be obtained.

Embodiment 3 FIG. The scanning line converter according to the third embodiment differs from the first and second embodiments only in the configuration and operation of the flicker removing circuit 31 shown in FIG. Therefore,
Only the detailed configuration and operation of the flicker elimination circuit 31 will be described, and description of the same parts as those in the first or second embodiment will be omitted.

FIG. 7 is a block diagram of the flicker removing circuit 31 of the scanning line conversion device according to the third embodiment. In addition,
In the figure, components denoted by the same reference numerals as those in the first or second embodiment have the same configuration and operation, and thus detailed description is omitted. Reference numeral 70 denotes a second vertical low-pass filter (hereinafter, referred to as a second VLPF). FIG. 8 shows FIG.
2 is a block diagram of a second VLPF 70 in FIG.
In the figure, components having the same reference numerals as those of the embodiment and the conventional example have the same configuration and operation, and thus detailed description is omitted. 71a and 71b are multiplication circuits for multiplying the input data by 0.2, and 72 is a multiplication circuit for multiplying the input data by 0.6. FIG. 9 shows the second VLPF 7 in FIG.
It is a figure showing the frequency characteristic of 0. In the figure, the horizontal axis represents the spatial frequency in the vertical direction, and the vertical axis represents the amplitude characteristics. FIG. 10 is a diagram for explaining the basic concept of the flicker removal circuit 31 of the scanning line conversion device according to the third embodiment of the present invention.
FIG. 12 shows an area on a two-dimensional frequency in the third embodiment. In the figure, the horizontal axis represents the spatial frequency in the horizontal direction, and the vertical axis represents the spatial frequency in the vertical direction.

Next, the concept of the third embodiment will be briefly described. In the third embodiment, the data of the horizontal high-frequency component in which flicker is not visually noticeable (indicated as area 2 in FIG. 10) and the data of the horizontal low-frequency component in which flicker is noticeable (indicated as area 1 in FIG. 10) are flickered. By changing the shape of the filter applied in the vertical direction in order to remove the image, the occurrence of visually noticeable flicker is suppressed and the resolution in the vertical direction is improved.

In the third embodiment, a filter having a low degree of suppression of high-frequency components in the vertical direction is used for a high-frequency component in the horizontal direction in which flicker is not visually noticeable due to the above operation (see FIG. 9).
To remove the flicker component (high-frequency component in the vertical direction), and for the low-frequency component in the horizontal direction in which flicker is conspicuous, use a filter (see FIG. 20) having a high degree of suppression of the high-frequency component in the vertical direction. Since the component (high-frequency component in the vertical direction) is removed, the flicker component can be almost completely removed from the output image, and the resolution in the vertical direction can be improved.

Next, the operation of the flicker removing circuit 31 according to the third embodiment will be described with reference to FIGS. 3, 7 to 10, and 19 to 20. The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. The Y signal input via the input terminal 40 is input to the first HHPF 45 and the register 46. In addition,
FIG. 3 shows a block diagram of the first HHPF 45, and its operation is the same as that of the first embodiment, so that detailed description is omitted.

The horizontal high frequency component separated by the first HHPF 45 is input to the subtraction circuit 44 and the second VLPF 70. On the other hand, the input Y signal is
The clock is delayed and input to the subtraction circuit 44. In the subtraction circuit 44, the first signal is output from the Y signal output from the register 46.
Subtracts the horizontal high-frequency component of the Y signal output from the HHPF 45 to separate the horizontal low-frequency component of the Y signal. The horizontal low-frequency component of the Y signal separated by the subtraction circuit 44 is equal to the first V
Input to LPF6. The high-frequency component in the horizontal direction of the Y signal input to the second VLPF 70 is suppressed in the vertical direction. Hereinafter, the operation of the second VLPF 70 will be described with reference to FIG.

The horizontal high-frequency component of the Y signal input via the input terminal 20 is supplied to the multiplication circuit 71a and the line memory 2
3a. The line memory 23a delays the input high-frequency component of the Y signal by one line and outputs the delayed signal. The horizontal high frequency component of the Y signal output from the line memory 23a is input to the multiplication circuit 72 and the line memory 23b. In the line memory 23b, similarly to the line memory 23a, the horizontal high frequency component of the input Y signal is delayed by one line and output. The output of the line memory 23b is the multiplication circuit 7
1b. The line memories 23a and 23a
The control of 3b is performed by using the data write and read control signals output from the second memory control circuit 32 via the input terminal 21.

The horizontal high frequency component of the Y signal input to the multiplication circuits 71a and 71b is multiplied by 0.2 and output.
The high frequency component of the Y signal input to the multiplication circuit 72 is multiplied by 0.6 and output. Multiplication circuits 71a and 7
1b and the output of the multiplying circuit 72 are added by the adding circuit 26, the high-frequency component in the vertical direction is suppressed, and the result is output from the second VLPF 70 via the output terminal 22. FIG. 9 shows the second
5 shows the frequency characteristics of the VLPF 70 of FIG. As shown in the figure,
The frequency characteristic of the second VLPF 70 is the vertical high band (525 /
The amplitude suppression degree (around 2 lines) is the first VL shown in FIG.
It is smaller than the amplitude suppression degree of PF6.

On the other hand, the horizontal low-frequency component of the Y signal input to the first VLPF 6 is output after removing the vertical high-frequency component. Since the operation of the first VLPF 6 is the same as that of the first embodiment, detailed description of the operation is omitted. Also, the first and second VLPFs 6 and the line memory 23a in 70
It is assumed that the control of writing and reading of data into and 23b is performed based on a control signal output from the second memory control circuit 32 via the input terminal 41 as in the first embodiment.

In the adder circuit 47, the horizontal low-frequency component of the Y signal from the first VLPF 6 from which the flicker component has been removed and the horizontal high-frequency component of the Y signal from the second VLPF 70 from which the flicker component has been removed. The components are added to generate a Y signal from which a flicker component has been removed. The Y signal from which the flicker component has been removed by the flicker removing circuit 31,
The two color difference signals (RY signal and BY signal) output from the D conversion circuits 3b and 3c are converted and output from the non-interlaced structure to the interlaced structure in the frame memories 7a to 7c.

Since the scanning line conversion apparatus of the third embodiment is configured as described above, a horizontal high-frequency component in which visual flicker is inconspicuous and a horizontal low-frequency component in which visual flicker is noticeable, are used. By changing the characteristics of the vertical low-pass filter that removes flicker components, the generation of flicker is sufficiently suppressed, and the resolution in the vertical direction is increased, so that it is possible to identify fine characters and the like. As for the characteristics of the above filter, a filter having a characteristic of high suppression of the vertical high frequency component is used to remove the flicker component with respect to the horizontal low frequency component in which the flicker is visually noticeable. For the band component, a filter having a characteristic with a low degree of suppression of the vertical high band component is used in order to secure the resolution in the vertical direction.

The first and second VLPFs 6 for removing flicker from the horizontal low-frequency component and the horizontal high-frequency component
The circuit configurations 70 and 70 are not limited to those shown in FIGS. 19 and 8, and may be configured using a non-linear processing circuit including amplitude limiting means such as a limiter circuit as shown in the second embodiment. In this case, the characteristics of the flicker elimination circuit used for the low-frequency components in the horizontal direction are larger than those of the flicker elimination circuit used for the high-frequency components in the horizontal direction. It is configured to suppress the occurrence of flicker.

In the third embodiment, the case has been described in which the image is divided into two bands of a low-frequency component in the horizontal direction and a high-frequency component in the horizontal direction. However, the present invention is not limited to this. The same effect can be obtained if the image is divided into a plurality of areas on the dimensional frequency plane, and a flicker removing circuit is provided for each area to remove the flicker component and to extract the vertical resolution component. For example, horizontal low, horizontal mid, and horizontal high
It is needless to say that the same effect can be achieved by dividing the frequency band into two bands and providing a flicker removing circuit for each component to remove the flicker component and also extract the vertical resolution component.

As a result of confirming the effect of the above scanning line conversion method by computer simulation, in the first embodiment, a small area of flicker slightly occurred in a diagonal line portion such as a character (a position at a viewing distance of about 1H). It can be completely removed, the resolution in the vertical direction is improved, and the recognition of fine characters is improved as compared with the conventional example.

The flicker elimination circuit 31 shown in the third embodiment includes a conventional first VLPF 6 and a conventional first VLPF 6.
By combining and processing the second VLPF 70 having substantially the same configuration as that of No. 6, flicker can be removed with a simple circuit configuration, and an advantageous effect that a good output image can be obtained without extremely increasing the circuit scale is obtained. is there.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. The scanning line converter in the fourth embodiment differs from the first, second, and third embodiments only in the configuration and operation of the flicker removing circuit 31 shown in FIG. Therefore, only the detailed configuration and operation of the flicker removal circuit 31 will be described,
The description of the same parts as in the above embodiment is omitted.

FIG. 11 is a block diagram of the flicker removing circuit 31 of the scanning line converter according to the fourth embodiment. In the figure, 80 and 81 are addition circuits, 82 is a subtraction circuit,
83 is a low-pass high-pass separation filter.

Next, the concept of the fourth embodiment will be briefly described. In the fourth embodiment, as described in the second embodiment, the vertical resolution component included in the vertical high-frequency component of the video signal is extracted and fed back (added) to the output image to improve the vertical resolution. Measure. Specifically, as described in the second embodiment, the flicker detected by the human eye depends on the amplitude of the high frequency component in the vertical direction. That is, flicker is not visually noticeable for the small amplitude component of the high frequency component in the vertical direction. Therefore, in the fourth embodiment, a vertical resolution component in which flicker is not visually noticeable is separated according to the vertical high-frequency component amplitude. And
The vertical resolution is improved by adding the separated vertical resolution component to the output image from which the vertical high frequency component has been removed.

Since the above operation adds a vertical resolution component in which visual flicker is not noticeable to the output image, the vertical resolution particularly in fine character portions is improved, and the occurrence of flicker can be suppressed, and fine characters and the like can be suppressed. Can also be recognized. In the fourth embodiment, the second embodiment is used.
Although the circuit scale is smaller than that of the second embodiment, the amplitude limit value of the limiter 62 needs to be set to a value slightly larger than that of the second embodiment.

Next, the operation of the flicker removing circuit 31 according to the fourth embodiment will be described with reference to FIG. The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. Y input through the input terminal 40
The signal is input to the multiplication circuit 24a and the line memory 23a. The line memory 23a delays the input Y signal by one line and outputs it. The Y signal output from the line memory 23a is supplied to the multiplication circuit 25 and the line memory 23.
b. In the line memory 23b, similarly to the line memory 23a, the input Y signal is delayed by one line and output. The output of the line memory 23b is a multiplication circuit 24
b. Note that the line memories 23a and 23
The control of b is performed using the data write and read control signals output from the second memory control circuit 32 via the input terminal 41.

The Y signals input to the multiplication circuits 24a and 24b are multiplied by 0.25 and output. The Y signal input to the multiplication circuit 25 is multiplied by 0.5 and output. The outputs of the multiplication circuits 24a and 24b are
0 is added. Then, the outputs of the addition circuit 80 and the multiplication circuit 25 are added by the addition circuit 81, and the vertical low-frequency component (vertical low-frequency component) of the Y signal is separated. Similarly,
In the subtraction circuit 82, the output of the multiplication circuit 25 is added to the addition circuit 8
The output of 0 is subtracted, and the vertical high-frequency component (vertical high-frequency component) of the Y signal is separated. The high-frequency component in the vertical direction of the Y signal output from the subtraction circuit 82 is input to the limiter 62. Note that the low-pass high-pass separation filter 8 in the fourth embodiment
3 is a line memory 23a, 23b, a multiplication circuit 24a,
24b, 25, addition circuits 80, 81, and subtraction circuit 8
2 is comprised.

The limiter 62 limits the amplitude of the vertical high frequency component of the input Y signal and outputs the resultant signal. FIG. 6B shows an example of the input / output characteristics of the limiter 62 according to the fourth embodiment. The vertical high-frequency component of the Y signal, the amplitude of which is limited by the limiter 62, is added to the vertical low-frequency component of the Y signal by the adding circuit 47 and output. In the fourth embodiment, the limiter 62 controls the Y
A small amplitude component (vertical luminosity component) in which flicker is inconspicuous is separated from a vertical high frequency component of the signal. Then, the vertical resolution component separated by the limiter 62 is fed back (added) to the output image (vertical low frequency component) to improve the vertical resolution.

As a result of the computer simulation, in the case of the fourth embodiment, when the amplitude of the high-frequency component in the vertical direction of the Y signal is -127 to 128, the maximum value of the amplitude limit value is set to about ± 10 to ± 20. Then, good results were obtained. Control of the line memories 23a and 23b is as follows.
The data write and read control signals output from the second memory control circuit 32 through the input terminal 41 are used for the control. The Y signal from which the flicker component has been removed by the flicker removal circuit 31, and the two color difference signals (RY) output from the A / D conversion circuits 3b and 3c.
Signals and BY signals) are stored in the frame memories 7a to 7c.
Is converted from a non-interlaced structure to an interlaced structure and output.

Since the scanning line conversion apparatus according to the fourth embodiment is configured as described above, the Y line in which flicker is visually inconspicuous is not observed.
The resolution in the vertical direction can be improved by separating the small-amplitude component in the vertical high-frequency component of the signal and feeding it back (adding) to the output image (vertical low-frequency component). be able to. Therefore, there is an effect that fine characters and the like on the display can be recognized. As a result of confirming the effect of the above scanning line conversion method by computer simulation, a small area flicker occurred in a diagonal line portion of a character or the like (at a position at a viewing distance of about 1H). The discrimination was also improved as compared with the conventional example. The detected small area flicker was not detected from a position about 3H away from the screen.

Further, the flicker removing circuit 31 shown in the fourth embodiment can remove flicker with a simple circuit configuration by adding a subtraction circuit 82, an addition circuit 47 and a limiter 62 to the conventional first VLPF 6. There is an effect that a good output image can be obtained without extremely increasing the circuit scale.

Further, Y shown in Embodiment 1 and Embodiment 2
The configuration of the filter that separates the high-frequency component and the low-frequency component in the vertical direction of the signal is the same as the configuration of the low-frequency and high-frequency separation filter 83 in FIG. 11 according to the fourth embodiment, so that the line memory 43 can be omitted. There is an effect that the circuit scale can be reduced.

Embodiment 5 FIG. The scanning line conversion apparatus according to the fifth embodiment is different from the first, second, third, and fourth embodiments only in the configuration and operation of the flicker removing circuit 31 illustrated in FIG. Therefore, only the detailed configuration and operation of the flicker elimination circuit 31 will be described, and description of the same parts as those in the above embodiment will be omitted.

FIG. 12 is a block diagram of the flicker removing circuit 31 of the scanning line conversion device according to the fifth embodiment. In the figure, 90 is a DC detection circuit for extracting a DC component in the horizontal direction from the input vertical high frequency component in the vertical direction, 91 is a limiter, and 92 is an amplitude conversion circuit. FIG. 13 is a diagram illustrating the input / output characteristics of the limiter 91 according to the fifth embodiment of the present invention. In FIG. 13, the horizontal axis represents input and the vertical axis represents output. Similarly, FIG. 14 shows one of the input / output characteristics of the amplitude conversion circuit 92.
Examples have been shown. In the figure, the horizontal axis represents input and the vertical axis represents output.

Next, the concept of the fifth embodiment will be briefly described. As described in the second embodiment in the fifth embodiment, a vertical resolution component is further extracted from a horizontal low-pass component in a vertical high-pass component indicated by hatching in FIG.
Feedback (addition) to the output image improves the resolution in the vertical direction. Specifically, the flicker detected by human eyes in the horizontal direction depends on the amplitude of the high frequency component in the vertical direction, in addition to the flicker occurrence area described in the first embodiment. That is, even if a flicker occurs with respect to the small amplitude component of the high frequency component in the vertical direction, it is not visually noticeable. In the second embodiment, the limiter 62 controls the vertical high frequency range.
From the horizontal low-frequency component, a small-amplitude component with less noticeable flicker was extracted and fed back (added) to the output image (vertical low-frequency component).

In the second embodiment, the resolution in the vertical direction is improved by increasing the maximum amplitude value output from the limiter 62.
Because large area flicker occurs at the horizontal line of the table, etc.
The output maximum amplitude of the limiter 62 could not be sufficiently obtained.
In the fifth embodiment, the DC component in the horizontal direction is detected from the input Y signal, and the limiter shape (characteristic) is switched between the DC component in the horizontal direction and another component to improve the resolution in the vertical direction.

Further, by suppressing the output amplitude of the high-frequency component in the horizontal direction output from the first HHPF 45 by the amplitude conversion circuit 92, flicker generated in the oblique line portion can be eliminated. (If the amplitude of the above component is increased, the occurrence of flicker slightly increases, but the vertical resolution slightly increases.)

Next, the operation of the flicker removal circuit 31 of the fifth embodiment will be described with reference to FIGS. The Y signal converted into a digital signal by the A / D conversion circuit 3a is input to the flicker removal circuit 31. The Y signal input via the input terminal 40 is input to the first VLPF 6 and the line memory 43. FIG. 19 shows a block diagram of the first VLPF 6. Since the detailed operation of the first VLPF 6 is the same as that of the first embodiment, the description is omitted. On the other hand, the Y signal input to the line memory 43 is output after being delayed by one line.

The subtraction circuit 44 subtracts the vertical low-frequency component of the Y signal output from the first VLPF 6 from the Y signal delayed by one line in the line memory 43, and separates the vertical high-frequency component of the Y signal. . The output of the subtraction circuit 44 is the first H
It is input to the HPF 45 and the register 60. The first HHPF 45 is shown in a block diagram in FIG. 3, and the detailed operation is the same as that of the first embodiment, and the description is omitted. On the other hand, the vertical high frequency component of the Y signal input to the register 60 is output after being delayed by one clock. The subtraction circuit 61 subtracts the vertical high-frequency component of the Y signal output from the first HHPF 45 from the vertical high frequency component of the Y signal delayed by one clock in the register 60. The vertical high-horizontal low-frequency component of the Y signal output from the subtraction circuit 61 is input to a limiter 91.

Further, the output of the first HHPF 45 is input to the DC detection circuit 90. In the DC detection circuit 90, the first
A DC component (DC component) is detected from the vertical high-frequency component of the Y signal output from the HHPF 45 of FIG. Less than,
The operation of the DC detection circuit 90 according to the fifth embodiment will be briefly described. First, the DC detection circuit 90 separates the DC component in the horizontal direction by comparing the amplitude of the vertical high band-horizontal high band component of the input Y signal with a predetermined value. Specifically, when the amplitude of the vertical high band-horizontal high band component of the input Y signal is YHH, for example, if YHH ≦ α and YHH ≧ −α, it is determined that the DC component has been detected. (Α is a positive real number) Note that α is 1-3
A good result was obtained as a result of performing a simulation with the setting at about. (Simulation was performed with an amplitude of YHH of -127 or more and 128 or less.)

The limiter 91 restricts the amplitude of the vertical high band-horizontal low band component of the input Y signal and outputs it. Figure 1
As shown in FIG. 3, the limiter 91 switches the limiter shape (characteristic) based on the input DC detection information. Specifically, when a DC component is detected by the DC detection circuit 90,
In the fifth embodiment, the limiter 91 outputs 0. If the DC component is not detected, the amplitude value of the vertical high band-horizontal low band component of the input Y signal is limited according to the characteristics shown in FIG. The vertical high band-horizontal low band component of the Y signal whose amplitude is limited by the limiter 91 is input to the addition circuit 63.

On the other hand, the vertical high-frequency component of the Y signal output from the first HHPF 45 is input to the amplitude conversion circuit 92. In the fifth embodiment, as shown in FIG.
The amplitude of the vertical high-frequency component of the Y signal output from the HHPF 45 is increased by a factor of 0.5. (Note that the characteristic of the amplitude conversion circuit 92 is a linear conversion in the fifth embodiment, but may be a non-linear conversion.) The output of the amplitude conversion circuit 92 is input to the addition circuit 63. The addition circuit 63 adds the output of the amplitude conversion circuit 92 and the output of the limiter 91. The output (vertical resolution component) of the addition circuit 63 is
At 7, it is added to the vertical low frequency component of the Y signal output from the register 46 and output.

In the fifth embodiment, the limiter 91
A small amplitude component (resolution component in the vertical direction) in which flicker is inconspicuous is separated from a vertical high band-horizontal low band component of the Y signal.
In the fifth embodiment, the first HHPF 45 and the limiter 9
The vertical resolution is improved by feeding back (adding) the high resolution component in the vertical direction separated by 1 to the output image (low frequency component in the vertical direction). Note that in the case of the fifth embodiment, the DC component of a visually noticeable flicker is output as the amplitude value 0 by the limiter 91, so that the maximum value of the amplitude limit value of the limiter 91 is compared with the case of the second embodiment. Can be set large, so that the resolution in the vertical direction can be further improved. Also, the first HH
Since the amplitude of the vertical high band-horizontal high band component of the Y signal output from the PF 45 is reduced by the amplitude conversion circuit 92 and is output, the Y signal is generated in an oblique line portion such as a character described in the second embodiment. Small area flicker can also be removed.

The first HHPF 45 and the register 4
Clocks are supplied to 6 and 60 from the first PLL circuit 5. The line memories 23a and 23b and the line memory 43 in the first VLPF 6 are controlled by the second memory control circuit 3 via the input terminal 41.
2 is performed by using the data write and read control signals output from the second data. Flicker removal circuit 3
1, the Y signal from which the flicker component has been removed, and A / D
The two color difference signals (RY signal and BY signal) output from the conversion circuits 3b and 3c are converted and output from the non-interlaced structure to the interlaced structure in the frame memories 7a to 7c.

Since the scanning line conversion apparatus according to the fifth embodiment is configured as described above, it is possible to prevent the flicker from being visually noticeable.
By separating small amplitude components in the vertical high-frequency component of the signal and feeding it back (adding) to the output image (vertical low-frequency component), the resolution in the vertical direction can be improved, and the flicker is also visually sufficient. Can be suppressed. Therefore, there is an effect that fine characters and the like on the display can be recognized. In addition, the first H
Since the output amplitude of the HPF 45 is reduced, flicker of a small area, which has occurred in an oblique line portion of a character or the like, can be suppressed, and the resolution in the vertical direction is improved, and the identification of a fine character is further improved as compared with the conventional example. improves.

Further, the flicker removing circuit 31 shown in the fifth embodiment can remove flicker with a simple circuit configuration by adding a simple circuit to the conventional first VLPF 6, thereby significantly increasing the circuit scale. There is an effect that a good output image can be obtained without any. The DC component in the horizontal direction of the Y signal is detected by the DC detection circuit 90, and the shape (characteristic) of the limiter 91 is switched based on the DC detection result. By reducing the feedback amount of the low-frequency component, the feedback amount of the vertical high-frequency component and the horizontal low-frequency component can be increased with respect to components other than the direct current component, so that the resolution component in the vertical direction can be further improved.

Further, the line memory 43 can be omitted by adopting the configuration of the filter for separating the high frequency component and the low frequency component in the vertical direction of the Y signal shown in the fifth embodiment by using the configuration of FIG. 11 shown in the fourth embodiment. This has the effect of reducing the circuit scale. In the fifth embodiment, the shape of the limiter 91 is switched between the DC component and the other components. However, the present invention is not limited to this. A plurality of types of DC detection levels in the DC detection circuit 90 are prepared, and The configuration of the limiter 91 may be changed according to the detection level.

In the fifth embodiment, when the DC component is detected by the DC detection circuit 90, when the amplitude of the vertical high band-horizontal high band component of the input Y signal is YHH, YHH ≦
When α and YHH ≧ −α, it was determined that the DC component was detected. However, a DC component (DC component) is obtained from the vertical high-frequency component of the Y signal output from the first HHPF 45.
, The DC detection circuit 90 first detects the amplitude (YHH) of the vertical high-horizontal high frequency component of the Y signal input first.
Is compared with a predetermined value (α), and the above YHH
If the absolute value of is less than α, it may be determined that a DC component has been detected. In the fifth embodiment, the DC detection circuit 90
Is described as a logic circuit, but the present invention is not limited to this, and a DC component may be detected using a microcomputer or the like. At this time, as described above, the algorithm for detecting the DC component is set to YHH
In the case of <α and YHH> −α, a similar effect can be obtained even if a DC component is detected. Here, α is a positive real number.

In the fifth embodiment, the first HHPF 45
Although the DC component of the Y signal is detected using the output of the Y signal, the present invention is not limited to this. For example, the DC component is detected from the vertical high frequency component of the Y signal output from the subtraction circuit 44, or the input Y signal is detected. Needless to say, the same effect can be obtained by directly detecting the DC component. Further, in the fifth embodiment, the case where the amplitude of the data of the vertical high frequency-horizontal high frequency component input from the first HHPF 45 is suppressed by the amplitude conversion circuit 92 has been described. The amplitude may be increased and fed back (added) to the output image, in which case the vertical resolution further increases. Further, the amplitude conversion circuit 92 has a plurality of amplitude conversion data, and the user or a personal computer or the like discriminates a picture and switches it (for example, when the resolution is required, it is set to double, If it is desired to completely remove flicker, it is set to 0.5 times, and in other cases, it is set to 1.0), and the same effect can be obtained.

Further, the DC detection circuit 90 shown in the fifth embodiment is replaced with the flicker removal circuit 3 shown in the second or fourth embodiment.
The same effect can be obtained even if the limiter 63 is provided in the switch 1 so as to switch the characteristics of the limiter 63 based on the detection result of the horizontal DC component (or the DC component of the high-frequency component in the vertical direction) of the input signal.

Embodiment 6 FIG. In addition, the above-mentioned Examples 1 to 5
In the above, the operation of the scanning line conversion device was described using a VGA signal of a personal computer as an example of a non-interlaced image. However, the present invention is not limited to this, and non-interlaced images (for example, standards are currently being discussed in Europe) Non-interlaced images transmitted by digital broadcasting, such as DVB, ATV, which is being standardized in the United States, or ISDB, which is being standardized in Japan, or images in other display modes of personal computers. ) Is converted to an interlaced image, the same effect can be obtained by removing the flicker component using the scanning line conversion device and outputting the image.

In the first embodiment, the matrix circuit 10 converts the R, G, and B signals into a Y signal and two color difference signals (R-G
After the conversion into the Y signal and the BY signal), only the flicker component of the Y signal is removed, but the present invention is not limited thereto.
The flicker components included in the R, G, and B signals may be removed by the flicker removal circuit 31 and output. Further, the flicker component may be removed from the RY signal and the BY signal by the flicker removing circuit 31. In addition, when the flicker component in the color difference signal is removed, the characteristic or configuration of the flicker removal circuit 31 may be changed from the case where the flicker component in the luminance signal is removed. Needless to say, the characteristics or configuration of the flicker removal circuit 31 may be changed for each color difference signal.

Embodiment 7 FIG. In the first to fifth embodiments, when the image without fine characters or the viewing distance is long, the scanning line conversion is performed so as to output the image from which the high-frequency component in the vertical direction has been removed as shown in the conventional example. The device may be configured. In the first to fifth embodiments, the luminance signal (Y signal) and the two color difference signals (R-
Y signal and BY signal), but the present invention is not limited thereto. For example, a luminance signal (Y signal) and two color signals (U and V signals), or a luminance signal (Y signal), and Needless to say, the same effect can be obtained even if the flicker component is removed from the Y signal after the conversion into another color signal and the conversion into an interlaced image is performed. Further, the scanning line conversion may be performed after converting the two color difference signals into the modulated color signals.

In the first to fifth embodiments, the horizontal high-pass filter or the vertical low-pass filter is configured as shown in FIGS. 3, 8, 11 and 19. Configuration (number of taps, filter shape,
And type (FIR filter, IIR filter, etc.))
The frequency characteristics and the like are not limited to this. In the first to fifth embodiments, the vertical high-pass filter is configured by subtracting the output of the vertical low-pass filter from the input signal. However, the present invention is not limited to this. For example, the vertical high-pass filter and the vertical low-pass filter are separately configured, or the vertical high-pass component is separated using the vertical high-pass filter, and then the vertical high-pass component is subtracted from the input signal. This may constitute a vertical low-pass filter. Similarly, the horizontal high-pass filter and the horizontal low-pass filter are separately configured, or the horizontal low-pass component is separated using the horizontal low-pass filter, and then the horizontal low-pass component is subtracted from the input signal. This may constitute a horizontal high-pass filter. In addition,
In the first to seventh embodiments, the case of a non-interlaced image input in a frame unit has been described, but the present invention is not limited to this. For example, a non-interlaced image is converted to an interlaced image without performing flicker removal and transmitted or reproduced, and the same effect can be obtained by using the flicker removing circuits shown in the first to seventh embodiments.
Specifically, if the input interlaced image is reconstructed into a non-interlaced image by a field frame conversion circuit using a memory or the like, the flicker elimination circuits shown in the above-described embodiments 1 to 7 impair the vertical resolution more than necessary. The flicker component contained in the interlaced image can be removed without any problem.

[0145]

Since the present invention is configured as described above, it has the following effects.

According to the scanning line converter of the first aspect, since the interlace signal is generated based on the luminance signal in which the amplitude of the vertical high band-horizontal low band component is limited, flicker can be generated without deteriorating the resolution. Can be suppressed.

According to the scanning line converter of the second aspect, when the amplitude of the horizontal high frequency component is lower than the predetermined amplitude, the amplitude of the vertical high frequency component-horizontal low frequency component is set to be equal to or less than the first amplitude. Limit, if greater than the second smaller than the first amplitude
, The flicker can be suppressed without deteriorating the resolution.

According to the scanning line converter of the third aspect, when the horizontal DC component of the luminance signal is detected, the amplitude of the vertical high band-horizontal low band component of the luminance signal is set to 0. The occurrence of flicker can be suppressed without deteriorating the resolution in the vertical direction.

According to the scanning line conversion device of the fourth aspect, the interlace signal is generated based on the luminance signal in which the amplitude of the vertical high band-horizontal high band component and the vertical high band-horizontal low band component is reduced. In addition, it is possible to suppress the occurrence of flicker occurring in the hatched portion of the image without deteriorating the resolution.

According to the scanning line conversion apparatus of the fifth aspect, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half of the luminance signal, so that generation of flicker is suppressed without deteriorating the resolution. In addition, the capacity of the frame memory for the resolution can be reduced.

According to the scanning line converter of the sixth aspect, the amplitude of the vertical high frequency component included in the horizontal low frequency component is limited so as to be smaller than the amplitude of the vertical high frequency component included in the horizontal high frequency component. Therefore, it is possible to suppress the occurrence of flicker without deteriorating the resolution.

According to the scanning line conversion apparatus of the present invention, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half of a luminance signal, so that generation of flicker is suppressed without deteriorating resolution. In addition, the capacity of the frame memory for the resolution can be reduced.

According to the scanning line converter of the eighth aspect, an interlace signal is generated based on the luminance signal of which the amplitude of the vertical high frequency component is limited, so that the occurrence of flicker is suppressed without deteriorating the resolution. be able to.

According to the scanning line converter of the ninth aspect, since only the vertical high-frequency component exceeding a predetermined amplitude value is removed, it is possible to suppress the occurrence of flicker without deteriorating the resolution in the vertical direction.

According to the tenth aspect of the present invention, an interlace signal is generated based on a color difference signal sampled at a clock frequency equal to or less than half of a luminance signal, so that generation of flicker is suppressed without deteriorating resolution. In addition, the capacity of the frame memory for the resolution can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a scanning line conversion apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a flicker removing circuit in FIG. 1;

FIG. 3 is a block diagram of a first HHPF in FIG. 2;

FIG. 4 is a diagram for explaining a basic concept of a flicker removal circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a flicker removing circuit of the scanning line conversion device according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating input / output characteristics of a limiter according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a flicker removal circuit of a scanning line conversion apparatus according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a second VLPF in FIG. 7;

9 is a diagram illustrating a frequency characteristic of a second VLPF in FIG. 8;

FIG. 10 is a diagram for explaining a basic concept of a flicker removal circuit according to a third embodiment of the present invention.

FIG. 11 is a block diagram illustrating a flicker removal circuit of a scanning line conversion apparatus according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a flicker removal circuit of a scanning line conversion device according to a fifth embodiment of the present invention.

FIG. 13 is a diagram illustrating input / output characteristics of a limiter according to a fifth embodiment of the present invention.

FIG. 14 is a diagram illustrating input / output characteristics of an amplitude conversion circuit according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a spatial frequency characteristic of a non-interlaced image.

FIG. 16 is a diagram showing a spatial frequency characteristic of an interlaced image.

17 is a diagram showing characteristics of the interlaced image shown in FIG. 16 on a two-dimensional frequency.

FIG. 18 is a block diagram of a conventional scanning line conversion device.

FIG. 19 is a block diagram of a first conventional VLPF.

FIG. 20 is a diagram showing frequency characteristics of a first conventional VLPF.

[Explanation of symbols]

6 first VLPF, 7 frame memory, 10 matrix circuit, 23 line memory, 24 multiplication circuit, 2
5 Multiplication circuit, 26 addition circuit, 30 LPF, 31
Flicker removal circuit, 32 Second memory control circuit, 43
Line memory, 44 subtraction circuit, 45 first HHP
F, 46 registers, 47 addition circuits, 52 registers, 53 multiplication circuits, 54 multiplication circuits, 55 addition circuits, 60 registers, 61 subtraction circuits, 62 limiters, 63 addition circuits, 70 second VLPFs, 71 multiplication circuits, 72 multiplications Circuit, 80 addition circuit, 81 addition circuit, 82 subtraction circuit, 83 low-pass high-pass separation filter, 90 DC detection circuit, 91 limiter, 92 amplitude conversion circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04N 5/205 H04N 11/00 11/00 11/24 (72) Inventor Naotoshi Maeda Nagaokakyo Baba Zhousho 1 Address Mitsubishi Electric Corporation Video System Development Laboratory F-term (reference) BA20 CA01 CA03 5C082 BA12 BB02 BB25 BC19 BD01 CA84 MM10

Claims (10)

[Claims] 1. A means for converting a non-interlaced signal composed of R, G, and B signals into a luminance signal and a color difference signal, wherein the amplitude of a vertical high band-horizontal low band component of the luminance signal is reduced to a predetermined amplitude or less. Means for limiting, and means for generating an interlace signal by thinning out a predetermined line of the luminance signal and the color difference signal whose amplitude of the vertical high band-horizontal low band component is limited. Scanning line converter. 2. A means for detecting the amplitude of a horizontal high-frequency component of a luminance signal, and when the amplitude of the horizontal high-frequency component falls below a predetermined amplitude, the amplitude of the vertical high-frequency component is reduced to a first amplitude. Means for limiting the amplitude of the horizontal high frequency component to be less than or equal to the second amplitude that is smaller than the first amplitude when the amplitude of the horizontal high frequency component exceeds the predetermined value. 2. The scanning line conversion device according to claim 1, further comprising: means for restricting the scanning line conversion to be as follows. 3. The apparatus further comprises means for detecting a horizontal DC component of the luminance signal, wherein when the DC component is detected, the amplitude of a vertical high-horizontal low-frequency component of the luminance signal is set to 0. The scanning line conversion device according to claim 1, wherein: 4. The apparatus further comprises means for reducing the amplitude of the vertical high-frequency component of the luminance signal, and interlacing the interlaced signal based on the luminance signal of which the amplitude of the vertical high-frequency component is reduced. Claim 1 characterized by generating
4. The scanning line conversion device according to any one of 3. 5. The apparatus according to claim 1, further comprising means for limiting the signal band of the color difference signal to less than half of the signal band of the luminance signal, and sampling the color difference signal having the restricted signal band at a clock frequency of less than half of the luminance signal. The scanning line conversion device according to claim 1, wherein an interlace signal is generated based on the sampled color difference signal. 6. A means for converting a non-interlace signal consisting of R, G, and B signals into a luminance signal and a color difference signal, means for outputting a horizontal high-frequency component of the luminance signal, Means for outputting a horizontal low-frequency component of the luminance signal by subtracting a high-frequency component,
First band limiting means for limiting the amplitude of the vertical high-frequency component included in the horizontal high-frequency component, and the vertical band height included in the horizontal high-frequency component included in the horizontal high-frequency component. Second limiting the amplitude to be smaller than the amplitude of the band component
And a means for generating an interlace signal by thinning out predetermined lines of the luminance signal and the color difference signal, the amplitude of the vertical high frequency component of which is limited by the first and second band limiting means. A scanning line conversion device comprising: 7. The apparatus further comprises means for limiting a signal band of the color difference signal to less than half of a signal band of the luminance signal, and sampling the color difference signal having the restricted signal band at a clock frequency of less than half of the luminance signal. The scanning line conversion device according to claim 6, wherein an interlace signal is generated based on the sampled color difference signal. 8. A means for converting a non-interlace signal consisting of R, G, and B signals into a luminance signal and a color difference signal, means for limiting the amplitude of a vertical high frequency component of the luminance signal, Means for generating an interlace signal by thinning out predetermined lines of the luminance signal and the chrominance signal whose component amplitudes are limited. 9. The scanning line conversion device according to claim 8, wherein only the vertical high frequency component exceeding a predetermined amplitude value is removed. 10. The image processing apparatus further comprises means for limiting a signal band of a color difference signal to less than half of a signal band of a luminance signal, and sampling the color difference signal having the limited signal band at a clock frequency of less than half of the luminance signal. 10. The scanning line conversion device according to claim 8, wherein an interlace signal is generated based on the sampled color difference signal.