JP2009267753A - Image format converting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image quality deterioration of a converted interlace signal by converting a format so as to use only the signal of an original line without using the signal of an interpolation line when a progressive signal converted from an interlace signal is converted again to an interlace signal. <P>SOLUTION: A detection device 13 detects whether an input progressive signal is a converted progressive signal obtained by converting the interlace signal comprising the signal of the original line of the interlace signal and the signal of the interpolation line obtained by interpolating the signal of the original line and further detects whether the signal of an input line is the signal of the original line or the signal of the interpolation line. A PI converter 14 thins out the signal of the interpolation line in the progressive signal from ADC 12 based on the detection signal from the detection device 13 and outputs the interlace signal only comprising the signal of the original line. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image format conversion apparatus, and more particularly to an image format conversion apparatus that converts a progressive signal (sequential scanning signal) of a video signal into an interlace signal (interlaced scanning signal).

  In recent years, video signal formats have been diversified along with higher image quality in DVDs (Digital Versatile Discs), digital broadcasts, TV games, and the like. Many devices that reproduce these videos have a function of converting (up-converting) into a higher-resolution video signal format.

  An image format conversion technique for converting an interlace signal into a progressive signal in an image processing circuit is conventionally known (see, for example, Patent Document 1). FIG. 9 shows a block diagram of an example of an image format conversion apparatus using the above-described image format conversion technique. In FIG. 9, the interlace signal input to the input terminal 1 is supplied to the motion detection circuit 2 and the progressive conversion circuit 3, respectively. The motion detection circuit 2 detects whether the pixel to be interpolated is moving or stationary based on the input interlace signal. The progressive conversion circuit 3 performs motion adaptive interpolation for appropriately switching the pixels used for interpolation on the interlaced signal input from the input terminal 1 in accordance with the motion detection result of the motion detection circuit 2 and converts the interlace signal to a progressive signal. To output terminal 4.

  FIG. 10 shows a configuration diagram of an example of the progressive conversion circuit 3 in FIG. 10, the progressive conversion circuit 3 includes a 1-field delay circuit 32, an 1-line delay circuit 33, and an interpolation filter circuit 34 to which an interlace signal is branched and input from the input terminal 1 to the input terminal 31 in FIG. , And a mixed addition circuit 35. The motion detection circuit 2 in FIG. 10 is the motion detection circuit 2 in FIG.

  Next, the operation of the progressive conversion circuit 3 will be described with reference to FIG. In FIG. 11, pixel P11 is a pixel that is going to be created by interpolation. In the same field, the pixel above the pixel P11 on the screen is P10, the pixel below is P12, and the pixels at the same position on the screen before and after one field are P01 and P21.

In FIG. 10, the interpolation filter circuit 34 interpolates the pixel P11 of FIG. 11 from the input interlace signal and the signal delayed by one line by the one-line delay circuit 33.
(1/2) · P10 + (1/2) · P12
An interpolation pixel having a value calculated based on the following calculation formula is generated. That is, the interpolation filter circuit 34 performs interpolation from the upper and lower pixels P10 and P12 of the interpolation pixel P11 in the same field (intra-field interpolation). The spatial frequency characteristics of this interpolation pixel are shown in FIG.

  The mixing and adding circuit 35 includes a value obtained by multiplying the value of the pixel P01 one field before the pixel P11 of the current field obtained by delaying one field by the one-field delay circuit 32 by the coefficient (1-k), and the interpolation circuit 34. The value obtained by multiplying the output interpolation pixel value by the coefficient k is mixed and added. The coefficients (1−k) and k are set according to the motion detection result of the motion detection circuit 2.

  That is, the motion detection circuit 2 detects a motion from the change in the value of the pixel P01 one field before and the pixel P21 one field after the pixel P11 in the current field, and if there is a motion, detects the motion and detects the coefficient k. Is set to “1”, and if there is no motion, it is detected as a still image and the coefficient k is set to “0”.

  As a result, the mixed addition circuit 35 sets k = 1 when the input pixel is detected as a moving image by the motion detection circuit 2, so that the interpolation pixel generated by the intra-field interpolation output from the interpolation filter circuit 34. Is output to the output terminal 36 as it is. In addition, when the pixel is detected as a still image by the motion detection circuit 2, the mixing and adding circuit 35 sets k = 0, so that the 1-field delay signal output from the 1-field delay circuit 32 (see FIG. 11). Pixel P01) is output as is to the output terminal 36 as an interpolation pixel.

  On the other hand, an image format conversion device that converts a progressive signal into an interlace signal is also known (see, for example, Patent Document 2). In the image format conversion apparatus described in Patent Document 2, the progressive signal is separated into a main signal and an auxiliary signal for each scanning line, and the horizontal scanning time is extended to the time of the interlace scanning system to form two interlace signals. In this configuration, the two interlace signals are converted and blanked.

JP 2004-328654 A JP-A-8-140060

  The progressive signal converted from the interlace signal by the image format conversion apparatus in FIG. 9 is composed of signals of the original line and the interpolation line of the interlace signal. Among the progressive signals, the pixel P10 and the pixel P12 in FIG. 10 are pixels in the original interlace signal (original line), and the characteristics are not deteriorated as compared with the original interlace signal. On the other hand, the pixel P11 is a pixel in a line (interpolation line) created by interpolation as described above, and in the case of intra-field interpolation, signal characteristics are deteriorated as compared with inter-field interpolation.

  When a progressive signal converted from such an interlace signal is subjected to format conversion to the original interlace signal again, it can be converted to the original interlace signal by converting only the signal of the original line. When converted to an interlaced signal using only the signal, the signal is a signal in which the high frequency component of the spatial frequency is degraded. In the apparatus for converting a progressive signal to an interlaced signal in Patent Document 2, there is no means for determining whether a line of the progressive signal is an original line or an interpolation line, so there is a possibility that conversion is performed using an interpolation line. Image quality degradation cannot be improved.

  The present invention has been made in view of the above points, and when converting a progressive signal converted from an interlace signal into an interlace signal again, a format is used so that only the signal of the original line is used without using the signal of the interpolation line. An object of the present invention is to provide an image format conversion device that improves image quality deterioration of a converted interlace signal by performing conversion.

  In order to achieve the above object, the present invention converts an interlace signal in which an input progressive signal is composed of an original line signal of an interlace signal and an interpolated line signal obtained by interpolating the original line signal. It is determined whether the signal of the line constituting the converted progressive signal is an original line signal or an interpolated line signal. Detection means for detecting based on the magnitude of the high-frequency component in the vertical direction in each of the signals, and based on the detection result of the detection means, the interpolation line signal is thinned out from the input progressive signal, and the original signal consisting only of the original line signal Conversion means for converting into an interlaced signal.

Here, the detection means is
First filter means for extracting a first high-frequency component that is a high-frequency component in the vertical direction in an odd-line signal of the input progressive signal, and a vertical high-frequency component in an even-line signal of the input progressive signal A second filter means for extracting the second high frequency component, and the odd frequency high frequency component and the even frequency high frequency component extracted by the first and second filter means are subtracted to generate an odd number When the signal of the line is the signal of the original line of the interlace signal, it has one polarity of positive polarity and negative polarity. When the signal of the even line is the signal of the original line of the interlace signal, it has the other polarity of positive polarity and negative polarity. The difference signal generating means for generating a difference signal, the integrating means for integrating the difference signal for a certain period, and the signal output from the integrating means are 1 When a signal having a positive polarity or a negative threshold level or more having the same polarity in a frame period and a signal having a positive polarity or a negative threshold level or more having different polarity alternately every frame period, the input progressive signal is And determining means for determining that the signal is a converted progressive signal and determining that a signal of one line having a level equal to or higher than a positive or negative threshold output from the integrating means is a signal of the original line.

  According to the present invention, when converting a progressive signal converted from an interlace signal into an interlace signal again, the conversion is performed by performing format conversion so that only the signal of the original line is used without using the signal of the interpolation line. It is possible to improve image quality deterioration of the later interlace signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of an image format conversion apparatus according to the present invention. The image format conversion apparatus 10 of the present embodiment shown in FIG. 1 is an A / D converter (ADC) that converts an analog video signal (a progressive signal in this case) input via an input terminal 11 into a digital video signal. 12, a detection device 13 for performing a predetermined detection process on the digital video signal output from the ADC 12, and a progressive-interlace conversion for the digital video signal output from the ADC 12 according to the detection result of the detection device 13. (Hereinafter referred to as PI conversion) and a PI converter 14 that outputs an interlace signal to the terminal 15.

  FIG. 2 is a circuit diagram of an embodiment of the detection device 13 in FIG. As shown in the figure, the detection device 13 includes a memory 132 that stores a digital video signal input from the ADC 12 of FIG. 1 via an input terminal 131, and a high-frequency component of the signal output from the memory 132 in units of lines. High pass filters (HPF) 133 and 134, level comparator 135 for level comparison of signals output from HPF 133 and 134, integrator 136 for integrating the output signal of level comparator 135, and integrator A predetermined discriminating operation is performed on the signal output from 136, and whether the input video data that is a progressive signal is video data in which the original image is progressive or whether the interlace signal is converted into a progressive signal is determined. The determination result is output to the PI converter 14 of FIG. 1 via the output terminal 138. More composed of the circuit 137.

  Next, the operation of the present embodiment will be described.

  In FIG. 2, the memory 132 temporarily stores the progressive signal converted into the digital video signal (video data) by the ADC 12, and then divides the video signal into odd-numbered video data and even-numbered video data. Output. The high pass filter (HPFodd) 133 filters the high frequency components of the odd line video data from the memory 132 and supplies the filtered high frequency components to the level comparator 135. A high-pass filter (HPFeven) 134 filters high-frequency components of even-line video data from the memory 132 and supplies the filtered high-frequency components to the level comparator 135.

  Here, in the case where the output video data of the memory 132 is video data of an interpolation line of a progressive signal obtained by up-converting an interlace signal, the high frequency component of the spatial frequency is degraded compared to the video data of the original line. Therefore, the output signals of the high-pass filters 133 and 134 are output at a lower level than the original line when the input video data is an interpolation line.

  Therefore, the signal level comparator 135 that outputs a signal obtained by subtracting the even-line signal output from the high-pass filter 1334 from the odd-line signal output from the high-pass filter 133 allows the odd-line signal to be output from the interpolation line. In the case of a signal, a negative polarity signal is output, and when the even line signal is an interpolation line signal, a positive polarity signal is output.

  The polarity relationship between these signals indicates the same state in the same frame. In addition, the front and rear frames show opposite polarity relations. This is because the relationship between the interpolation line and the original line is alternately repeated for each line in one frame, and the order is changed in the next frame.

  The integrator 136 integrates the signal from the level comparator 135. The discriminating circuit 137 discriminates whether the input signal line is the original line or the interpolation line based on the polarity of the signal from the integrator 136, and sends the discrimination result to the PI converter 14 in FIG. 1 via the output terminal 138. Output.

  Next, operations of the memory 132, the high-pass filters 133 and 134, and the level comparator 135 will be described more specifically and in detail.

  FIG. 3 shows a specific circuit diagram of an embodiment of the detection device 13 in FIG. In the figure, the same components as those in FIG. In FIG. 3, the one-line delay circuits 21, 22 and 23 cascaded to the input terminal 131 constitute the memory 132 of FIG. Also, the high-pass filters (hereinafter referred to as V-HPF) 24 and 25 in the vertical direction in FIG. 3 constitute the high-pass filters 133 and 134 in FIG.

Next, the operation of the detection device 13 in FIG. 3 will be described. The progressive signal converted into a digital video signal (video data) by the ADC 12 in FIG. 1 is delayed by one line by the one-line delay circuits 21, 22 and 23 via the input terminal 131. The V-HPF 24 receives three pieces of delayed video data obtained by delaying the input video data output from the one-line delay circuits 21, 22, and 23 by one line, two lines, and three lines, respectively. Then, each calculation based on a predetermined calculation formula is performed to output a high frequency component of the input video data. Here, the above-described predetermined arithmetic expression is obtained by inputting the adjacent three lines of pixels P10, P11, and P12 in the same field shown in FIG.
(-1/4) * P10 + (1/2) * P11 + (-1/4) * P12
It is. FIG. 4 shows the spatial frequency characteristics of the V-HPF 24.

  The other V-HPF 25 inputs the input video data of the input terminal 131 and two delayed video data obtained by delaying the input video data output from the one-line delay circuits 21 and 22 by one line and two lines, respectively. The input video data is calculated based on a predetermined calculation formula, and the high frequency component of the input video data is output. The V-HPF 25 has the same configuration as the V-HPF 25 except that the input video data is different from the V-HPF 24. Therefore, the spatial frequency characteristic of the V-HPF 25 is expressed by the same characteristic of FIG. 4 as that of the V-HPF 24. In this way, the high frequency component of the odd line video data is output from the V-HPF 24, and the high frequency component of the video data of the even line of the next line is output from the V-HPF 25.

  Next, the level comparator 135 outputs a differential signal obtained by subtracting the signal of the even line of the next line from the V-HPF 25 from the signal of the odd line from the V-HPF 24. The integrator 136 takes an absolute value of the difference signal and performs an integration process. The discriminator 137 performs a predetermined discriminating operation on the signal output from the integrator 136 and converts the input video data, which is a progressive signal, into whether the original image is progressive video data, or converts the interlace signal into a progressive signal. It is discriminated whether the video data has been processed, and the discrimination result is output to the output terminal 138.

  Next, the discrimination operation of the discriminator 137 will be described in detail using an example when actual video data is input.

  FIG. 5 shows timing charts of the output signals of the V-HPFs 24 and 25, the output signal of the level comparator 135, and the output signal of the integrator 136 when the original image is input with progressive video data. FIG. 6 shows the output signals of the V-HPFs 24 and 25 when the same image as that shown in FIG. 5 is taken as an interlace signal and the interlaced signal is converted into a progressive signal by the circuit shown in FIG. , Timing charts of the output signal of the level comparator 135 and the output signal of the integrator 136 are shown.

  In the case of video data obtained by converting an interlace signal into a progressive signal, the video data of the interpolation line shows the high-frequency attenuation characteristics shown in FIG. 12, so that the V-HPF 24 or 25 shown in FIG. Only a minute level is output. The difference signal between adjacent lines appears in a positive or negative fixed direction, as indicated by 3 in FIG.

  However, in the progressive signal composed of only the original line, there is no regularity in the difference between adjacent lines, so the difference signal output from the level comparator 135 is on both sides of plus / minus as shown by 3 in FIG. appear. However, since this is easily affected by the pattern, in the present embodiment, the integrator 136 integrates the difference signal for a certain period. The output signal of the integrator 136 has a waveform indicated by 4 in FIG. 5 for a progressive signal composed of only the original line, and in the case of video data obtained by converting an interlace signal into a progressive signal, the waveform indicated by 4 in FIG. Become.

  3 determines that the input video data is video data obtained by converting an interlace signal into a progressive signal when the output signal of the integrator 136 exceeds a predetermined threshold value. In this embodiment, in the case of video data obtained by converting an interlace signal into a progressive signal, the polarity of the difference signal is positive when the original line is an odd line and negative when the original line is an even line. Accordingly, the discrimination circuit 137 is an interlace signal in which the odd line is the original line if the polarity of the output signal of the integrator 136 is positive for one frame period, and the even line is the original line if the polarity is negative for one frame period. Is determined to be video data converted into a progressive signal.

  The above operation is the description of the detection device 13 of FIG. The PI converter 14 shown in FIG. 1 is configured such that the input line of the input video data supplied from the ADC 12 is an interlace signal based on the detection signal output from the detection device 13 (the determination signal output from the determination circuit 137). Is determined to be an original line or an interpolation line of video data converted into a progressive signal, and only the interpolation line is thinned out. Thereby, the PI converter 14 can convert again the video data obtained by converting the interlace signal into the progressive signal into an interlace signal consisting only of the original line of the original interlace signal, and outputs the interlace signal to the output terminal 15. To do. In this way, the video data obtained by converting the interlace signal into the progressive signal can be converted again into the original interlace signal without image quality deterioration.

  According to the present invention, when displaying a video signal input having a pixel number higher than the number of pixels of the display element, it is possible to realize a TV that can display even if the processing capacity of the image processing circuit is small and minimizes image quality degradation. It is. A specific description thereof will be described with reference to the examples of FIGS.

  FIG. 7 shows a block diagram of an example of an image display device using the image format conversion device of the present embodiment. In the figure, a WXGA display element 42 is a 1366 × 768 pixel display element as in FIG. Here, in FIG. 7, when the progressive signal (1080p progressive signal) having 1080 effective scanning lines converted from the interlace signal is converted into the interlace signal again and the WXGA display element 42 performs image display, FIG. The image format conversion apparatus 43 according to the present embodiment described with reference to FIG. 3 converts the progressive signal into an interlace signal (1080i interlace signal) having 1080 effective scanning lines composed only of the original line of the original interlace signal. .

  The image processing circuit 44 performs predetermined signal processing on the 1080i interlaced signal output from the image format conversion device 43 and supplies it to the WXGA display element 42 to display an image. Here, the image processing circuit 44 may be a circuit having a processing capacity of 74.2 MHz, which is a frequency of the 1080i interlaced signal to be input, and may be half the operating frequency of the conventional image processing circuit 41 shown in FIG. Circuit scale, cost, power consumption, and the like can be reduced as compared with the image display apparatus shown in FIG.

  Thus, according to the present embodiment, when displaying a video signal input having a pixel number higher than the number of pixels of the display element, even if the processing capability of the image processing circuit is small, it can be displayed by the display element. In addition, it is possible to realize an image display apparatus that minimizes image quality degradation.

  Note that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be applied to, for example, a progressive signal or an interlace signal having an effective number of scanning lines other than the above-described embodiment.

It is a block diagram of one embodiment of an image format conversion device of the present invention. FIG. 2 is a circuit diagram of an embodiment of the detection device 13 in FIG. 1. FIG. 2 is a specific circuit diagram of an embodiment of the detection device 13 in FIG. 1. It is a figure which shows the spatial frequency characteristic of V-HPF in FIG. FIG. 4 is a timing chart of output signals of respective units of the detection device of FIG. 3 when an original image is input with progressive video data. FIG. 4 is a timing chart of output signals of respective units of the detection device of FIG. 3 when progressive video data obtained by converting an interlace signal into a progressive signal is input. It is a block diagram of an example of the image display apparatus using the image format conversion apparatus of embodiment of this invention. It is a block diagram of an example of the image display apparatus using the conventional image format conversion apparatus. It is a block diagram of an example of the conventional image format conversion apparatus. It is a block diagram of an example of the progressive conversion circuit in FIG. It is operation | movement explanatory drawing of a progressive conversion circuit. It is a figure which shows the spatial frequency characteristic of an interpolation pixel.

Explanation of symbols

11, 131 Progressive signal input terminal 12 A / D converter (ADC)
13 Detector 14 PI converter (progressive-interlace converter)
15 Interlace signal output terminals 21 to 23 1-line delay circuit 24, 25 Vertical high-pass filter (V-HPF)
132 Memory 133, 134 High pass filter (HPF)
135 level comparator 136 integrator 137 discrimination circuit

Claims (2)

The input progressive signal is a converted progressive signal obtained by converting the interlace signal, comprising an interlace signal original line signal and an interpolation line signal obtained by interpolating the original line signal, In addition, it is determined whether the signal of the line constituting the converted progressive signal is the signal of the original line or the signal of the interpolated line, and the high frequency signal in the vertical direction in each of the odd line signal and the even line signal of the converted progressive signal. Detection means for detecting based on the size of the component;
Conversion means for thinning out the signal of the interpolation line from the input progressive signal based on the detection result of the detection means, and converting it to the original interlace signal consisting only of the signal of the original line;
An image format conversion apparatus comprising: The detection means includes
First filter means for extracting a first high-frequency component that is a high-frequency component in a vertical direction in a signal of an odd-numbered line of the input progressive signal;
Second filter means for extracting a second high-frequency component that is a high-frequency component in the vertical direction in the signal of the even-numbered line of the input progressive signal;
When the first high frequency component and the second high frequency component extracted by the first and second filter means are subtracted, and the signal of the odd line is the signal of the original line of the interlace signal Difference signal generating means for generating a difference signal having the other polarity of positive polarity and negative polarity when the signal of the even-numbered line is the signal of the original line of the interlaced signal in one polarity of positive polarity and negative polarity ,
Integrating means for integrating the difference signal for a fixed period;
The signal output from the integrating means is a signal having a level equal to or greater than a positive or negative threshold having the same polarity in one frame period, and a level equal to or greater than the positive or negative threshold having a different polarity every frame period. When the input progressive signal is a signal of the original line, it is determined that the input progressive signal is the converted progressive signal, and the signal of one line having a level equal to or higher than the positive or negative threshold output from the integrating means is the signal of the original line. The image format conversion apparatus according to claim 1, further comprising: a determination unit that determines that

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