JP2002009510A - High frequency circuit and package - Google Patents
High frequency circuit and packageInfo
- Publication number
- JP2002009510A JP2002009510A JP2000192784A JP2000192784A JP2002009510A JP 2002009510 A JP2002009510 A JP 2002009510A JP 2000192784 A JP2000192784 A JP 2000192784A JP 2000192784 A JP2000192784 A JP 2000192784A JP 2002009510 A JP2002009510 A JP 2002009510A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- bonding pad
- wire
- dielectric substrate
- microstrip line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
- H01L2224/49176—Wire connectors having the same loop shape and height
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
Description
【０００１】[0001]
【発明が属する技術分野】この発明は、高周波、特にミ
リ波帯で動作する高周波回路およびパッケージに関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency circuit and a package operating at a high frequency, particularly, a millimeter wave band.
【０００２】[0002]
【従来の技術】図６は、従来の高周波回路の接続部の構
成を示す図である。図において、１は誘電体基板、２は
マイクロストリップ線路、３はワイヤやリボン等の導体
（なおここでは、ワイヤという）である。2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a connection portion of a conventional high-frequency circuit. In the figure, reference numeral 1 denotes a dielectric substrate, 2 denotes a microstrip line, and 3 denotes a conductor such as a wire or a ribbon (hereinafter, referred to as a wire).
【０００３】また、図７は、従来の高周波回路の接続部
の特性を示す図である。図において、曲線aは接続部の
反射特性、曲線bは通過特性である。FIG. 7 is a diagram showing characteristics of a connection portion of a conventional high-frequency circuit. In the figure, a curve a indicates the reflection characteristic of the connection portion, and a curve b indicates the transmission characteristic.
【０００４】次に、従来の高周波回路の接続部の構成及
び特性について説明する。従来の高周波回路の接続部
は、図６に示すように、複数の誘電体基板１上に構成し
たマイクロストリップ線路２の開放端に、1本或いは複
数本のワイヤ３をボンディングすることによって、複数
のマイクロストリップ線路２を接続している。しかし、
このように複数のマイクロストリップ線路２を接続する
多くの場合は、マイクロストリップ線路２の開放端にて
所望の特性インピーダンスを得ており、ワイヤ３の特性
インピーダンスはマイクロストリップ線路２の特性イン
ピーダンスと合致しないことが多い。このため、高周波
回路の接続部における特性は図７のように、低周波では
反射特性（曲線a）、通過特性（曲線b）とも特に問題な
いが、高周波領域、特にミリ波領域では、反射特性、通
過特性ともに劣化する（不整合が発生する）。したがっ
て、接続部による特性劣化による高周波回路の特性劣化
を招き、結果的にシステム性能の劣化を招くという問題
があった。Next, a description will be given of the configuration and characteristics of a connection portion of a conventional high-frequency circuit. As shown in FIG. 6, one or more wires 3 are bonded to the open end of a microstrip line 2 formed on a plurality of dielectric substrates 1 by bonding one or more wires 3 as shown in FIG. Of microstrip lines 2 are connected. But,
In many cases where a plurality of microstrip lines 2 are connected as described above, a desired characteristic impedance is obtained at the open end of the microstrip line 2, and the characteristic impedance of the wire 3 matches the characteristic impedance of the microstrip line 2. Often not. For this reason, as shown in FIG. 7, the characteristics at the connection portion of the high-frequency circuit are not particularly problematic in the reflection characteristics (curve a) and the transmission characteristics (curve b) at low frequencies, but in the high-frequency region, particularly in the millimeter-wave region. , Pass characteristics deteriorate (mismatch occurs). Therefore, there has been a problem that the characteristics of the high-frequency circuit are deteriorated due to the characteristics deterioration due to the connection portion, and as a result, the system performance is deteriorated.
【０００５】このような問題に関し、従来は、例えば特
開2000-165114号公報のように、ワイヤ３が接続される
マイクロストリップ線路２の先端をテーパ状にする等の
対策が取られていた。その内容を以下に示す。In order to deal with such a problem, conventionally, measures such as tapering the tip of the microstrip line 2 to which the wire 3 is connected have been taken as disclosed in Japanese Patent Application Laid-Open No. 2000-165114, for example. The contents are shown below.
【０００６】図８、図９は、特開2000-165114号公報に
示される対策内容である。図において、1は誘電体基
板、２はマイクロストリップ線路、３はワイヤ、曲線c
は接続部の反射特性、曲線dは通過特性である。FIGS. 8 and 9 show the countermeasures described in Japanese Patent Application Laid-Open No. 2000-165114. In the figure, 1 is a dielectric substrate, 2 is a microstrip line, 3 is a wire, curve c
Represents the reflection characteristic of the connection portion, and curve d represents the transmission characteristic.
【０００７】次に、従来の対策による効果を示す。図８
のように、本対策は、ワイヤ３が接続されるマイクロス
トリップ線路２の先端より、誘電体基板1における通過
周波数の３／１０＊実効波長以上のテーパを設けてい
る。これにより、ワイヤ３とマイクロストリップ線路２
における不整合は図９のとおり、若干の改善を見せる。
しかし、この対策では、ワイヤ３の特性インピーダンス
とマイクロストリップ線路２の接続部付近の特性インピ
ーダンスを近づけることは可能であるが、依然、マイク
ロストリップ線路２の接続部以外の箇所、つまり回路全
体から見れば、不整合が生じたままであり、特に、ミリ
波帯等の高周波帯では、この影響が顕著に見られるた
め、他の対策が必要であった。Next, the effects of the conventional measures will be described. FIG.
As described above, in this measure, a taper is provided from the tip of the microstrip line 2 to which the wire 3 is connected, at least 3/10 * the effective wavelength of the pass frequency in the dielectric substrate 1. Thereby, the wire 3 and the microstrip line 2
9 shows a slight improvement as shown in FIG.
However, in this measure, it is possible to make the characteristic impedance of the wire 3 close to the characteristic impedance near the connection portion of the microstrip line 2, but it can still be seen from a portion other than the connection portion of the microstrip line 2, that is, from the entire circuit. For example, the mismatch still occurs. In particular, in a high frequency band such as a millimeter wave band, this effect is remarkably observed, so that other measures are required.
【０００８】[0008]
【発明が解決しようとする課題】上記のように、従来の
高周波回路では、ワイヤの特性インピーダンスを管理し
ていないことが多く、複数の誘電体基板に構成したマイ
クロストリップ線路を接続した場合、その接続部におい
て不整合が発生し、システム性能の劣化を招くという課
題があった。As described above, in the conventional high-frequency circuit, the characteristic impedance of the wire is often not managed, and when a microstrip line configured on a plurality of dielectric substrates is connected, the There is a problem that a mismatch occurs at the connection part, which causes deterioration of system performance.
【０００９】この発明はかかる課題を解決するためにな
されたものであり、複数の誘電体基板に構成したマイク
ロストリップ線路の先端に、幅が誘電体基板における通
過周波数の実効波長以下でのボンディングパッドを配置
し、そのパッド寸法によって、通過周波数におけるワイ
ヤによる不整合を低減する。SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has a bonding pad having a width equal to or less than an effective wavelength of a pass frequency on a dielectric substrate at a tip of a microstrip line formed on a plurality of dielectric substrates. And its pad size reduces wire mismatch at the pass frequency.
【００１０】[0010]
【課題を解決するための手段】第１の発明による高周波
回路は、複数のマイクロストリップ線路を接続するため
のワイヤ等の導体と、このワイヤ等の導体をボンディン
グし、かつ幅が誘電体基板における通過周波数の実効波
長以下のボンディングパッドとを備えたものである。According to a first aspect of the present invention, there is provided a high-frequency circuit comprising: a conductor such as a wire for connecting a plurality of microstrip lines; And a bonding pad having a wavelength equal to or less than the effective wavelength of the pass frequency.
【００１１】また、第２の発明による高周波回路は、上
記ボンディングパッドにおけるインピーダンスにインダ
クタンス成分及び容量成分をもって整合するための整合
回路を上記マイクロストリップ線路の所定位置に設けた
ものである。In the high-frequency circuit according to the second invention, a matching circuit for matching the impedance at the bonding pad with an inductance component and a capacitance component is provided at a predetermined position of the microstrip line.
【００１２】第３の発明による高周波回路は、上記ボン
ディングパッドからの距離が誘電体基板における通過周
波数の実効波長の１／２以下の箇所に、長さが誘電体基
板における通過周波数の実効波長の１／２以下の先端開
放線路あるいは先端短絡線路等の整合回路を設けたもの
である。The high-frequency circuit according to a third aspect of the present invention is the high-frequency circuit, wherein the distance from the bonding pad is equal to or less than half the effective wavelength of the pass frequency on the dielectric substrate, and the length is the effective wavelength of the pass frequency on the dielectric substrate. A matching circuit such as an open-ended line or a short-circuited line of 1/2 or less is provided.
【００１３】また、第４の発明によるパッケージは、誘
電体基板を積層してキャビティを構成し、そのキャビテ
ィに高周波半導体回路を収納し、その高周波半導体回路
とマイクロストリップ線路の接続部に、ワイヤ等の導体
と、このワイヤ等の導体をボンディングし、かつ幅が誘
電体基板における通過周波数の実効波長以下のボンディ
ングパッドとを備えたものである。In the package according to the fourth aspect of the present invention, a dielectric substrate is laminated to form a cavity, a high-frequency semiconductor circuit is housed in the cavity, and a wire or the like is connected to a connection between the high-frequency semiconductor circuit and the microstrip line. And a bonding pad that bonds the conductor such as a wire and has a width equal to or less than the effective wavelength of the pass frequency in the dielectric substrate.
【００１４】[0014]
【発明の実施の形態】実施の形態１．図１は、この発明
の実施の形態１を示す高周波回路の構成図であり、図に
おいて、１は誘電体基板、２はマイクロストリップ線
路、３はワイヤ、４はボンディングパッドである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram of a high-frequency circuit according to a first embodiment of the present invention. In the figure, 1 is a dielectric substrate, 2 is a microstrip line, 3 is a wire, and 4 is a bonding pad.
【００１５】また、図２はこの発明の高周波回路の特性
を示す図である。図において、曲線eは反射特性、曲線f
は通過特性である。FIG. 2 is a diagram showing characteristics of the high-frequency circuit according to the present invention. In the figure, curve e is the reflection characteristic, curve f
Is the pass characteristic.
【００１６】次に、構成について説明する。複数の誘電
体基板１に構成したマイクロストリップ線路２の先端に
ボンディングパッド４を設けており、このボンディング
パッド４上にワイヤ３をボンディングすることにより、
複数の誘電体基板１及びマイクロストリップ線路２を接
続する。このとき、ボンディングパッド４の幅は、マイ
クロストリップ線路２の通過周波数f0における、誘電体
基板１の実効波長以下である。Next, the configuration will be described. A bonding pad 4 is provided at a tip of a microstrip line 2 formed on a plurality of dielectric substrates 1, and a wire 3 is bonded onto the bonding pad 4 to
A plurality of dielectric substrates 1 and microstrip lines 2 are connected. At this time, the width of the bonding pad 4 is equal to or smaller than the effective wavelength of the dielectric substrate 1 at the pass frequency f0 of the microstrip line 2.
【００１７】次に、高周波回路の接続部の特性について
説明する。図２において、曲線eは接続部における反射
特性であり、曲線fは通過特性である。反射特性、通過
特性ともに通過周波数f0において、従来の高周波回路の
特性よりも改善されていることがわかる。これは、ワイ
ヤ３のインダクタンス成分を、ボンディングパッド４の
容量成分によって、通過周波数f0におけるインピーダン
ス整合をとった結果である。この容量成分はボンディン
グパッド４の寸法（幅）によって変えることができ、誘
電体基板の実効波長以下の値で整合をとることが可能で
ある。このように、高周波回路の接続部において、幅寸
法を調整されたボンディングパッドを使用することで、
この接続部の不整合を低減することができ、高周波回路
やシステム性能の劣化を防止できる。Next, the characteristics of the connection portion of the high-frequency circuit will be described. In FIG. 2, a curve e is a reflection characteristic at the connection portion, and a curve f is a pass characteristic. It can be seen that both the reflection characteristics and the pass characteristics are improved at the pass frequency f0 as compared with the characteristics of the conventional high-frequency circuit. This is the result of impedance matching at the pass frequency f0 of the inductance component of the wire 3 by the capacitance component of the bonding pad 4. This capacitance component can be changed depending on the dimension (width) of the bonding pad 4, and matching can be achieved with a value equal to or less than the effective wavelength of the dielectric substrate. In this way, by using the bonding pad whose width has been adjusted in the connection portion of the high-frequency circuit,
This mismatching of the connection can be reduced, and deterioration of the high-frequency circuit and system performance can be prevented.
【００１８】実施の形態２．図３は、この発明の実施の
形態２を示す高周波回路の構成図であり、図において、
１は誘電体基板、２はマイクロストリップ線路、３はワ
イヤ、４はボンディングパッド、５は先端開放線路によ
る整合回路である。Embodiment 2 FIG. FIG. 3 is a configuration diagram of a high-frequency circuit according to Embodiment 2 of the present invention.
1 is a dielectric substrate, 2 is a microstrip line, 3 is a wire, 4 is a bonding pad, and 5 is a matching circuit using an open-ended line.
【００１９】また、図４はこの発明の高周波回路におけ
る、ワイヤ３とボンディングパッド４による接続部の特
性を示す図である。図において、曲線gは反射特性、曲
線hは通過特性である。FIG. 4 is a graph showing the characteristics of the connection between the wire 3 and the bonding pad 4 in the high-frequency circuit according to the present invention. In the figure, a curve g is a reflection characteristic, and a curve h is a transmission characteristic.
【００２０】次に、構成及び特性について説明する。複
数の誘電体基板１に構成したマイクロストリップ線路２
の先端にボンディングパッド４を設け、このボンディン
グパッド３上にワイヤ３をボンディングすることによ
り、複数の誘電体基板１及びマイクロストリップ線路２
を接続する。このとき、ボンディングパッド４の幅は、
マイクロストリップ線路２の通過周波数f0における、誘
電体基板１の実効波長以下である。このように、実施の
形態１と同様に、寸法を調整されたボンディングパッド
４を使用することによって、接続部の不整合を低減でき
る。Next, the configuration and characteristics will be described. Microstrip line 2 formed on a plurality of dielectric substrates 1
A bonding pad 4 is provided at the tip of the substrate, and a wire 3 is bonded on the bonding pad 3 to form a plurality of dielectric substrates 1 and microstrip lines 2.
Connect. At this time, the width of the bonding pad 4 is
It is equal to or less than the effective wavelength of the dielectric substrate 1 at the pass frequency f0 of the microstrip line 2. Thus, as in the first embodiment, by using the bonding pad 4 whose dimensions are adjusted, it is possible to reduce the mismatch of the connection portion.
【００２１】しかし、ワイヤ３が長い場合、ボンディン
グパッド４の寸法を調整しても、図４のように、ワイヤ
３の不整合を大きく低減できない場合がある。これは、
ワイヤ３が長すぎるため、ワイヤ３のインダクタンス成
分を、ボンディングパッド４の容量成分でインピーダン
ス整合がとりきれないためである。このような場合は、
図３のように、ボンディングパッド４からの距離が、マ
イクロストリップ線路２の通過周波数f0における、誘電
体基板１の実効波長＊１／２以下の箇所に、長さがマイ
クロストリップ線路２の通過周波数f0における誘電体基
板１の実効波長＊１／２以下の、先端開放線路あるいは
先端短絡線路等の整合回路を設けることにより、接続部
の不整合を低減できる。However, when the wire 3 is long, even if the dimensions of the bonding pad 4 are adjusted, the mismatch of the wire 3 may not be significantly reduced as shown in FIG. this is,
This is because the impedance of the wire 3 cannot be sufficiently matched with the capacitance of the bonding pad 4 because the wire 3 is too long. In such a case,
As shown in FIG. 3, the distance from the bonding pad 4 to the pass wavelength f0 of the microstrip line 2 is equal to or less than the effective wavelength * 1/2 of the dielectric substrate 1 and the length of the pass frequency of the microstrip line 2. By providing a matching circuit such as an open-ended line or a short-circuited line having an effective wavelength of １ ／ or less of the dielectric substrate 1 at f0, mismatching of the connection portion can be reduced.
【００２２】これは、ボンディングパッド４におけるイ
ンピーダンスにインダクタンス成分及び容量成分をもっ
て再整合するためである。このように、本実施の形態に
よれば、ワイヤ３が長い場合でも、インピーダンス整合
でき、高周波回路及びシステムの特性劣化を防ぐことが
できる。This is because the impedance at the bonding pad 4 is re-matched with an inductance component and a capacitance component. As described above, according to the present embodiment, even when the wire 3 is long, impedance matching can be performed, and deterioration of characteristics of the high-frequency circuit and the system can be prevented.
【００２３】なお、上記整合回路５は、一方の誘電体基
板１に施したマイクロストリップ線路２に設けたが、こ
の整合回路５を他方の誘電体基板１に施したマイクロス
トリップ線路２のみに設けても良いし、また両方のマイ
クロストリップ線路に設けても良い。Although the matching circuit 5 is provided on the microstrip line 2 provided on one dielectric substrate 1, the matching circuit 5 is provided only on the microstrip line 2 provided on the other dielectric substrate 1. Or may be provided on both microstrip lines.
【００２４】実施の形態３．図４は、この発明の実施の
形態３を示すパッケージの構成図であり、図において、
１は誘電体基板、２はマイクロストリップ線路、３はワ
イヤ、４はボンディングパッド、６はベース、７はカバ
ー、８はキャビティ、９は高周波半導体回路である。Embodiment 3 FIG. FIG. 4 is a configuration diagram of a package showing a third embodiment of the present invention.
1 is a dielectric substrate, 2 is a microstrip line, 3 is a wire, 4 is a bonding pad, 6 is a base, 7 is a cover, 8 is a cavity, and 9 is a high-frequency semiconductor circuit.
【００２５】次に、構成及び動作について説明する。本
パッケージは、金属製のベース６の上に複数の誘電体基
板１を積層してキャビティ８を作り、キャビティ８の内
部に高周波半導体回路９を収納し、カバー７にて封止し
ている。このパッケージにおいて、収納された高周波半
導体回路９は、マイクロストリップ線路２とボンディン
グパッド４を介して接続され、動作する。このとき、ボ
ンディングパッド４の幅は、マイクロストリップ線路２
の通過周波数f0における、誘電体基板１の実効波長以下
である。このように、実施の形態１と同様に、寸法を調
整されたボンディングパッド４を使用することによっ
て、接続部の不整合を低減でき、高周波回路を含むパッ
ケージやシステム性能の劣化を防止できる。Next, the configuration and operation will be described. In this package, a plurality of dielectric substrates 1 are stacked on a metal base 6 to form a cavity 8, a high-frequency semiconductor circuit 9 is housed inside the cavity 8, and sealed with a cover 7. In this package, the housed high-frequency semiconductor circuit 9 is connected to the microstrip line 2 via the bonding pad 4 and operates. At this time, the width of the bonding pad 4 is
Is equal to or less than the effective wavelength of the dielectric substrate 1 at the pass frequency f0. Thus, similarly to the first embodiment, by using the bonding pad 4 whose dimensions are adjusted, it is possible to reduce the mismatch of the connection portion, and to prevent the deterioration of the package including the high-frequency circuit and the system performance.
【００２６】[0026]
【発明の効果】第１の発明によれば、複数のマイクロス
トリップ線路を接続するためのワイヤ等の導体と、この
ワイヤ等の導体をボンディングし、かつ幅が誘電体基板
における通過周波数の実効波長以下のボンディングパッ
ドとを備えたことにより、高周波回路やシステム性能の
劣化を防止できる。According to the first invention, a conductor such as a wire for connecting a plurality of microstrip lines is bonded to the conductor such as a wire, and the effective wavelength of the pass frequency in the dielectric substrate is equal to the width of the conductor. The provision of the following bonding pads can prevent high-frequency circuits and system performance from deteriorating.
【００２７】また、第２、第３の発明によれば、整合回
路を備えたことにより、高周波回路やシステム性能の劣
化を防止できる。According to the second and third aspects of the present invention, since the matching circuit is provided, deterioration of the high-frequency circuit and system performance can be prevented.
【００２８】第４の発明によれば、誘電体基板を積層し
てキャビティを構成し、そのキャビティに高周波半導体
回路を収納し、その高周波半導体回路とマイクロストリ
ップ線路の接続部に、ワイヤ等の導体と、このワイヤ等
の導体をボンディングし、かつ幅が誘電体基板における
通過周波数の実効波長以下のボンディングパッドとを備
えたことにより、高周波回路を含むパッケージやシステ
ム性能の劣化を防止できる。According to the fourth invention, a dielectric substrate is laminated to form a cavity, a high-frequency semiconductor circuit is housed in the cavity, and a conductor such as a wire is connected to a connection between the high-frequency semiconductor circuit and the microstrip line. And a bonding pad for bonding a conductor such as a wire and having a width equal to or less than the effective wavelength of the pass frequency of the dielectric substrate, so that the performance of a package including a high-frequency circuit and system performance can be prevented from deteriorating.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 この発明の実施の形態１を示す高周波回路の
構成図である。FIG. 1 is a configuration diagram of a high-frequency circuit according to a first embodiment of the present invention.
【図２】 この発明の実施の形態１を示す高周波回路の
接続部の特性図である。FIG. 2 is a characteristic diagram of a connection portion of the high-frequency circuit according to the first embodiment of the present invention.
【図３】 この発明の実施の形態２を示す高周波回路の
構成図である。FIG. 3 is a configuration diagram of a high-frequency circuit according to a second embodiment of the present invention.
【図４】 この発明の実施の形態２を示す高周波回路の
接続部の特性図である。FIG. 4 is a characteristic diagram of a connection portion of the high-frequency circuit according to the second embodiment of the present invention.
【図５】 この発明の実施の形態３を示すパッケージの
構成図である。FIG. 5 is a configuration diagram of a package according to a third embodiment of the present invention.
【図６】 従来による第１の高周波回路を示す構成図で
ある。FIG. 6 is a configuration diagram showing a conventional first high-frequency circuit.
【図７】 従来による第１の高周波回路の接続部の特性
を示す図である。FIG. 7 is a diagram showing characteristics of a connection portion of a conventional first high-frequency circuit.
【図８】 従来による第２の高周波回路を示す構成図で
ある。FIG. 8 is a configuration diagram showing a second conventional high-frequency circuit.
【図９】 従来による第２の高周波回路の接続部の特性
を示す図である。FIG. 9 is a diagram illustrating characteristics of a connection portion of a second high-frequency circuit according to the related art.
１ 誘電体基板、２ マイクロストリップ線路、３ ワ
イヤ、４ ボンディングパッド、５ 整合回路、６ ベ
ース、７ カバー、８ キャビティ、９ 高周波半導体
回路。1 Dielectric substrate, 2 microstrip line, 3 wires, 4 bonding pads, 5 matching circuit, 6 base, 7 cover, 8 cavity, 9 high frequency semiconductor circuit.
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１３年４月２３日（２００１．４．２
３）[Submission date] April 23, 2001 (2001.4.2
3)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項１[Correction target item name] Claim 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項３[Correction target item name] Claim 3
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【手続補正３】[Procedure amendment 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１０】[0010]
【課題を解決するための手段】第１の発明による高周波
回路は、複数のマイクロストリップ線路を接続するため
のワイヤ等の導体と、このワイヤ等の導体をボンディン
グし、かつ幅が誘電体基板における通過周波数の実効波
長以下で、かつマイクロストリップ線路幅以上のボンデ
ィングパッドとを備えたものである。According to a first aspect of the present invention, there is provided a high-frequency circuit comprising: a conductor such as a wire for connecting a plurality of microstrip lines; And a bonding pad having a width equal to or smaller than the effective wavelength of the pass frequency and equal to or larger than the microstrip line width .
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１２[Correction target item name] 0012
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１２】第３の発明による高周波回路は、上記ボン
ディングパッドからの距離が誘電体基板における通過周
波数の実効波長の１／２以下の箇所に、上記マイクロス
トリップ線路幅のいずれか一方の縁からの長さが上記誘
電体基板における通過周波数の実効波長の１／２以下の
先端開放線路あるいは先端短絡線路等の整合回路を設け
たものである。The high-frequency circuit according to a third aspect of the present invention is the high-frequency circuit, wherein the distance from the bonding pad is less than half the effective wavelength of the pass frequency on the dielectric substrate .
A matching circuit such as an open-end line or a short-circuit line having a length from any one edge of the trip line width equal to or less than １ ／ of the effective wavelength of the pass frequency in the dielectric substrate is provided.
【手続補正５】[Procedure amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００１６】次に、構成について説明する。複数の誘電
体基板１に構成したマイクロストリップ線路２の先端に
ボンディングパッド４を設けており、このボンディング
パッド４上にワイヤ３をボンディングすることにより、
複数の誘電体基板１及びマイクロストリップ線路２を接
続する。このとき、ボンディングパッド４の幅は、マイ
クロストリップ線路２の通過周波数ｆ0における、誘電
体基板１の実効波長以下であり、かつマイクロストリッ
プ線路２の幅以上である。Next, the configuration will be described. A bonding pad 4 is provided at a tip of a microstrip line 2 formed on a plurality of dielectric substrates 1, and a wire 3 is bonded onto the bonding pad 4 to
A plurality of dielectric substrates 1 and microstrip lines 2 are connected. The width of the bonding pad 4, in the pass frequency f0 of the microstrip line 2 is equal to or less than the effective wavelength of the dielectric substrate 1, and the microstrip
The width of the transmission line 2 .
【手続補正６】[Procedure amendment 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２０[Correction target item name] 0020
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２０】次に、構成及び特性について説明する。複
数の誘電体基板１に構成したマイクロストリップ線路２
の先端にボンディングパッド４を設け、このボンディン
グパッド３上にワイヤ３をボンディングすることによ
り、複数の誘電体基板１及びマイクロストリップ線路２
を接続する。このとき、ボンディングパッド４の幅は、
マイクロストリップ線路２の通過周波数ｆ0における、
誘電体基板１の実効波長以下であり、かつマイクロスト
リップ線路２の幅以上である。このように、実施の形態
１と同様に、寸法を調整されたボンディングパッド４を
使用することによって、接続部の不整合を低減できる。Next, the configuration and characteristics will be described. Microstrip line 2 formed on a plurality of dielectric substrates 1
A bonding pad 4 is provided at the tip of the substrate, and a wire 3 is bonded on the bonding pad 3 to form a plurality of dielectric substrates 1 and microstrip lines 2.
Connect. At this time, the width of the bonding pad 4 is
At the pass frequency f0 of the microstrip line 2,
Less than the effective wavelength of the dielectric substrate 1 and
It is not less than the width of the lip line 2 . Thus, as in the first embodiment, by using the bonding pad 4 whose dimensions are adjusted, it is possible to reduce the mismatch of the connection portion.
【手続補正７】[Procedure amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２１[Correction target item name] 0021
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２１】 しかし、ワイヤ３が長い場合、ボンディ
ングパッド４の寸法を調整しても、図４のように、ワイ
ヤ３の不整合を大きく低減できない場合がある。これ
は、ワイヤ３が長すぎるため、ワイヤ３のインダクタン
ス成分を、ボンディングパッド４の容量成分でインピー
ダンス整合がとりきれないためである。このような場合
は、図３のように、ボンディングパッド４からの距離
が、マイクロストリップ線路２の通過周波数f0におけ
る、誘電体基板１の実効波長＊１／２以下の箇所に、マ
イクロストリップ線路２の幅のいずれか一方の縁からの
長さがマイクロストリップ線路２の通過周波数f0におけ
る誘電体基板１の実効波長＊１／２以下の、先端開放線
路あるいは先端短絡線路等の整合回路を設けることによ
り、接続部の不整合を低減できる。However, when the wire 3 is long, even if the dimensions of the bonding pad 4 are adjusted, the mismatch of the wire 3 may not be significantly reduced as shown in FIG. This is because the wire 3 is too long, and the inductance component of the wire 3 cannot be impedance-matched with the capacitance component of the bonding pad 4. In such a case, as shown in FIG. 3, the distance from the bonding pad 4 is set to a value less than the effective wavelength * 1/2 of the dielectric substrate 1 at the pass frequency f0 of the microstrip line 2 .
An open-ended line or a short-circuited line whose width from one edge of the width of the microstrip line 2 is less than or equal to the effective wavelength * 1/2 of the dielectric substrate 1 at the pass frequency f0 of the microstrip line 2. By providing a matching circuit such as a line, it is possible to reduce mismatching of the connection portion.
【手続補正８】[Procedure amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２４[Correction target item name] 0024
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２４】実施の形態３．図５は、この発明の実施の
形態３を示すパッケージの構成図であり、図において、
１は誘電体基板、２はマイクロストリップ線路、３はワ
イヤ、４はボンディングパッド、６はベース、７はカバ
ー、８はキャビティ、９は高周波半導体回路である。Embodiment 3 FIG. FIG. 5 is a configuration diagram of a package showing a third embodiment of the present invention.
1 is a dielectric substrate, 2 is a microstrip line, 3 is a wire, 4 is a bonding pad, 6 is a base, 7 is a cover, 8 is a cavity, and 9 is a high-frequency semiconductor circuit.
【手続補正９】[Procedure amendment 9]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２５[Correction target item name] 0025
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２５】次に、構成及び動作について説明する。本
パッケージは、金属製のベース６の上に複数の誘電体基
板１を積層してキャビティ８を作り、キャビティ８の内
部に高周波半導体回路９を収納し、カバー７にて封止し
ている。このパッケージにおいて、収納された高周波半
導体回路９は、マイクロストリップ線路２とボンディン
グパッド４を介して接続され、動作する。このとき、ボ
ンディングパッド４の幅は、マイクロストリップ線路２
の通過周波数f0における、誘電体基板１の実効波長以下
であり、かつマイクロストリップ線路２の幅以上であ
る。このように、実施の形態１と同様に、寸法を調整さ
れたボンディングパッド４を使用することによって、接
続部の不整合を低減でき、高周波回路を含むパッケージ
やシステム性能の劣化を防止できる。Next, the configuration and operation will be described. In this package, a plurality of dielectric substrates 1 are stacked on a metal base 6 to form a cavity 8, a high-frequency semiconductor circuit 9 is housed inside the cavity 8, and sealed with a cover 7. In this package, the housed high-frequency semiconductor circuit 9 is connected to the microstrip line 2 via the bonding pad 4 and operates. At this time, the width of the bonding pad 4 is
Below the effective wavelength of the dielectric substrate 1 at the pass frequency f0
And not less than the width of the microstrip line 2 . Thus, similarly to the first embodiment, by using the bonding pad 4 whose dimensions are adjusted, it is possible to reduce the mismatch of the connection portion, and to prevent the deterioration of the package including the high-frequency circuit and the system performance.
【手続補正１０】[Procedure amendment 10]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２６[Correction target item name] 0026
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２６】[0026]
【発明の効果】第１の発明によれば、複数のマイクロス
トリップ線路を接続するためのワイヤ等の導体と、この
ワイヤ等の導体をボンディングし、かつ幅が誘電体基板
における通過周波数の実効波長以下であり、かつマイク
ロストリップ線路２の幅以上のボンディングパッドとを
備えたことにより、高周波回路やシステム性能の劣化を
防止できる。According to the first invention, a conductor such as a wire for connecting a plurality of microstrip lines is bonded to the conductor such as a wire, and the effective wavelength of the pass frequency in the dielectric substrate is equal to the width of the conductor. Less than and microphone
By providing a bonding pad having a width equal to or greater than the width of the lossy strip line 2 , deterioration of high-frequency circuits and system performance can be prevented.
【手続補正１１】[Procedure amendment 11]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２８[Correction target item name] 0028
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【００２８】第４の発明によれば、誘電体基板を積層し
てキャビティを構成し、そのキャビティに高周波半導体
回路を収納し、その高周波半導体回路とマイクロストリ
ップ線路の接続部に、ワイヤ等の導体と、このワイヤ等
の導体をボンディングし、かつ幅が誘電体基板における
通過周波数の実効波長以下であり、かつマイクロストリ
ップ線路２の幅以上のボンディングパッドとを備えたこ
とにより、高周波回路を含むパッケージやシステム性能
の劣化を防止できる。According to the fourth invention, a dielectric substrate is laminated to form a cavity, a high-frequency semiconductor circuit is housed in the cavity, and a conductor such as a wire is connected to a connection between the high-frequency semiconductor circuit and the microstrip line. And a conductor such as a wire, the width of which is less than or equal to the effective wavelength of the pass frequency on the dielectric substrate , and
By providing the bonding pad having a width equal to or larger than the width of the gap line 2 , deterioration of a package including a high-frequency circuit and system performance can be prevented.
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｐ 1/04 Ｈ０１Ｐ 1/04 (72)発明者 松尾 浩一 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 Ｆターム(参考） 5F044 EE01 EE02 5J011 DA12 Continued on the front page (51) Int.Cl. 7 Identification FI FI Theme Court II (Reference) H01P 1/04 H01P 1/04 (72) Inventor Koichi Matsuo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In-house F term (reference) 5F044 EE01 EE02 5J011 DA12
Claims (4)
トリップ線路を接続してなる高周波回路において、複数
のマイクロストリップ線路を接続するためのワイヤ等の
導体と、幅が上記誘電体基板における通過周波数の実効
波長以下で上記ワイヤ等の導体をボンディングするため
のボンディングパッドとを具備したことを特徴とする高
周波回路。1. A high-frequency circuit comprising a plurality of microstrip lines connected to a plurality of dielectric substrates, wherein a conductor such as a wire for connecting the plurality of microstrip lines and a pass frequency of the dielectric substrate are provided. And a bonding pad for bonding a conductor such as the above-mentioned wire at an effective wavelength equal to or less than the effective wavelength.
ーダンスにインダクタンス成分及び容量成分をもって整
合するための整合回路を上記マイクロストリップ線路の
所定位置に設けたことを特徴とする請求項１記載の高周
波回路。2. The high-frequency circuit according to claim 1, wherein a matching circuit for matching the impedance at the bonding pad with an inductance component and a capacitance component is provided at a predetermined position of the microstrip line.
記誘電体基板における通過周波数の実効波長の１／２以
下の箇所に、長さが上記誘電体基板における通過周波数
の実効波長の１／２以下の整合回路を具備したことを特
徴とする請求項１又は２記載の高周波回路。3. A location where the distance from the bonding pad is 1/2 or less of the effective wavelength of the pass frequency on the dielectric substrate, and the length is 1/2 or less of the effective wavelength of the pass frequency on the dielectric substrate. 3. The high-frequency circuit according to claim 1, further comprising a matching circuit.
し、そのキャビティに高周波半導体回路を収納するパッ
ケージにおいて、複数のマイクロストリップ線路の接続
部に請求項１〜３いずれかに記載の高周波回路を適用し
たことを特徴とするパッケージ。4. A high-frequency circuit according to claim 1, wherein a cavity is formed by laminating dielectric substrates, and a high-frequency semiconductor circuit is housed in the cavity in a connection portion of a plurality of microstrip lines. A package characterized by applying.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000192784A JP2002009510A (en) | 2000-06-27 | 2000-06-27 | High frequency circuit and package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000192784A JP2002009510A (en) | 2000-06-27 | 2000-06-27 | High frequency circuit and package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002009510A true JP2002009510A (en) | 2002-01-11 |
Family
ID=18691867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000192784A Pending JP2002009510A (en) | 2000-06-27 | 2000-06-27 | High frequency circuit and package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002009510A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004075336A1 (en) * | 2003-02-21 | 2004-09-02 | Matsushita Electric Industrial Co., Ltd. | High frequency circuit |
| JP2011172072A (en) * | 2010-02-19 | 2011-09-01 | Fujitsu Ltd | Transmission line, impedance transformer, integrated circuit mounting device, and communication device module |
| WO2015062067A1 (en) * | 2013-11-01 | 2015-05-07 | Telefonaktiebolaget L M Ericsson (Publ) | Method and arrangement for board-to-board interconnection |
-
2000
- 2000-06-27 JP JP2000192784A patent/JP2002009510A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004075336A1 (en) * | 2003-02-21 | 2004-09-02 | Matsushita Electric Industrial Co., Ltd. | High frequency circuit |
| JP2011172072A (en) * | 2010-02-19 | 2011-09-01 | Fujitsu Ltd | Transmission line, impedance transformer, integrated circuit mounting device, and communication device module |
| US8816793B2 (en) | 2010-02-19 | 2014-08-26 | Fujitsu Limited | Transmission line, impedance transformer, integrated circuit mounted device, and communication device module |
| WO2015062067A1 (en) * | 2013-11-01 | 2015-05-07 | Telefonaktiebolaget L M Ericsson (Publ) | Method and arrangement for board-to-board interconnection |
| US9839118B2 (en) | 2013-11-01 | 2017-12-05 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and arrangement for board-to-board interconnection |
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