JP2002009343A - Semiconductor light emitting device and protector - Google Patents
Semiconductor light emitting device and protectorInfo
- Publication number
- JP2002009343A JP2002009343A JP2000191368A JP2000191368A JP2002009343A JP 2002009343 A JP2002009343 A JP 2002009343A JP 2000191368 A JP2000191368 A JP 2000191368A JP 2000191368 A JP2000191368 A JP 2000191368A JP 2002009343 A JP2002009343 A JP 2002009343A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- semiconductor light
- transistor
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、保護素子を内蔵し
た半導体発光装置及びこれに使用することができる熱破
壊及び過電圧破壊防止用保護装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having a built-in protection element and a protection device for preventing thermal destruction and overvoltage destruction which can be used in the device.
【０００２】[0002]
【従来の技術】近年、窒化ガリウム（GaN）系半導体を
用いた青色半導体発光素子即ち発光ダイオードが注目さ
れている。この発光ダイオードは数十ボルト程度のサー
ジ電圧で破壊するため、例えば、特開平１１−１２０３
６号公報に開示されているように発光ダイオードに並列
に過電圧防止用のツェナダイオード（定電圧ダイオー
ド）が接続される。これにより、静電気等による過電圧
が発光ダイオードに印加された時にツェナダイオードが
導通して発光ダイオードが過電圧から保護される。2. Description of the Related Art In recent years, a blue semiconductor light emitting device using a gallium nitride (GaN) based semiconductor, that is, a light emitting diode, has attracted attention. This light emitting diode is destroyed by a surge voltage of about several tens of volts.
As disclosed in Japanese Patent Laid-Open Publication No. 6-106, a Zener diode (constant voltage diode) for overvoltage prevention is connected in parallel with the light emitting diode. Thus, when an overvoltage due to static electricity or the like is applied to the light emitting diode, the zener diode conducts and the light emitting diode is protected from the overvoltage.
【０００３】[0003]
【発明が解決しようとする課題】ところで、ツェナダイ
オード等の保護素子と発光ダイオードとの組立体を構成
する時には、保護素子の上にマイクロバンプ電極等によ
って発光ダイオードを結合させる。このため、発光ダイ
オードの放熱経路に保護素子が介在し、保護素子が発光
ダイオードの放熱性を低下させる。もし、保護素子を設
けないで発光ダイオードに流す電流と同一の値の電流を
保護素子を設けた発光ダイオードに流すと、発光ダイオ
ードの温度がその許容範囲よりも高くなり、発光ダイオ
ードの劣化又は破損が生じるおそれがある。今、発光ダ
イオードと保護素子を一体的に組み立てる場合について
述べたが、保護素子が発光ダイオードの放熱を妨害しな
い場合であっても、発光ダイオード等の半導体発光素子
の熱破壊は問題になる。また、発光ダイオード以外の回
路素子においても過電圧破壊と熱破壊との両方を防止し
なければならない時がある。When an assembly of a light-emitting diode and a protection element such as a Zener diode is constructed, the light-emitting diode is connected to the protection element by a micro-bump electrode or the like. For this reason, the protection element is interposed in the heat radiation path of the light emitting diode, and the protection element reduces the heat radiation of the light emitting diode. If a current of the same value as the current flowing through the light-emitting diode without the protection element is passed through the light-emitting diode with the protection element, the temperature of the light-emitting diode becomes higher than its allowable range, and the LED is deteriorated or damaged. May occur. Although the case where the light emitting diode and the protection element are assembled integrally has been described above, even when the protection element does not hinder the heat radiation of the light emitting diode, thermal destruction of the semiconductor light emitting element such as the light emitting diode becomes a problem. In some cases, it is necessary to prevent both overvoltage breakdown and thermal breakdown in circuit elements other than light emitting diodes.
【０００４】そこで、本発明の第１の目的は、半導体発
光素子の熱破壊を防ぐことができる半導体発光装置を提
供することにある。本発明の第２の目的は、半導体発光
素子の熱破壊と過電圧破壊との両方を防ぐことができる
半導体発光装置を提供することにある。本発明の第３の
目的は、熱破壊と過電圧破壊との両方を防ぐことができ
る保護装置を提供することにある。[0004] Therefore, a first object of the present invention is to provide a semiconductor light emitting device which can prevent thermal destruction of a semiconductor light emitting element. A second object of the present invention is to provide a semiconductor light emitting device that can prevent both thermal breakdown and overvoltage breakdown of a semiconductor light emitting element. A third object of the present invention is to provide a protection device that can prevent both thermal destruction and overvoltage destruction.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための本発明は、半導体発光素子と、前
記半導体発光素子に並列に接続され且つ前記半導体発光
素子の温度が所定温度よりも高くなった時にオン状態に
なるか又は抵抗値が低下する特性を有している保護素子
とから成る半導体発光装置に係わるものである。SUMMARY OF THE INVENTION In order to solve the above problems and achieve the above object, the present invention provides a semiconductor light emitting device and a semiconductor light emitting device which is connected in parallel to the semiconductor light emitting device and has a predetermined temperature. A semiconductor light emitting device comprising a protection element having a characteristic of turning on or a resistance value decreasing when it becomes higher.
【０００６】なお、請求項２に示すように発光素子に並
列に過電圧防止用定電圧ダイオードを接続することが望
ましい。また、請求項３に示すように発光素子を保護素
子の上に配置することが望ましい。また、請求項４に示
すように保護素子をトランジスタとし、定電圧ダイオー
ドと同一の半導体基体に設けることが望ましい。請求項
５に示すようにトランジスタと定電圧ダイオードとを並
列接続して回路素子のための熱破壊及び過電圧破壊防止
用保護装置を形成することができる。It is desirable to connect a constant voltage diode for preventing overvoltage in parallel with the light emitting element. In addition, it is desirable that the light emitting element is disposed on the protection element. It is desirable that the protection element be a transistor and be provided on the same semiconductor substrate as the constant voltage diode. According to a fifth aspect, a transistor and a constant voltage diode can be connected in parallel to form a protection device for preventing thermal destruction and overvoltage destruction for a circuit element.
【０００７】[0007]
【発明の効果】請求項１〜４の発明によれば、半導体発
光素子の温度が所定温度よりも高くなると、保護素子が
オン又は低抵抗値になり、半導体発光素子のバイパスと
して働き、半導体発光素子の電流が遮断又は抑制され、
半導体発光素子の温度上昇が抑えられ、この劣化又は破
壊が防止される。また、請求項２の発明によれば、熱破
壊防止と過電圧防止との両方を達成することができる。
請求項３の発明によれば、保護素子を有するにも拘らず
比較的小さい発光装置を提供することができる。請求項
４の発明によれば、熱破壊及び過電圧破壊の両方を防ぐ
ことができる発光装置の小型化且つ低コスト化を図るこ
とができる。また、請求項５の発明によれば、発光素子
のみでなくこれ以外の回路素子の熱破壊及び過電圧破壊
を防ぐことができる。According to the first to fourth aspects of the present invention, when the temperature of the semiconductor light emitting element becomes higher than a predetermined temperature, the protection element is turned on or has a low resistance value, and functions as a bypass for the semiconductor light emitting element. The current of the element is interrupted or suppressed,
The temperature rise of the semiconductor light emitting element is suppressed, and this deterioration or destruction is prevented. Further, according to the invention of claim 2, both prevention of thermal destruction and prevention of overvoltage can be achieved.
According to the third aspect of the present invention, it is possible to provide a relatively small light emitting device despite having a protection element. According to the fourth aspect of the invention, it is possible to reduce the size and cost of the light emitting device that can prevent both thermal destruction and overvoltage destruction. According to the fifth aspect of the present invention, not only the light emitting element but also other circuit elements can be prevented from thermal destruction and overvoltage destruction.
【０００８】[0008]
【実施形態】次に、図１〜図８を参照して本発明の実施
形態を説明する。Next, an embodiment of the present invention will be described with reference to FIGS.
【０００９】[0009]
【第１の実施形態】図１〜図５に示す第１の実施形態の
半導体発光装置１は、発光素子としての窒化ガリウム
（GａＮ）系発光ダイオード２と、トランジスタ４と定
電圧ダイオード５とから成る複合保護素子３と、第１及
び第２の主端子６，７と、制御端子８とを有している。First Embodiment A semiconductor light emitting device 1 according to a first embodiment shown in FIGS. 1 to 5 includes a gallium nitride (GaN) based light emitting diode 2 as a light emitting element, a transistor 4 and a constant voltage diode 5. , The first and second main terminals 6 and 7, and the control terminal 8.
【００１０】発光ダイオード２のアノードは第１の主端
子６に接続され、カソードは第２の主端子７に接続され
ている。複合保護素子３に含まれているシリコンから成
るNPN型トランジスタ４は発光ダイオード２に対して並
列に接続されている。即ちトランジスタ４のコレクタは
第１の主端子６に接続され、このエミッタは第２の主端
子７に接続され、ベースは制御端子８に接続されてい
る。また、トランジスタ４は発光ダイオード２に熱結合
されている。このトランジスタ４が導通を開始するため
のベース・エミッタ間電圧ＶBE即ち、ベース電流が流れ
始めるために要求されるベース・エミッタ間電圧ＶBEは
２５℃（室温）で約０．７Ｖである。また、オン開始時
のベース・エミッタ間電圧ＶBEは約‐２ｍＶ／℃の負の
温度係数を有している。本実施形態では負の温度係数を
有するトランジスタ４が感熱素子として利用され、発光
ダイオード２の過熱を防いでいる。The light emitting diode 2 has an anode connected to the first main terminal 6 and a cathode connected to the second main terminal 7. The NPN transistor 4 made of silicon contained in the composite protection element 3 is connected in parallel to the light emitting diode 2. That is, the collector of the transistor 4 is connected to the first main terminal 6, the emitter is connected to the second main terminal 7, and the base is connected to the control terminal 8. Transistor 4 is thermally coupled to light emitting diode 2. The transistor 4 is the voltage V BE between the base and emitter for initiating conduction That is, the voltage V BE between the base and emitter, which is required for the base current starts to flow is about 0.7V at 25 ° C. (room temperature). Further, the base-emitter voltage V BE at the start of turning on has a negative temperature coefficient of about −2 mV / ° C. In this embodiment, the transistor 4 having a negative temperature coefficient is used as a thermal element to prevent the light emitting diode 2 from overheating.
【００１１】電子回路素子としての発光ダイオード２を
駆動する時には第１の主端子６を電流制限用抵抗９を介
して直流電源端子１０に接続し、第２の主端子７をグラ
ンド端子１１に接続する。また、トランジスタ４を発光
ダイオード２の熱破壊防止用保護素子として使用する時
には、トランジスタ４のベース即ち制御端子８にバイア
ス回路１２を接続する。バイアス回路１２は、直流電源
端子１０とグランド端子１１との間に接続された第１及
び第２の抵抗１３，１４から成り、第１及び第２の抵抗
１３，１４の相互接続点が制御端子８に接続されてい
る。本実施例においてはバイアス回路１２によってトラ
ンジスタ４のベース・エミッタ間に与える固定バイアス
電圧Ｖｂは０．５５Ｖに設定されているものとする。こ
のバイアス電圧Vb＝０．５５Vを得るための抵抗１３の
値R1の決定は次式に従って行う。 Vb＝Vcc R２／（R1＋R2） R1＝R2｛（Vcc／Vb）−１｝ なお、抵抗１４として既値の抵抗R2を使用する。このバ
イアス電圧Ｖｂは、発光ダイオード２の通常の温度範囲
ではトランジスタ４がオンにならないが、発光ダイオー
ド２の温度が通常温度範囲よりも高い異常温度（本実施
例では１００℃以上）になるとオンになるように決定さ
れる。この実施形態では、発光ダイオード２の保護開始
温度が１００℃である。もし、発光ダイオード２及びト
ランジスタ４の温度が１００℃になると、トランジスタ
４が導通を開始するために要求されるベース・エミッタ
間電圧ＶBEが２５℃の時の値（０．７Ｖ）よりも０．１
５Ｖ下がり、０．５５Ｖとなる。１００℃の時には、バ
イアス回路１２からは０．５５Ｖのバイアス電圧Ｖｂが
トランジスタ４に印加されているので、トランジスタ４
がオンになり、発光ダイオード２のバイパス即ち短絡回
路が形成され、発光ダイオード２の電流が遮断又は抑制
され、発光ダイオード２の温度上昇が制限される。即
ち、トランジスタ４がオンになると、抵抗９を通る電流
がトランジスタ４に分流し、発光ダイオード２の電流が
低下する。トランジスタ４はシリコンから成り、ＧａＮ
系発光ダイオード２よりは熱破壊しにくい。また、トラ
ンジスタ４は発光ダイオード２の許容最大電流と同一の
値の電流が流れても破壊しないように形成されている。
なお、好ましくは、トランジスタ４の許容最大コレクタ
電流の値を発光ダイオード２の許容最大電流の２倍以上
に決定する。When driving the light emitting diode 2 as an electronic circuit element, the first main terminal 6 is connected to a DC power supply terminal 10 via a current limiting resistor 9 and the second main terminal 7 is connected to a ground terminal 11. I do. When the transistor 4 is used as a protection element for preventing thermal destruction of the light emitting diode 2, a bias circuit 12 is connected to the base of the transistor 4, that is, the control terminal 8. The bias circuit 12 includes first and second resistors 13 and 14 connected between the DC power supply terminal 10 and the ground terminal 11, and an interconnection point between the first and second resistors 13 and 14 is a control terminal. 8 is connected. In this embodiment, it is assumed that the fixed bias voltage Vb applied between the base and the emitter of the transistor 4 by the bias circuit 12 is set to 0.55V. The value R1 of the resistor 13 for obtaining the bias voltage Vb = 0.55V is determined according to the following equation. Vb = Vcc R2 / (R1 + R2) R1 = R2 {(Vcc / Vb) -1} Note that the existing resistor R2 is used as the resistor 14. This bias voltage Vb turns on when the temperature of the light emitting diode 2 reaches an abnormal temperature higher than the normal temperature range (100 ° C. or higher in this embodiment), although the transistor 4 does not turn on in the normal temperature range of the light emitting diode 2. It is determined to be. In this embodiment, the protection start temperature of the light emitting diode 2 is 100 ° C. If the temperature of the light-emitting diode 2 and the transistor 4 becomes 100 ° C., the base-emitter voltage V BE required for the transistor 4 to start conducting becomes lower than the value (0.7 V) at 25 ° C. .1
It drops by 5V to 0.55V. At 100 ° C., since the bias voltage Vb of 0.55 V is applied to the transistor 4 from the bias circuit 12,
Is turned on, a bypass or short circuit of the light emitting diode 2 is formed, the current of the light emitting diode 2 is cut off or suppressed, and the temperature rise of the light emitting diode 2 is limited. That is, when the transistor 4 is turned on, the current passing through the resistor 9 is shunted to the transistor 4, and the current of the light emitting diode 2 decreases. Transistor 4 is made of silicon, GaN
It is less susceptible to thermal destruction than the system light emitting diode 2. The transistor 4 is formed so as not to be destroyed even when a current having the same value as the allowable maximum current of the light emitting diode 2 flows.
Preferably, the value of the maximum allowable collector current of the transistor 4 is determined to be twice or more the maximum allowable current of the light emitting diode 2.
【００１２】定電圧ダイオード５は、発光ダイオード２
の定格電圧では導通しないが、定格電圧と破壊する可能
性のある最低破壊電圧との間の所定電圧で導通し、発光
ダイオード２に一定電圧以上の電圧が印加されることを
防ぐように形成されている。これにより、静電気等の高
いサージ電圧が第１及び第２の主端子６，７間に印加さ
れた時に定電圧ダイオード５が導通し、発光ダイオード
２の両端子間電圧が制限される。The constant voltage diode 5 is a light emitting diode 2
It does not conduct at the rated voltage, but conducts at a predetermined voltage between the rated voltage and the lowest breakdown voltage that may cause destruction, and is formed so as to prevent a voltage higher than a certain voltage from being applied to the light emitting diode 2. ing. Thus, when a high surge voltage such as static electricity is applied between the first and second main terminals 6 and 7, the constant voltage diode 5 conducts, and the voltage between both terminals of the light emitting diode 2 is limited.
【００１３】図２〜図５は発光装置１の各部の構成を詳
しく示すものである。図２に概略的に示すように発光ダ
イオ−ド２は複合保護素子３の上に配置されている。発
光ダイオ−ド２は図２及び図３から明らかなように、G
ａN系半導体発光ダイオ−ドの本体部２０とアノ−ド側
のマイクロバンプ電極２１とカソ−ド側マイクロバンプ
電極２２とから成るフリップチップであって、バンプ電
極２１、２２によって複合保護素子３の上面に機械的及
び電気的に結合されている。なお、発光ダイオ−ド２か
らは主として上方に光が放射される。FIGS. 2 to 5 show the configuration of each part of the light emitting device 1 in detail. As schematically shown in FIG. 2, the light emitting diode 2 is arranged on the composite protection element 3. As apparent from FIGS. 2 and 3, the light emitting diode 2 has G
a flip chip comprising a body 20 of an aN-based semiconductor light-emitting diode, a micro-bump electrode 21 on the anode side, and a micro-bump electrode 22 on the cathode side; It is mechanically and electrically coupled to the upper surface. Light is mainly emitted upward from the light emitting diode 2.
【００１４】複合保護素子３は、トランジスタ４と定電
圧ダイオ−ド５とを図３〜図５に示すように同一のシリ
コン半導体基体２３に形成したものである。図２〜図５
に示すように複合保護素子３の一方の主面には第１の主
電極２４と第２主電極２５の表面側部分２５ａと制御電
極２６が設けられ、他方の主面に第２の主電極２５の裏
面部分２５ｂが設けられている。図２に概略的に示すよ
うに第１の主電極２４はワイヤから成る第１の導体２７
によって柱状リ−ドから成る第１の主端子６に接続され
ている。第２の主電極２５の裏面側部分２５ｂは第２の
主端子７に一体的に形成された光反射凹部を有するヘッ
ダ部７ａにAgペ−スト等の導電性接合材２８によって電
気的及び機械的に結合されている。制御電極２６はワイ
ヤから成る第２の導体２９によって柱状リ−ドから成る
制御端子８に接続されている。発光ダイオ−ド２、複合
保護素子３、端子６、７、８の一部、導体２７、２９は
光透過性樹脂３０によって被覆されている。The composite protection element 3 is such that a transistor 4 and a constant voltage diode 5 are formed on the same silicon semiconductor substrate 23 as shown in FIGS. 2 to 5
As shown in the figure, a first main electrode 24, a surface side portion 25a of a second main electrode 25 and a control electrode 26 are provided on one main surface of the composite protection element 3, and a second main electrode is provided on the other main surface. There are provided 25 back surface portions 25b. As schematically shown in FIG. 2, the first main electrode 24 is a first conductor 27 made of a wire.
Is connected to a first main terminal 6 composed of a columnar lead. The back surface side portion 25b of the second main electrode 25 is electrically and mechanically connected to a header portion 7a having a light reflecting recess formed integrally with the second main terminal 7 by a conductive bonding material 28 such as Ag paste. Are combined. The control electrode 26 is connected to a control terminal 8 composed of a columnar lead by a second conductor 29 composed of a wire. The light emitting diode 2, the composite protective element 3, a part of the terminals 6, 7, 8 and the conductors 27, 29 are covered with a light transmitting resin 30.
【００１５】発光ダイオ−ド２は複合保護素子３の上に
バンプ電極２１、２２を介して結合されているので、発
光ダイオ−ド２の熱は複合保護素子３の中のトランジス
タ４に伝達される。従って、トランジスタ４は発光ダイ
オ−ド２の熱結合された状態にあり、発光ダイオ−ド２
の温度変化に追従してトランジスタ４の温度も変化す
る。トランジスタ４を含む複合保護素子３は第２の主端
子７のヘッダ部７ａに直接的に結合されているので比較
的放熱性が良いが、発光ダイオ−ド２は複合保護素子３
を介してヘッダ部７ａに結合されているので、ヘッダ部
７ａに直接に結合する場合に比べて放熱性が悪い。しか
し、この放熱性の悪さに起因する弊害がトランジスタ４
によって電気回路的に除去されている。Since the light emitting diode 2 is coupled to the composite protection device 3 via the bump electrodes 21 and 22, the heat of the light emitting diode 2 is transmitted to the transistor 4 in the composite protection device 3. You. Therefore, transistor 4 is in a thermally coupled state with light emitting diode 2 and light emitting diode 2
, The temperature of the transistor 4 also changes. Since the composite protection element 3 including the transistor 4 is directly coupled to the header portion 7a of the second main terminal 7, the heat dissipation is relatively good.
Is connected to the header portion 7a through the first portion, so that heat radiation is poor as compared with the case of directly connecting to the header portion 7a. However, the adverse effect due to the poor heat dissipation is the transistor 4
Has been removed in an electrical circuit.
【００１６】複合保護素子３を構成するシリコン半導体
基体２３には、図３〜図５に示すようにP型基板領域３
１、N+型埋め込み領域３２、N型シリコンのエピタキシ
ヤル成長領域から成り且つ領域３２よりも低不純物濃度
のN-型領域３３、P型ベ−ス領域３４、N型エミッタ領域
３５、領域３３よりも不純物濃度が高いN+型コレクタ接
続領域３６、領域３４よりも不純物濃度が高いP+型表裏
接続領域３７が設けられている。As shown in FIGS. 3 to 5, a P-type substrate region 3 is formed on the silicon semiconductor substrate 23 constituting the composite protection element 3.
1. N + -type buried region 32, N − -type region 33, P-type base region 34, N-type emitter region 35, region 33, which is composed of an epitaxial growth region of N-type silicon and has a lower impurity concentration than region 32. An N + -type collector connection region 36 having a higher impurity concentration than the P + -type front and back connection region 37 having a higher impurity concentration than the region 34 is provided.
【００１７】半導体基体２３のP型基板領域３１は基体
２３の下面の全体に露出するように配置されている。N+
型埋め込み領域３２は基板領域３１とN-型領域３３との
間に配置されている。P型ベ−ス領域３４はN-型領域３
３の中に島状に形成されている。N型エミッタ領域３５
はベ−ス領域３４の中に島状に形成されている。N+型の
コレクタ接続領域３６は埋め込み領域３２に対向するよ
うにN-型領域３３の中に島状に形成されている。低抵抗
の表裏接続領域３７は第２の主電極２５の表面側部分２
５ａと裏面側部分２５ｂとを電気的に接続するように配
置されている。The P-type substrate region 31 of the semiconductor substrate 23 is disposed so as to be exposed on the entire lower surface of the substrate 23. N +
The mold buried region 32 is arranged between the substrate region 31 and the N − -type region 33. The P-type base region 34 is the N - type region 3
3 is formed in an island shape. N-type emitter region 35
Are formed in the base region 34 in an island shape. The N + -type collector connection region 36 is formed in the N − -type region 33 in an island shape so as to face the buried region 32. The low-resistance front-back connection region 37 is the front-side portion 2 of the second main electrode 25.
5a and the back surface side portion 25b are arranged so as to be electrically connected.
【００１８】半導体基体２３の表面側の第１の主電極２
４は、N+型のコレクタ接続領域３６にオ−ミック接触し
ている。第２の主電極２５の表面側部分２５ａはP+型表
裏接続領域３７、エミッタ領域３５の上に設けられてい
る。制御電極２６はP型ベ−ス領域３４の上に配置され
ている。図３では省略されているが、半導体基体２３の
表面には絶縁膜３８から形成され、ここに形成された開
口を介して第１の主電極２５の表面側部分２５ａ及び制
御電極２６が半導体基体２３の所定領域に接続されてい
る。また、第１の主電極２４は図５に示すように絶縁膜
２８の上に延在し、発光ダイオ−ド２の接続に利用され
ている。図３で破線で示されている発光ダイオ−ド２０
は、第１の主電極２４と第２の主電極２５の表面側部分
２５ａに対向配置され、図５に示すようにアノ−ド側の
バンプ電極２１が第１の主電極２４に結合され、カソ−
ド側のバンプ電極２２が第２の主電極２５の表面側部分
２５ａに結合されている。尚、電極部分を斜線で示して
いる。First main electrode 2 on the surface side of semiconductor substrate 23
4 is in ohmic contact with the N + type collector connection region 36. The front side portion 25 a of the second main electrode 25 is provided on the P + type front / back connection region 37 and the emitter region 35. The control electrode 26 is arranged on the P-type base region 34. Although not shown in FIG. 3, the surface of the semiconductor substrate 23 is formed of an insulating film 38, and the surface side portion 25a of the first main electrode 25 and the control electrode 26 are formed through the opening formed therein. 23 are connected to predetermined regions. The first main electrode 24 extends on the insulating film 28 as shown in FIG. 5 and is used for connecting the light emitting diode 2. The light emitting diode 20 indicated by a broken line in FIG.
Is disposed so as to face the first main electrode 24 and the surface side portion 25a of the second main electrode 25, and the anode-side bump electrode 21 is coupled to the first main electrode 24 as shown in FIG. Caso
The second bump electrode 22 is coupled to the front surface side portion 25 a of the second main electrode 25. In addition, the electrode part is shown by oblique lines.
【００１９】図４に示すように順次に重なるように配置
されているN型エミッタ領域３５とP型ベ−ス領域３４と
N-型領域３３とN+型埋め込み領域３２とによってNPN型
トランジスタ４が構成され、コレクタとして機能するN+
型埋め込み領域３２がN-型領域３３及びN+型領域３６を
介して第１の主電極２４に接続されている。第１の主電
極２４の一部はトランジスタ４のコレクタ電極として機
能し、第２の主電極２５の表面部分２５aの一部はトラ
ンジスタ４のエミッタ電極として機能し、制御電極２６
はトランジスタ４のベ−ス電極として機能している。As shown in FIG. 4, an N-type emitter region 35 and a P-type base region 34 which are arranged so as to sequentially overlap each other are formed.
N - configured the NPN transistor 4 by -type region 33 and N + -type buried region 32, serves as the collector N +
The buried region 32 is connected to the first main electrode 24 via the N − region 33 and the N + region 36. Part of the first main electrode 24 functions as a collector electrode of the transistor 4, part of the surface portion 25 a of the second main electrode 25 functions as an emitter electrode of the transistor 4, and
Functions as a base electrode of the transistor 4.
【００２０】N+型領域３６の一部は、P+型表裏接続領域
３７の一部と重なっている。従って、N+型領域３６が定
電圧ダイオ−ド５のカソ−ド領域として機能し、P+型表
裏接続領域３７が定電圧ダイオ−ド５のアノ−ド領域と
して機能している。また、第１の主電極２４の一部は定
電圧ダイオ−ド５のカソ−ド電極として機能し、第２の
主電極２５の裏面側領域２５ｂは定電圧ダイオ−ド５の
アノ−ド電極として機能している。A part of the N + type region 36 overlaps a part of the P + type front / back connection region 37. Therefore, the N + type region 36 functions as a cathode region of the constant voltage diode 5, and the P + type front / back connection region 37 functions as an anode region of the constant voltage diode 5. Further, a part of the first main electrode 24 functions as a cathode electrode of the constant voltage diode 5, and the back side region 25b of the second main electrode 25 is an anode electrode of the constant voltage diode 5. Functioning as
【００２１】上述から明らかなように本実施形態は次の
効果を有する。 （１） 発光ダイオ−ド２の温度が所定温度以上になる
と、トランジスタ４がオンになり、発光ダイオ−ド２の
電流が低減又は遮断され、発光ダイオ−ド２の劣化又は
熱破壊が防止される。 （２） 定電圧ダイオ−ド５を発光ダイオ−ド２に並列
に接続したので、過電圧時に定電圧ダイオ−ド５が導通
して発光ダイオ−ド２の電圧がクランプされ、過電圧に
よる劣化又は破壊が防止される。 （３） 熱破壊防止用トランジスタ４と過電圧防止用定
電圧ダイオ−ド５とを同一の半導体基体３に設けて複合
保護素子としたので、この小型化及び低コスト化を達成
することができる。 （４） トランジスタ４と定電圧ダイオ−ド５とから成
る複合保護素子の上に発光ダイオ−ド２を配置したの
で、これ等の組立体を小型化することができる。As apparent from the above, the present embodiment has the following effects. (1) When the temperature of the light emitting diode 2 exceeds a predetermined temperature, the transistor 4 is turned on, the current of the light emitting diode 2 is reduced or cut off, and the deterioration or thermal destruction of the light emitting diode 2 is prevented. You. (2) Since the constant voltage diode 5 is connected in parallel with the light emitting diode 2, the voltage of the light emitting diode 2 is clamped at the time of overvoltage, and the voltage of the light emitting diode 2 is clamped. Is prevented. (3) Since the transistor 4 for preventing thermal destruction and the constant voltage diode 5 for preventing overvoltage are provided on the same semiconductor substrate 3 to form a composite protection element, it is possible to achieve a reduction in size and cost. (4) Since the light-emitting diode 2 is disposed on the composite protection element including the transistor 4 and the constant voltage diode 5, the size of the assembly can be reduced.
【００２２】[0022]
【第２の実施形態】次に、図６及び図７を参照して第２
の実施形態の発光装置１ａを説明する。但し、図６及び
図７、更に後述する図８において図１〜図５と実質的に
同一の部分には同一の符号を付し、その説明を省略す
る。Second Embodiment Next, a second embodiment will be described with reference to FIGS.
The light emitting device 1a according to the embodiment will be described. However, in FIGS. 6 and 7, and in FIG. 8, which will be described later, the same parts as those in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof will be omitted.
【００２３】図６及び図７に示す発光装置１ａは、回路
基板に対して表面実装方式で取り付けるための絶縁性支
持基板４０を設け、この他は図２の発光装置1と実質的
に同一に形成したものである。基板４０には、図2の端
子６、７、8に対応する導体層から成る端子６ａ、７
ａ、８ａが設けられている。図6〜図7の発光ダイオ−ド
２及び複合保護素子３は図２〜図５で同一符号で示すも
のと同様に形成されている。図６及び図７において第２
の主電極の裏面側部分２５ｂは導電性接合材２８ａによ
って基板４０の第２の主端子７ａに電気的及び機械的に
結合されている。第１の主電極２４は導体２７によって
第１の主端子６ａに接続され、制御端子２６は導体２９
によって制御端子８ａに接続されている。基板４０の上
面には発光ダイオード２及び複合保護素子３を覆うよう
に光透過性樹脂３０が設けられている。The light emitting device 1a shown in FIGS. 6 and 7 is provided with an insulating support substrate 40 for mounting on a circuit board by a surface mounting method. It is formed. Terminals 6a, 7 made of a conductor layer corresponding to terminals 6, 7, 8 in FIG.
a and 8a are provided. The light emitting diode 2 and the composite protection element 3 in FIGS. 6 to 7 are formed in the same manner as those shown in FIGS. 6 and FIG.
The back side portion 25b of the main electrode is electrically and mechanically coupled to the second main terminal 7a of the substrate 40 by a conductive bonding material 28a. The first main electrode 24 is connected to the first main terminal 6a by a conductor 27, and the control terminal 26 is connected to a conductor 29
Connected to the control terminal 8a. A light transmitting resin 30 is provided on the upper surface of the substrate 40 so as to cover the light emitting diode 2 and the composite protection element 3.
【００２４】第２の実施形態の発光装置は、第１の実施
形態と同一の効果を有し、更に表面実装できるという効
果も有する。The light emitting device according to the second embodiment has the same effect as the first embodiment, and also has the effect that it can be surface-mounted.
【００２５】[0025]
【第３の実施形態】図８に示す第３の実施形態の発光装
置１ｂは、図１と同様に互いに並列に接続された発光ダ
イオ−ド２と定電圧ダイオ−ド５を有する他に、感熱素
子４ａを有する。感熱素子４ａは発光ダイオ−ド２に熱
結合されたサ−ミスタであって、例えば約１００℃以上
の異常温度で抵抗値が大幅に低下するように形成されて
いる。従って、図８の実施形態によっても発光ダイオ−
ドの熱破壊及び過電圧破壊を防止することができる。Third Embodiment A light emitting device 1b according to a third embodiment shown in FIG. 8 has a light emitting diode 2 and a constant voltage diode 5 connected in parallel to each other as in FIG. It has a thermal element 4a. The thermosensitive element 4a is a thermistor thermally coupled to the light emitting diode 2, and is formed such that the resistance value is significantly reduced at an abnormal temperature of, for example, about 100 ° C. or more. Therefore, the light emitting diode is also provided by the embodiment of FIG.
Can be prevented from thermal destruction and overvoltage destruction.
【００２６】[0026]
【変形例】本発明は上述の実施形態に限定されるもので
なく、例えば、次の変形が可能なものである。 （１） バイアス回路１２を発光ダイオ−ド２と別の電
源に接続することができる。 （２） シリコン基板の上にGaN系半導体層を成長さ
せ、GaN系半導体層によって発光ダイオ−ド２を形成
し、シリコン基板にトランジスタ４及び定電圧ダイオ−
ド５を設けることができる。 （３） 複合保護素子３を発光ダイオ−ド２以外の電子
回路素子に並列に接続し、電子回路素子の熱破壊及び過
電圧破壊を防止することができる。[Modifications] The present invention is not limited to the above-described embodiment. For example, the following modifications are possible. (1) The bias circuit 12 can be connected to the light emitting diode 2 and another power supply. (2) A GaN-based semiconductor layer is grown on a silicon substrate, a light emitting diode 2 is formed by the GaN-based semiconductor layer, and a transistor 4 and a constant voltage diode are formed on the silicon substrate.
5 can be provided. (3) The composite protection element 3 can be connected in parallel to electronic circuit elements other than the light emitting diode 2 to prevent thermal destruction and overvoltage destruction of the electronic circuit element.
【図１】本発明の第１の実施形態の発光装置をバイアス
回路及び駆動回路を伴って示す回路図である。FIG. 1 is a circuit diagram showing a light emitting device according to a first embodiment of the present invention together with a bias circuit and a drive circuit.
【図２】図１の発光装置を概略的に示す一部切断正面図
である。FIG. 2 is a partially cutaway front view schematically showing the light emitting device of FIG. 1;
【図３】図２の複合保護素子を、絶縁膜を省いて示す平
面図である。FIG. 3 is a plan view showing the composite protection element of FIG. 2 without an insulating film.
【図４】図３のA−Ａ線を示す断面図である。FIG. 4 is a sectional view taken along line AA of FIG. 3;
【図５】図３のＢ−Ｂ線を示す断面図である。FIG. 5 is a sectional view taken along line BB of FIG. 3;
【図６】第２の実施形態の発光装置を示す正面図であ
る。FIG. 6 is a front view illustrating a light emitting device according to a second embodiment.
【図７】図６の発光装置を被覆樹脂を省いて示す平面図
である。FIG. 7 is a plan view showing the light emitting device of FIG. 6 without a coating resin.
【図８】第３の実施形態の発光装置を示す回路図であ
る。FIG. 8 is a circuit diagram illustrating a light emitting device according to a third embodiment.
１ 発光装置 ２ 発光ダイオ−ド ３ 複合保護素子 ４ 過熱防止用トランジスタ ５ 過電圧防止用定電圧ダイオ−ド DESCRIPTION OF SYMBOLS 1 Light emitting device 2 Light emitting diode 3 Composite protection element 4 Transistor for overheating prevention 5 Constant voltage diode for overvoltage prevention
Claims (5)
に並列に接続され且つ前記半導体発光素子の温度が所定
温度よりも高くなった時にオン状態になるか又は抵抗値
が低下する特性を有している保護素子とから成る半導体
発光装置。1. A semiconductor light emitting device, comprising: a semiconductor light emitting device, which is connected in parallel with the semiconductor light emitting device and has a characteristic that when the temperature of the semiconductor light emitting device becomes higher than a predetermined temperature, the semiconductor light emitting device is turned on or its resistance value is reduced Semiconductor light-emitting device comprising a protective element.
された過電圧防止用定電圧ダイオードを有していること
を特徴とする請求項１記載の半導体発光装置。2. The semiconductor light emitting device according to claim 1, further comprising an overvoltage preventing constant voltage diode connected in parallel to said semiconductor light emitting element.
に配置されていることを特徴とする請求項１又は２記載
の半導体発光装置。3. The semiconductor light emitting device according to claim 1, wherein said semiconductor light emitting element is disposed on said protection element.
ース・エミッタ間電圧が負の温度係数を有するトランジ
スタであり、前記トランジスタと前記定電圧ダイオード
は同一の半導体基体に形成されており、前記半導体発光
素子は前記半導体基体の上に配置されていることを特徴
とする請求項２記載の半導体発光装置。4. The protection element is a transistor whose base-emitter voltage required for starting conduction has a negative temperature coefficient, wherein the transistor and the constant voltage diode are formed on the same semiconductor substrate. 3. The semiconductor light emitting device according to claim 2, wherein a semiconductor light emitting element is disposed on said semiconductor base.
間電圧が負の温度係数を有するトランジスタと、前記ト
ランジスタのコレクタとエミッタとの間に接続された定
電圧ダイオードとから成る熱破壊及び過電圧破壊防止用
保護装置。5. A thermal breakdown and an overvoltage breakdown comprising a transistor having a negative temperature coefficient for a base-emitter voltage required for starting conduction and a constant voltage diode connected between the collector and the emitter of the transistor. Protection device for prevention.
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|---|---|---|---|
| JP2000191368A JP3613328B2 (en) | 2000-06-26 | 2000-06-26 | Semiconductor light emitting device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000191368A JP3613328B2 (en) | 2000-06-26 | 2000-06-26 | Semiconductor light emitting device |
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| Publication Number | Publication Date |
|---|---|
| JP2002009343A true JP2002009343A (en) | 2002-01-11 |
| JP3613328B2 JP3613328B2 (en) | 2005-01-26 |
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ID=18690677
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000191368A Expired - Fee Related JP3613328B2 (en) | 2000-06-26 | 2000-06-26 | Semiconductor light emitting device |
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