JP2001519956A - アドレスされた構成部分の思索の失敗を検出するメモリ・コントローラ - Google Patents
アドレスされた構成部分の思索の失敗を検出するメモリ・コントローラInfo
- Publication number
- JP2001519956A JP2001519956A JP51207399A JP51207399A JP2001519956A JP 2001519956 A JP2001519956 A JP 2001519956A JP 51207399 A JP51207399 A JP 51207399A JP 51207399 A JP51207399 A JP 51207399A JP 2001519956 A JP2001519956 A JP 2001519956A
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Classifications
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.コンピュータにおいてメモリへのアクセスを制御するシステムであって、 命令のアドレスが、メモリまたはメモリ・マップI/Oデバイスのどちらに向 けられたものかを示すハードウエア手段と、 前記アドレスがメモリまたはI/Oであることを思索する命令を起動するソフ トウエア手段と、 前記命令に関して行った前記思索を、前記ハードウエア手段の指示と比較する 手段と、 比較が、前記思索および前記指示が異なることを示した場合、補正処置を取る 手段と、 を備えることを特徴とするシステム。 2.請求項1記載のメモリへのアクセスを制御するシステムにおいて、前記ハー ドウエア手段が、 仮想アドレスおよび関連する物理アドレスに対する複数の格納ロケーションを 含むルック・アサイド・バッファと、 前記変換ルック・アサイド・バッファの各格納ロケーションにおける格納位置 と、 を備えることを特徴とするシステム。 3.請求項1記載のメモリへのアクセスを制御するシステムにおいて、前記アド レスがメモリまたはI/Oであることを思索する命令を起動する前記ソフトウエ ア手段が、ターゲット・プロセッサに対する1組の命令から変換された、ホスト ・プロセッサに対する1組の命令であり、前記1組の命令が、当該命令によって 用いられる各アドレスに対する思索の指示を含むことを特徴とするシステム。 4.請求項1記載のメモリへのアクセスを制御するシステムにおいて、前記ハー ドウエア手段が、 仮想アドレスおよび関連する物理アドレスに対する複数の格納ロケーションを 含むルック・アサイド・バッファと、 前記変換ルック・アサイド・バッファの各格納ロケーションにおける格納位置 と、 を備え、 前記アドレスがメモリまたはI/Oであることを思索する命令を起動する前記 ソフトウエア手段が、ターゲット・プロセッサに対する1組の命令から変換され た、ホスト・プロセッサに対する1組の命令であり、前記1組の命令が、当該命 令によって用いられる各アドレスに対する思索の指示を含む、 ことを特徴とするシステム。 5.請求項4記載のメモリへのアクセスを制御するシステムにおいて、前記命令 に関して行った前記思索を、前記ハードウエア手段の指示と比較する前記手段が 、各アドレスに対する思索の指示を、一致するアドレスを格納する格納ロケーシ ョンにおける記憶位置の状態と比較するハードウエア比較器を備えることを特徴 とするシステム。 6.マイクロプロセッサ用メモリ・コントローラであって、 アドレスされるメモリの本質に関する思索の失敗を双方共検出する手段と、 かかる失敗から復元する手段と、 を備えることを特徴とするメモリ・コントローラ。 7.請求項6記載のメモリ・コントローラにおいて、アドレスされるメモリの本 質に関する思索の失敗を検出する前記手段が、 アドレスされる物理メモリの本質の指示を格納するハードウエア手段と、 前記アドレスされるメモリの本質の思索を、前記ハードウエア手段によって格 納された、前記アドレスされる物理メモリの本質の指示と比較する手段と、 を備えることを特徴とするメモリ・コントローラ。 8.請求項7記載のメモリ・コントローラにおいて、かかる失敗から復元する前 記手段が、 前記アドレスされるメモリの本質の思索を、前記アドレスされる物理メモリの 本質の指示と比較する前記手段による比較の失敗に応答し、例外を発生する手段 と、 前記例外に応答する手段と、 を備えることを特徴とするメモリ・コントローラ。 9.請求項6記載のメモリ・コントローラにおいて、アドレスされるメモリの本 質に関する思索の失敗を検出する前記手段が、 前記アドレスされる物理メモリの本質の指示を格納するハードウエア手段と、 前記アドレスされるメモリの本質に関する思索、および前記ハードウエア手段 によって格納された、前記アドレスされる物理メモリの本質の指示を比較する手 段と、 を備え、 かかる失敗から復元する前記手段が、 前記アドレスされるメモリの本質の思索を、前記アドレスされる物理メモリの 本質の指示と比較する前記手段による比較の失敗に応答し、例外を発生する手段 と、 前記例外に応答する手段と、 を備えることを特徴とするメモリ・コントローラ。 10.請求項9記載のメモリ・コントローラにおいて、前記例外に応答する前記 手段が、 前記マイクロプロセッサを利用するコンピュータの状熊を復元する手段と、 前記アドレスされるメモリの本質が前記思索とは異なると推定し、前記アドレ スにアクセスする手段と、 を備えることを特徴とするメモリ・コントローラ。 11.請求項9記載のメモリ・コントローラにおいて、かかる失敗から復元する 前記手段が、 前記アドレスされるメモリの本質に関する思索の失敗に応答して、例外を発生 する手段と、 前記アドレスされるメモリの本質に関する思索の失敗に関係する例外から復元 するためのプロセスを与える手段と、 を備えることを特徴とするメモリ・コントローラ。 12.コンピュータ用メモリ制御システムであって、 主メモリと、 メモリ・マップ入出力(I/O)デバイスと、 コマンドに、特定のアドレスにおける動作に影響を与えさせるメモリ制御ソフ トウエアと、 最近アクセスされた仮想アドレスと、これら仮想アドレスの前記コンピュータ 内部における物理アドレスへの変換とを格納するメモリ・ロケーションを含む変 換ルックアサイド・バッファと、 前記アドレスがメモリまたはメモリ・マップI/Oのどちらであると仮定した かに関する指示を記録する、各メモリ・ロケーション毎の少なくとも1つのメモ リ位置と、 を備えることを特徴とするコンピュータ用メモリ制御システム。 13.請求項12記載のメモリ制御システムであって、更に、前記変換ルックア サイド・バッファに格納されている仮想アドレスにアクセスする命令が、前記物 理アドレスが当該物理アドレスに対して記録された指示と同一であると推定する か否かを検出する比較器を備えることを特徴とするメモリ制御システム。 14.コンピュータ・システム内のメモリとしてアクセスされる構成部分の特性 に関して失敗した思索から復元する方法であって、 メモリとしてアクセスされる構成部分の特性が存在しないことに関する例外か ら復元するプロセスを与えるステップと、 あるアドレスに対するアクセスを発生し、特定のアドレスの特性に関して思索 するステップと、 前記思索を前記アドレスされる構成部分の特性と比較することによって、前記 思索の失敗を検出するステップと、 前記プロセスを走らせることによって、前記思索の失敗の検出に応答するステ ップと、 から成ることを特徴とする方法。 15.請求項14記載の失敗した思索から復元する方法において、前記思索の失 敗を検出する前記ステップが、前記思索の失敗に応答して例外を発生するステッ プを含むことを特徴とする方法。 16.請求項14記載の失敗した思索から復元する方法において、メモリとして アクセスされる構成部分の特性が存在しないことに関する例外から復元するプロ セスを与える前記ステップが、 前記思索以前に存在していた前記コンピュータ・システムの状熊の指示を格納 する、復元用例外ハンドラを格納するステップと、 前記思索以前に存在していた前記コンピュータの状熊の指示を格納するステッ プと、 を含み、 前記プロセスを走らせることによって、前記思索の失敗の検出に応答する前記 ステップが、 前記格納した状熊の指示を復元するステップと、 前記復元した状熊を利用し、前記失敗した思索が行われた地点から、前記コン ピュータの動作を継続するステップと、 を含むことを特徴とする方法。 17.マイクロプロセッサであって、 第1命令セットを実行可能なホスト・プロセッサと、 第2の異なる命令セットを有するターゲット・プロセッサに対して書かれたプ ログラムを、前記第1命令セットの命令に変換するコード・モーフィング・ソフ トウエアと、 メモリ・コントローラと、 を備え、前記メモリ・コントローラが、 最近アクセスされた仮想ターゲット・アドレスと、該仮想ターゲット・アドレ スによって表わされる物理アドレスとを記録する、複数の格納ロケーションを含 むアドレス変換バッファと、 前記格納ロケーションの各々が、物理アドレスがメモリ・アドレスまたはメモ リ・マップ入出力(I/O)アドレスのどちらであるかを示す手段を含み、 格納ロケーションにおける指示を、格納位置における仮想ターゲット・アドレ スへのアクセスがメモリまたはメモリ・マップI/Oのどちらに対するものであ るかについて行われた思索と比較し、前記アドレスにアクセスする際に行うべき 後続の動作を示す手段と、 を備えることを特徴とするマイクロプロセッサ。 18.請求項17記載のマイクロプロセッサにおいて、格納ロケーションにおけ る指示を、格納位置における仮想ターゲット・アドレスへのアクセスがメモリま たはメモリ・マップI/Oのどちらに対するものであるかについて行われた思索 と比較し、前記アドレスにアクセスする際に行うべき後続の動作を示す前記手段 が、 比較の失敗に応答して例外を発生する手段と、 前記例外に応答し、前記アドレスにアクセスする際に行うべき後続の動作を示 す手段と、 を備えることを特徴とするマイクロプロセッサ。 19.請求項18記載のマイクロプロセッサにおいて、物理アドレスがメモリ・ アドレスまたはメモリ・マップ入出力(I/O)アドレスのどちらであるかを示 す前記手段が、格納ロケーションにおける格納位置を備えることを特徴とするマ イクロプロセッサ。 20.メモリ・コントローラであって、 最近アクセスされた仮想ターゲット・アドレスと、該仮想ターゲット・アドレ スによって表わされる物理アドレスとを記録する、複数の格納ロケーションを含 むアドレス変換バッファと、 前記格納ロケーションの各々が、物理アドレスがメモリ・アドレスまたはメモ リ・マップ入出力(I/O)アドレスのどちらであるかを示す手段を含み、 格納ロケーションにおける指示を、格納位置におけるアドレスへのアクセスが メモリまたはメモリ・マップI/Oのどちらにに対するものであるかについて行 われた思索と比較し、前記アドレスにアクセスする際に行うべき後続の動作を示 す手段と、 を備えることを特徴とするメモリ・コントローラ。 21.請求項20記載のメモリ・コントローラにおいて、格納ロケーションにお ける指示を、格納位置における仮想ターゲット・アドレスへのアクセスがメモリ またはメモリ・マップI/Oのどちらにに対するものであるかについて行われた 思索と比較し、前記アドレスにアクセスする際に行うべき後続の動作を示す前記 手段が、 比較の失敗に応答して例外を発生する手段と、 前記例外に応答し、前記アドレスにアクセスする際に行うべき後続の動作を示 す手段と、 を備えることを特徴とするメモリ・コントローラ。 22.請求項20記載のメモリ・コントローラにおいて、物理アドレスがメモリ ・アドレスまたはメモリ・マップ入出力(I/O)アドレスのどちらであるかを 示す前記手段が、格納ロケーションにおける格納位置を備えることを特徴とする メモリ・コントローラ。
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PCT/US1997/014118 WO1999008188A1 (en) | 1996-08-20 | 1997-08-11 | A memory controller for detecting a failure of speculation of a component being addressed |
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JP (1) | JP3615770B2 (ja) |
KR (1) | KR100463810B1 (ja) |
CN (1) | CN1161691C (ja) |
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Families Citing this family (144)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5493687A (en) | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
US5961629A (en) * | 1991-07-08 | 1999-10-05 | Seiko Epson Corporation | High performance, superscalar-based computer system with out-of-order instruction execution |
ATE200357T1 (de) | 1991-07-08 | 2001-04-15 | Seiko Epson Corp | Risc-prozessor mit dehnbarer architektur |
US5539911A (en) * | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
WO1993020505A2 (en) | 1992-03-31 | 1993-10-14 | Seiko Epson Corporation | Superscalar risc instruction scheduling |
JP3637920B2 (ja) | 1992-05-01 | 2005-04-13 | セイコーエプソン株式会社 | スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法 |
US6735685B1 (en) | 1992-09-29 | 2004-05-11 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
KR100248903B1 (ko) | 1992-09-29 | 2000-03-15 | 야스카와 히데아키 | 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템 |
DE69330889T2 (de) | 1992-12-31 | 2002-03-28 | Seiko Epson Corp | System und Verfahren zur Änderung der Namen von Registern |
US5628021A (en) | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
US6199152B1 (en) * | 1996-08-22 | 2001-03-06 | Transmeta Corporation | Translated memory protection apparatus for an advanced microprocessor |
US6117187A (en) * | 1997-09-30 | 2000-09-12 | Hewlett-Packard Company | Automatic generation of a software installation package |
US6370632B1 (en) | 1997-11-18 | 2002-04-09 | Intrinsity, Inc. | Method and apparatus that enforces a regional memory model in hierarchical memory systems |
US6260131B1 (en) | 1997-11-18 | 2001-07-10 | Intrinsity, Inc. | Method and apparatus for TLB memory ordering |
US6397242B1 (en) | 1998-05-15 | 2002-05-28 | Vmware, Inc. | Virtualization system including a virtual machine monitor for a computer with a segmented architecture |
US6496847B1 (en) | 1998-05-15 | 2002-12-17 | Vmware, Inc. | System and method for virtualizing computer systems |
US6205537B1 (en) | 1998-07-16 | 2001-03-20 | University Of Rochester | Mechanism for dynamically adapting the complexity of a microprocessor |
US6704925B1 (en) | 1998-09-10 | 2004-03-09 | Vmware, Inc. | Dynamic binary translator with a system and method for updating and maintaining coherency of a translation cache |
US8631066B2 (en) * | 1998-09-10 | 2014-01-14 | Vmware, Inc. | Mechanism for providing virtual machines for use by multiple users |
US6308318B2 (en) * | 1998-10-07 | 2001-10-23 | Hewlett-Packard Company | Method and apparatus for handling asynchronous exceptions in a dynamic translation system |
ATE293808T1 (de) * | 1998-10-10 | 2005-05-15 | Transitive Ltd | Programm-kode-umwandlung |
US7516453B1 (en) * | 1998-10-26 | 2009-04-07 | Vmware, Inc. | Binary translator with precise exception synchronization mechanism |
JP3583937B2 (ja) * | 1998-12-28 | 2004-11-04 | 富士通株式会社 | 情報処理装置 |
US6311326B1 (en) * | 1999-01-04 | 2001-10-30 | Emc Corporation | Online debugging and tracing system and method |
US8074055B1 (en) | 1999-01-28 | 2011-12-06 | Ati Technologies Ulc | Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code |
US7941647B2 (en) | 1999-01-28 | 2011-05-10 | Ati Technologies Ulc | Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination |
US8127121B2 (en) | 1999-01-28 | 2012-02-28 | Ati Technologies Ulc | Apparatus for executing programs for a first computer architechture on a computer of a second architechture |
EP1151374B1 (en) * | 1999-01-28 | 2017-08-02 | Advanced Silicon Technologies, LLC | Executing programs for a first computer architecture on a computer of a second architecture |
US6763452B1 (en) | 1999-01-28 | 2004-07-13 | Ati International Srl | Modifying program execution based on profiling |
US7013456B1 (en) | 1999-01-28 | 2006-03-14 | Ati International Srl | Profiling execution of computer programs |
US7275246B1 (en) | 1999-01-28 | 2007-09-25 | Ati International Srl | Executing programs for a first computer architecture on a computer of a second architecture |
US7111290B1 (en) * | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
US8065504B2 (en) | 1999-01-28 | 2011-11-22 | Ati International Srl | Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor |
US7065633B1 (en) | 1999-01-28 | 2006-06-20 | Ati International Srl | System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU |
US6978462B1 (en) | 1999-01-28 | 2005-12-20 | Ati International Srl | Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled |
US6954923B1 (en) | 1999-01-28 | 2005-10-11 | Ati International Srl | Recording classification of instructions executed by a computer |
US6662354B1 (en) | 1999-01-29 | 2003-12-09 | Unisys Corporation | Determining destinations of a dynamic branch |
US7065750B2 (en) * | 1999-02-17 | 2006-06-20 | Elbrus International | Method and apparatus for preserving precise exceptions in binary translated code |
US6397267B1 (en) * | 1999-03-04 | 2002-05-28 | Sun Microsystems, Inc. | Redirected I/O for scalable performance storage architecture |
US7058932B1 (en) | 1999-04-19 | 2006-06-06 | Unisys Corporation | System, computer program product, and methods for emulation of computer programs |
US6725189B2 (en) * | 1999-04-22 | 2004-04-20 | Unisys Corporation | Adapter for coupling a legacy operating system to a driver of an I/O channel which has an incompatible native operating system interface |
US7353163B2 (en) * | 1999-04-27 | 2008-04-01 | Transitive Limited | Exception handling method and apparatus for use in program code conversion |
GB2349486B (en) * | 1999-04-27 | 2001-05-30 | Univ Manchester | Exception handling in program code conversion. |
DE69938621D1 (de) * | 1999-05-03 | 2008-06-12 | St Microelectronics Sa | Befehlausgabe in einem Rechner |
US6779107B1 (en) | 1999-05-28 | 2004-08-17 | Ati International Srl | Computer execution by opportunistic adaptation |
US6442664B1 (en) * | 1999-06-01 | 2002-08-27 | International Business Machines Corporation | Computer memory address translation system |
US7634635B1 (en) | 1999-06-14 | 2009-12-15 | Brian Holscher | Systems and methods for reordering processor instructions |
US7089404B1 (en) * | 1999-06-14 | 2006-08-08 | Transmeta Corporation | Method and apparatus for enhancing scheduling in an advanced microprocessor |
US6549959B1 (en) | 1999-08-30 | 2003-04-15 | Ati International Srl | Detecting modification to computer memory by a DMA device |
US6714904B1 (en) * | 1999-10-13 | 2004-03-30 | Transmeta Corporation | System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions |
US7761857B1 (en) | 1999-10-13 | 2010-07-20 | Robert Bedichek | Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts |
US6880152B1 (en) * | 1999-10-13 | 2005-04-12 | Transmeta Corporation | Method of determining a mode of code generation |
US6363336B1 (en) * | 1999-10-13 | 2002-03-26 | Transmeta Corporation | Fine grain translation discrimination |
JP5220974B2 (ja) | 1999-10-14 | 2013-06-26 | ブルアーク ユーケー リミテッド | ハードウェア実行又はオペレーティングシステム機能の加速のための装置及び方法 |
US6748589B1 (en) | 1999-10-20 | 2004-06-08 | Transmeta Corporation | Method for increasing the speed of speculative execution |
US6751583B1 (en) | 1999-10-29 | 2004-06-15 | Vast Systems Technology Corporation | Hardware and software co-simulation including simulating a target processor using binary translation |
US6594750B1 (en) * | 1999-12-08 | 2003-07-15 | Ati International Srl | Method and apparatus for handling an accessed bit in a page table entry |
US6845353B1 (en) | 1999-12-23 | 2005-01-18 | Transmeta Corporation | Interpage prologue to protect virtual address mappings |
JP2001195250A (ja) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 命令トランスレータ、トランスレータ付命令メモリおよびそれらを用いたデータ処理装置 |
US7100061B2 (en) | 2000-01-18 | 2006-08-29 | Transmeta Corporation | Adaptive power control |
US6934832B1 (en) | 2000-01-18 | 2005-08-23 | Ati International Srl | Exception mechanism for a computer |
US7085914B1 (en) | 2000-01-27 | 2006-08-01 | International Business Machines Corporation | Methods for renaming stack references to processor registers |
US7036106B1 (en) | 2000-02-17 | 2006-04-25 | Tensilica, Inc. | Automated processor generation system for designing a configurable processor and method for the same |
US6763327B1 (en) * | 2000-02-17 | 2004-07-13 | Tensilica, Inc. | Abstraction of configurable processor functionality for operating systems portability |
US6594821B1 (en) * | 2000-03-30 | 2003-07-15 | Transmeta Corporation | Translation consistency checking for modified target instructions by comparing to original copy |
US6349361B1 (en) | 2000-03-31 | 2002-02-19 | International Business Machines Corporation | Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system |
US6968469B1 (en) | 2000-06-16 | 2005-11-22 | Transmeta Corporation | System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored |
US6615300B1 (en) | 2000-06-19 | 2003-09-02 | Transmeta Corporation | Fast look-up of indirect branch destination in a dynamic translation system |
US6826682B1 (en) | 2000-06-26 | 2004-11-30 | Transmeta Corporation | Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state |
US7389208B1 (en) | 2000-06-30 | 2008-06-17 | Accord Solutions, Inc. | System and method for dynamic knowledge construction |
US7260731B1 (en) | 2000-10-23 | 2007-08-21 | Transmeta Corporation | Saving power when in or transitioning to a static mode of a processor |
US6772372B2 (en) * | 2001-03-06 | 2004-08-03 | Hewlett-Packard Development Company, L.P. | System and method for monitoring unaligned memory accesses |
US6775823B2 (en) * | 2001-03-07 | 2004-08-10 | Palmsource, Inc. | Method and system for on-line submission and debug of software code for a portable computer system or electronic device |
JP3610915B2 (ja) * | 2001-03-19 | 2005-01-19 | 株式会社デンソー | 処理実行装置及びプログラム |
US7013460B2 (en) * | 2001-05-15 | 2006-03-14 | Hewlett-Packard Development Company, L.P. | Specifying an invariant property (range of addresses) in the annotation in source code of the computer program |
US7266811B2 (en) * | 2001-09-05 | 2007-09-04 | Conexant Systems, Inc. | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor |
US7251594B2 (en) * | 2001-12-21 | 2007-07-31 | Hitachi, Ltd. | Execution time modification of instruction emulation parameters |
JP4374834B2 (ja) * | 2002-08-12 | 2009-12-02 | セイコーエプソン株式会社 | カートリッジおよび記録装置 |
US7496494B2 (en) * | 2002-09-17 | 2009-02-24 | International Business Machines Corporation | Method and system for multiprocessor emulation on a multiprocessor host system |
US8108843B2 (en) | 2002-09-17 | 2012-01-31 | International Business Machines Corporation | Hybrid mechanism for more efficient emulation and method therefor |
US9043194B2 (en) * | 2002-09-17 | 2015-05-26 | International Business Machines Corporation | Method and system for efficient emulation of multiprocessor memory consistency |
US7146607B2 (en) * | 2002-09-17 | 2006-12-05 | International Business Machines Corporation | Method and system for transparent dynamic optimization in a multiprocessing environment |
US7953588B2 (en) * | 2002-09-17 | 2011-05-31 | International Business Machines Corporation | Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host |
US7457822B1 (en) | 2002-11-01 | 2008-11-25 | Bluearc Uk Limited | Apparatus and method for hardware-based file system |
US8041735B1 (en) | 2002-11-01 | 2011-10-18 | Bluearc Uk Limited | Distributed file system and method |
US20040122800A1 (en) * | 2002-12-23 | 2004-06-24 | Nair Sreekumar R. | Method and apparatus for hardware assisted control redirection of original computer code to transformed code |
US7024537B2 (en) * | 2003-01-21 | 2006-04-04 | Advanced Micro Devices, Inc. | Data speculation based on addressing patterns identifying dual-purpose register |
US7310723B1 (en) | 2003-04-02 | 2007-12-18 | Transmeta Corporation | Methods and systems employing a flag for deferring exception handling to a commit or rollback point |
JP2005032018A (ja) * | 2003-07-04 | 2005-02-03 | Semiconductor Energy Lab Co Ltd | 遺伝的アルゴリズムを用いたマイクロプロセッサ |
US7698539B1 (en) * | 2003-07-16 | 2010-04-13 | Banning John P | System and method of instruction modification |
US7606997B1 (en) | 2003-07-18 | 2009-10-20 | Guillermo Rozas | Method and system for using one or more address bits and an instruction to increase an instruction set |
US8220058B2 (en) | 2003-09-25 | 2012-07-10 | Oracle America, Inc. | Rendering and encryption engine for application program obfuscation |
US7415618B2 (en) | 2003-09-25 | 2008-08-19 | Sun Microsystems, Inc. | Permutation of opcode values for application program obfuscation |
US7424620B2 (en) | 2003-09-25 | 2008-09-09 | Sun Microsystems, Inc. | Interleaved data and instruction streams for application program obfuscation |
US7363620B2 (en) | 2003-09-25 | 2008-04-22 | Sun Microsystems, Inc. | Non-linear execution of application program instructions for application program obfuscation |
US7353499B2 (en) | 2003-09-25 | 2008-04-01 | Sun Microsystems, Inc. | Multiple instruction dispatch tables for application program obfuscation |
US20050165837A1 (en) * | 2004-01-22 | 2005-07-28 | International Business Machines Corporation | System and method for embedded java memory footprint performance improvement |
US7383461B2 (en) * | 2004-02-12 | 2008-06-03 | International Business Machines Corporation | Method and system to recover a failed flash of a blade service processor in a server chassis |
US20050183077A1 (en) * | 2004-02-12 | 2005-08-18 | International Business Machines Corporation | System and method for JIT memory footprint improvement for embedded java devices |
US7734797B2 (en) * | 2004-03-29 | 2010-06-08 | Marvell International Ltd. | Inter-processor communication link with manageability port |
US7225297B2 (en) * | 2004-05-28 | 2007-05-29 | International Business Machines Corporation | Compressed cache lines incorporating embedded prefetch history data |
US7237085B2 (en) * | 2004-05-28 | 2007-06-26 | Oracle International Corporation | Architecture for a scalable heap analysis tool |
US7278014B2 (en) * | 2004-12-02 | 2007-10-02 | International Business Machines Corporation | System and method for simulating hardware interrupts |
GB2425372B (en) * | 2005-04-20 | 2007-06-13 | Transitive Ltd | Method and apparatus for precise handling of exceptions during program code conversion |
US8413162B1 (en) | 2005-06-28 | 2013-04-02 | Guillermo J. Rozas | Multi-threading based on rollback |
EP1752874A1 (en) * | 2005-07-19 | 2007-02-14 | Alcatel | Adaptive evolutionary computer software product |
US7684973B2 (en) * | 2005-12-29 | 2010-03-23 | Bull Hn Information Systems Inc. | Performance improvement for software emulation of central processor unit utilizing signal handler |
US9658849B2 (en) * | 2006-07-06 | 2017-05-23 | Imperas Software Ltd. | Processor simulation environment |
JP5226328B2 (ja) * | 2007-03-27 | 2013-07-03 | パナソニック株式会社 | コード変換装置 |
US8266387B2 (en) * | 2007-06-27 | 2012-09-11 | Microsoft Corporation | Leveraging transactional memory hardware to accelerate virtualization emulation |
US9043553B2 (en) * | 2007-06-27 | 2015-05-26 | Microsoft Technology Licensing, Llc | Leveraging transactional memory hardware to accelerate virtualization and emulation |
US8176253B2 (en) * | 2007-06-27 | 2012-05-08 | Microsoft Corporation | Leveraging transactional memory hardware to accelerate virtualization and emulation |
US8078854B2 (en) * | 2008-12-12 | 2011-12-13 | Oracle America, Inc. | Using register rename maps to facilitate precise exception semantics |
US20100153776A1 (en) * | 2008-12-12 | 2010-06-17 | Sun Microsystems, Inc. | Using safepoints to provide precise exception semantics for a virtual machine |
US8959277B2 (en) * | 2008-12-12 | 2015-02-17 | Oracle America, Inc. | Facilitating gated stores without data bypass |
US20100162045A1 (en) * | 2008-12-22 | 2010-06-24 | Russ Craig F | Method, apparatus and system for restarting an emulated mainframe iop |
US9069918B2 (en) * | 2009-06-12 | 2015-06-30 | Cadence Design Systems, Inc. | System and method implementing full-rate writes for simulation acceleration |
US8392694B2 (en) * | 2009-09-15 | 2013-03-05 | International Business Machines Corporation | System and method for software initiated checkpoint operations |
US9317288B2 (en) | 2011-04-07 | 2016-04-19 | Via Technologies, Inc. | Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
EP2631786B1 (en) | 2011-04-07 | 2018-06-06 | VIA Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
US9274795B2 (en) | 2011-04-07 | 2016-03-01 | Via Technologies, Inc. | Conditional non-branch instruction prediction |
US8880851B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US9244686B2 (en) | 2011-04-07 | 2016-01-26 | Via Technologies, Inc. | Microprocessor that translates conditional load/store instructions into variable number of microinstructions |
US9378019B2 (en) | 2011-04-07 | 2016-06-28 | Via Technologies, Inc. | Conditional load instructions in an out-of-order execution microprocessor |
US9898291B2 (en) | 2011-04-07 | 2018-02-20 | Via Technologies, Inc. | Microprocessor with arm and X86 instruction length decoders |
US8924695B2 (en) | 2011-04-07 | 2014-12-30 | Via Technologies, Inc. | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor |
CN103765400B (zh) | 2011-04-07 | 2016-05-04 | 威盛电子股份有限公司 | 一种乱序执行微处理器中的有条件存储指令 |
US9032189B2 (en) | 2011-04-07 | 2015-05-12 | Via Technologies, Inc. | Efficient conditional ALU instruction in read-port limited register file microprocessor |
US9146742B2 (en) | 2011-04-07 | 2015-09-29 | Via Technologies, Inc. | Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA |
US9336180B2 (en) | 2011-04-07 | 2016-05-10 | Via Technologies, Inc. | Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode |
US8880857B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US9176733B2 (en) | 2011-04-07 | 2015-11-03 | Via Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
EP2508979B1 (en) | 2011-04-07 | 2018-10-10 | VIA Technologies, Inc. | Efficient conditional alu instruction in read-port limited register file microprocessor |
US9043580B2 (en) | 2011-04-07 | 2015-05-26 | Via Technologies, Inc. | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) |
US9141389B2 (en) | 2011-04-07 | 2015-09-22 | Via Technologies, Inc. | Heterogeneous ISA microprocessor with shared hardware ISA registers |
US9292470B2 (en) | 2011-04-07 | 2016-03-22 | Via Technologies, Inc. | Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program |
US9645822B2 (en) | 2011-04-07 | 2017-05-09 | Via Technologies, Inc | Conditional store instructions in an out-of-order execution microprocessor |
US9128701B2 (en) | 2011-04-07 | 2015-09-08 | Via Technologies, Inc. | Generating constant for microinstructions from modified immediate field during instruction translation |
EP2704001B1 (en) | 2012-08-31 | 2016-10-19 | VIA Technologies, Inc. | Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode |
EP3179363B1 (en) | 2012-08-31 | 2019-04-24 | VIA Technologies, Inc. | Microprocessor that enables arm isa program to access general purpose registers written by x86 isa program |
US9250900B1 (en) | 2014-10-01 | 2016-02-02 | Cadence Design Systems, Inc. | Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network |
US20180101384A1 (en) * | 2015-04-17 | 2018-04-12 | Hewlett Packard Enterprise Development Lp | Morphed instruction according to configuration update |
CN110297455B (zh) * | 2018-03-23 | 2022-08-12 | 欧姆龙(上海)有限公司 | 可编程逻辑控制器及其自检和恢复方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61166653A (ja) * | 1985-01-19 | 1986-07-28 | Panafacom Ltd | アドレス変換エラー処理方法 |
JP2589713B2 (ja) * | 1987-11-20 | 1997-03-12 | 株式会社日立製作所 | データプロセッサ及びデータ処理システム |
US5142672A (en) * | 1987-12-15 | 1992-08-25 | Advanced Micro Devices, Inc. | Data transfer controller incorporating direct memory access channels and address mapped input/output windows |
GB2260004B (en) * | 1991-09-30 | 1995-02-08 | Apple Computer | Memory management unit for a computer system |
US5465337A (en) * | 1992-08-13 | 1995-11-07 | Sun Microsystems, Inc. | Method and apparatus for a memory management unit supporting multiple page sizes |
US5442766A (en) * | 1992-10-09 | 1995-08-15 | International Business Machines Corporation | Method and system for distributed instruction address translation in a multiscalar data processing system |
IE940855A1 (en) * | 1993-12-20 | 1995-06-28 | Motorola Inc | Data processor with speculative instruction fetching and¹method of operation |
US5561814A (en) * | 1993-12-22 | 1996-10-01 | Intel Corporation | Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges |
US5526510A (en) * | 1994-02-28 | 1996-06-11 | Intel Corporation | Method and apparatus for implementing a single clock cycle line replacement in a data cache unit |
US5566298A (en) * | 1994-03-01 | 1996-10-15 | Intel Corporation | Method for state recovery during assist and restart in a decoder having an alias mechanism |
US5613083A (en) * | 1994-09-30 | 1997-03-18 | Intel Corporation | Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions |
US5564111A (en) * | 1994-09-30 | 1996-10-08 | Intel Corporation | Method and apparatus for implementing a non-blocking translation lookaside buffer |
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JP3615770B2 (ja) | 2005-02-02 |
CN1161691C (zh) | 2004-08-11 |
CA2283559C (en) | 2004-05-25 |
EP1002271A4 (en) | 2002-09-25 |
US5832205A (en) | 1998-11-03 |
WO1999008188A1 (en) | 1999-02-18 |
EP1002271A1 (en) | 2000-05-24 |
CN1265204A (zh) | 2000-08-30 |
DE69739078D1 (de) | 2008-12-11 |
ATE412940T1 (de) | 2008-11-15 |
CA2283559A1 (en) | 1999-02-18 |
KR100463810B1 (ko) | 2004-12-29 |
KR20010014095A (ko) | 2001-02-26 |
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