JP2001506781A - ビデオフレームレンダリングエンジン - Google Patents
ビデオフレームレンダリングエンジンInfo
- Publication number
- JP2001506781A JP2001506781A JP52299998A JP52299998A JP2001506781A JP 2001506781 A JP2001506781 A JP 2001506781A JP 52299998 A JP52299998 A JP 52299998A JP 52299998 A JP52299998 A JP 52299998A JP 2001506781 A JP2001506781 A JP 2001506781A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- memory
- data
- interface
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.作動中にはメモリーと共に作動する集積回路において、前記メモリーに連結 されていて、前記メモリーへのアクセスを制御するように構成されているイン タフェース回路と、前記インタフェース回路にそこからの情報を受け取るため 連結されていて、前記インタフェース回路を制御するように構成されている埋 め込みプロセッサと、前記インタフェース回路にそこからの情報を受け取るた め連結されている、算術計算を実行するためのアレイプロセッサとから成るこ とを特徴とする集積回路。 2.前記アレイプロセッサが、複数の乗算/累算器と、前記複数の乗算/累算器 の内少なくとも2つに、共有されたオペランドを供給するために連結されてい る共有オペランド回路とから成ることを特徴とする、上記請求項1に記載の集 積回路。 3.前記インタフェース回路が、幅広いアクセスを提供するためのワイヤ束を含 んでいることを特徴とする、上記請求項1に記載の集積回路。 4.前記ワイヤ束が、少なくとも256本のワイヤから成ることを特徴とする、 上記請求項3に記載の集積回路。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3347696P | 1996-12-19 | 1996-12-19 | |
US60/033,476 | 1996-12-19 | ||
US5039697P | 1997-06-20 | 1997-06-20 | |
US60/050,396 | 1997-06-20 | ||
PCT/US1997/023849 WO1998028695A1 (en) | 1996-12-19 | 1997-12-18 | Video frame rendering engine |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001506781A true JP2001506781A (ja) | 2001-05-22 |
JP4235987B2 JP4235987B2 (ja) | 2009-03-11 |
Family
ID=26709753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52299998A Expired - Lifetime JP4235987B2 (ja) | 1996-12-19 | 1997-12-18 | ビデオフレームレンダリングエンジン |
Country Status (6)
Country | Link |
---|---|
US (1) | US6854003B2 (ja) |
JP (1) | JP4235987B2 (ja) |
KR (1) | KR100366689B1 (ja) |
DE (2) | DE19782200B4 (ja) |
GB (1) | GB2335127B (ja) |
WO (1) | WO1998028695A1 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004280623A (ja) * | 2003-03-18 | 2004-10-07 | Renesas Technology Corp | セキュリティシステム |
US7353362B2 (en) | 2003-07-25 | 2008-04-01 | International Business Machines Corporation | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus |
US7412588B2 (en) | 2003-07-25 | 2008-08-12 | International Business Machines Corporation | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus |
JP2010244584A (ja) * | 2010-08-04 | 2010-10-28 | Renesas Electronics Corp | 半導体装置、バスインターフェース装置、およびコンピュータシステム |
JP2012119012A (ja) * | 2012-02-17 | 2012-06-21 | Renesas Electronics Corp | プロセッサ、バスインターフェース装置、およびコンピュータシステム |
KR101511273B1 (ko) | 2008-12-29 | 2015-04-10 | 삼성전자주식회사 | 멀티 코어 프로세서를 이용한 3차원 그래픽 렌더링 방법 및시스템 |
JP2021100428A (ja) * | 2008-11-12 | 2021-07-08 | プロキドニー | 単離した腎細胞およびその使用 |
Families Citing this family (36)
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US6646639B1 (en) | 1998-07-22 | 2003-11-11 | Nvidia Corporation | Modified method and apparatus for improved occlusion culling in graphics systems |
US6480205B1 (en) | 1998-07-22 | 2002-11-12 | Nvidia Corporation | Method and apparatus for occlusion culling in graphics systems |
DE69813912T2 (de) * | 1998-10-26 | 2004-05-06 | Stmicroelectronics Asia Pacific Pte Ltd. | Digitaler audiokodierer mit verschiedenen genauigkeiten |
US7111155B1 (en) | 1999-05-12 | 2006-09-19 | Analog Devices, Inc. | Digital signal processor computation core with input operand selection from operand bus for dual operations |
US7107302B1 (en) | 1999-05-12 | 2006-09-12 | Analog Devices, Inc. | Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units |
US6859872B1 (en) | 1999-05-12 | 2005-02-22 | Analog Devices, Inc. | Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation |
US6820189B1 (en) | 1999-05-12 | 2004-11-16 | Analog Devices, Inc. | Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation |
US6417851B1 (en) | 1999-12-06 | 2002-07-09 | Nvidia Corporation | Method and apparatus for lighting module in a graphics processor |
US6573900B1 (en) | 1999-12-06 | 2003-06-03 | Nvidia Corporation | Method, apparatus and article of manufacture for a sequencer in a transform/lighting module capable of processing multiple independent execution threads |
US6452595B1 (en) | 1999-12-06 | 2002-09-17 | Nvidia Corporation | Integrated graphics processing unit with antialiasing |
US6765575B1 (en) | 1999-12-06 | 2004-07-20 | Nvidia Corporation | Clip-less rasterization using line equation-based traversal |
US6198488B1 (en) | 1999-12-06 | 2001-03-06 | Nvidia | Transform, lighting and rasterization system embodied on a single semiconductor platform |
US6844880B1 (en) | 1999-12-06 | 2005-01-18 | Nvidia Corporation | System, method and computer program product for an improved programmable vertex processing model with instruction set |
US6515671B1 (en) | 1999-12-06 | 2003-02-04 | Nvidia Corporation | Method, apparatus and article of manufacture for a vertex attribute buffer in a graphics processor |
US6870540B1 (en) | 1999-12-06 | 2005-03-22 | Nvidia Corporation | System, method and computer program product for a programmable pixel processing model with instruction set |
US6504542B1 (en) | 1999-12-06 | 2003-01-07 | Nvidia Corporation | Method, apparatus and article of manufacture for area rasterization using sense points |
US6650325B1 (en) | 1999-12-06 | 2003-11-18 | Nvidia Corporation | Method, apparatus and article of manufacture for boustrophedonic rasterization |
US6353439B1 (en) | 1999-12-06 | 2002-03-05 | Nvidia Corporation | System, method and computer program product for a blending operation in a transform module of a computer graphics pipeline |
US7209140B1 (en) | 1999-12-06 | 2007-04-24 | Nvidia Corporation | System, method and article of manufacture for a programmable vertex processing model with instruction set |
US6593923B1 (en) | 2000-05-31 | 2003-07-15 | Nvidia Corporation | System, method and article of manufacture for shadow mapping |
US6806886B1 (en) | 2000-05-31 | 2004-10-19 | Nvidia Corporation | System, method and article of manufacture for converting color data into floating point numbers in a computer graphics pipeline |
US20020008704A1 (en) * | 2000-07-21 | 2002-01-24 | Sheasby Michael C. | Interactive behavioral authoring of deterministic animation |
US8930844B2 (en) * | 2000-08-22 | 2015-01-06 | Bruce Carlin | Network repository of digitalized 3D object models, and networked generation of photorealistic images based upon these models |
US6597356B1 (en) | 2000-08-31 | 2003-07-22 | Nvidia Corporation | Integrated tessellator in a graphics processing unit |
US6697064B1 (en) | 2001-06-08 | 2004-02-24 | Nvidia Corporation | System, method and computer program product for matrix tracking during vertex processing in a graphics pipeline |
US7456838B1 (en) | 2001-06-08 | 2008-11-25 | Nvidia Corporation | System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipeline |
WO2002101497A2 (en) | 2001-06-08 | 2002-12-19 | Nvidia Corporation | System, method and computer program product for programmable fragment processing in a graphics pipeline |
US7162716B2 (en) | 2001-06-08 | 2007-01-09 | Nvidia Corporation | Software emulator for optimizing application-programmable vertex processing |
US7006101B1 (en) | 2001-06-08 | 2006-02-28 | Nvidia Corporation | Graphics API with branching capabilities |
KR100648293B1 (ko) * | 2005-08-09 | 2006-11-23 | 삼성전자주식회사 | 그래픽 시스템 및 그것의 그래픽 처리 방법 |
KR100835173B1 (ko) * | 2006-09-20 | 2008-06-05 | 한국전자통신연구원 | 곱셈 누적 연산을 위한 디지털 신호처리 장치 및 방법 |
ATE480060T1 (de) * | 2007-04-20 | 2010-09-15 | Nethawk Oyj | Verfahren, vorrichtung, testgerät und programm zum testen von multimediakommunikationsgeräten und -software |
US8515052B2 (en) * | 2007-12-17 | 2013-08-20 | Wai Wu | Parallel signal processing system and method |
US7724165B2 (en) * | 2008-07-17 | 2010-05-25 | Faraday Technology Corp. | Audio codec and built-in self test method for the same |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
US9411726B2 (en) * | 2014-09-30 | 2016-08-09 | Samsung Electronics Co., Ltd. | Low power computation architecture |
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-
1997
- 1997-12-18 DE DE19782200A patent/DE19782200B4/de not_active Expired - Lifetime
- 1997-12-18 WO PCT/US1997/023849 patent/WO1998028695A1/en not_active Application Discontinuation
- 1997-12-18 DE DE19782200T patent/DE19782200T1/de active Pending
- 1997-12-18 JP JP52299998A patent/JP4235987B2/ja not_active Expired - Lifetime
- 1997-12-18 US US08/993,442 patent/US6854003B2/en not_active Expired - Lifetime
- 1997-12-18 KR KR10-1999-7005593A patent/KR100366689B1/ko not_active IP Right Cessation
- 1997-12-18 GB GB9914054A patent/GB2335127B/en not_active Expired - Fee Related
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004280623A (ja) * | 2003-03-18 | 2004-10-07 | Renesas Technology Corp | セキュリティシステム |
US7353362B2 (en) | 2003-07-25 | 2008-04-01 | International Business Machines Corporation | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus |
US7412588B2 (en) | 2003-07-25 | 2008-08-12 | International Business Machines Corporation | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus |
US7917729B2 (en) | 2003-07-25 | 2011-03-29 | International Business Machines Corporation | System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus |
US8036243B2 (en) | 2003-07-25 | 2011-10-11 | International Business Machines Corporation | Single chip protocol converter |
US8811422B2 (en) | 2003-07-25 | 2014-08-19 | Microsoft Corporation | Single chip protocol converter |
JP2021100428A (ja) * | 2008-11-12 | 2021-07-08 | プロキドニー | 単離した腎細胞およびその使用 |
KR101511273B1 (ko) | 2008-12-29 | 2015-04-10 | 삼성전자주식회사 | 멀티 코어 프로세서를 이용한 3차원 그래픽 렌더링 방법 및시스템 |
JP2010244584A (ja) * | 2010-08-04 | 2010-10-28 | Renesas Electronics Corp | 半導体装置、バスインターフェース装置、およびコンピュータシステム |
JP2012119012A (ja) * | 2012-02-17 | 2012-06-21 | Renesas Electronics Corp | プロセッサ、バスインターフェース装置、およびコンピュータシステム |
Also Published As
Publication number | Publication date |
---|---|
WO1998028695A1 (en) | 1998-07-02 |
GB2335127A (en) | 1999-09-08 |
KR100366689B1 (ko) | 2003-01-06 |
US6854003B2 (en) | 2005-02-08 |
DE19782200T1 (de) | 1999-11-18 |
GB2335127B (en) | 2002-02-13 |
KR20000062253A (ko) | 2000-10-25 |
JP4235987B2 (ja) | 2009-03-11 |
US20020002574A1 (en) | 2002-01-03 |
GB9914054D0 (en) | 1999-08-18 |
DE19782200B4 (de) | 2011-06-16 |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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