JP2001358536A - Full-wave rectification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a full-wave rectification circuit by which the linearity of output amplitude to input amplitude is improved. SOLUTION: The full-wave rectification circuit has the first and second differential input terminals 1, 2, to which a signal is input, the first and second differential N-P-N transistors 4, 5 in which the input terminals 1, 2 are connected to bases, respectively, a current source 8 connected to emitters for the N-P-N transistors 4, 5 in which the emitters are connected mutually, and the first and second transconductors 6, 7 for adjusting a current flowing through the N-P-N transistors 4, 5 changed at the level of the input signal. The current flowing through the N-P-N transistors 4, 5 is made constant by the input signal, and voltage between the base and the emitter is not changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full-wave rectifier circuit for full-wave rectifying an input signal using an analog integrated circuit, and more particularly to a full-wave rectifier circuit having a good linearity of an output amplitude with respect to an input amplitude. .

[0002]

2. Description of the Related Art A conventional full-wave rectifier circuit will be described with reference to the drawings.

As shown in FIG. 8, a conventional full-wave rectifier circuit has a positive first differential input terminal 1 and a negative second differential input terminal to which a differential AC signal V _IN is input. 2 are provided. The first differential input terminal 1 is connected to the base of the first differential NPN transistor 4, and the second differential input terminal 2
Is connected to the base of the second differential NPN transistor 5. The first and second differential NPN transistors 4 and 5 have their collectors connected in common and connected to a power supply VCC, and their emitters connected in common and connected to a ground GND via a current source 8. And the first and second
An output terminal 3 for outputting a full-wave rectified signal is provided to the commonly connected emitters of the differential NPN transistors 4 and 5.

The operation of the conventional full-wave rectifier circuit configured as described above will be described below.

First, first and second differential input terminals 1 and 2
2, a differential AC signal V _IN is input, and depending on the input level of the differential AC signal V _IN , a state in which both the first and second differential NPN transistors 4 and 5 operate or a state in which either one operates. Exists. Therefore, current is supplied to the current source 8 by the first or second differential NPN transistors 4 and 5 operating from the power supply VCC. here,
The emitter voltages of the first and second transistors 4 and 5, that is, the output voltage V _OUT are expressed as follows.

Assuming that the current flowing through the transistor 4 is I _PO , the current flowing through the transistor 5 is I _NO , and the current flowing through the current source 8 is 2I, the currents I _PO and I _NO are respectively

[0007]

## EQU1 ## I _PO = 2I · [1-1 / ｛1 + exp (V _IN ·
q / k · T)｝]

[0008]

## EQU2 ## I _NO = 2I / {1 + exp (V _IN · q / k · T)} Here, T = 273 + t (absolute temperature), k =
1.38 × 10 ^-23 (Boltzmann constant), q = 1.6 ×
10 ⁻¹⁹ (electron charge amount), t is a temperature expressed in degrees Celsius.

Next, the emitter voltage of the first and second transistors 4 and 5, that is, the output voltage V _OUT is

[0010]

(Equation 3) It is represented by However, I _S is the saturation current of the transistors 4 and 5. V _BE4 and V _BE5 are base-emitter voltages of the first and second transistors 4 and 5, respectively.

As a result, the differential input terminal from the output terminal 3
Differential AC signal V applied to 1, 2 _INThe full-wave rectified
Wave rectified signal is output voltage V_OUTIs output as

[0012]

SUMMARY OF THE INVENTION
In the configuration of the conventional example, the first and second differential NPN
A differential AC signal V which is an input to the bases of the transistors 4 and 5_IN
Is the absolute temperature, k is the Boltzmann constant, and q is the electron's
When the load is_IN= 4 · kT / q within the dynamic range given by
Then, the first and second NPN transistors 4 and 5
In the state of one-way operation. Therefore, the differential AC signal V _INEntering
When the power level changes, the first and second differential NPN transistors
Current I flowing through emitters of transistors 4 and 5_PO, I_NOof
The values are represented and change as in the formula above, so each
Base-emitter voltage V_BE4, V_BE5Is not constant
No.

On the other hand, a differential AC signal V _IN which is an input to the bases of the first and second differential NPN transistors 4 and 5
Is higher than the dynamic range given by V _IN = 4 · kT / q, one of the first and second differential NPN transistors 4 and 5 is in an operating state, and the first and second differential NPN transistors 4 and 5 are in an operating state.
Currents I _PO and I _NO flowing through the emitters of the differential NPN transistors 4 and 5 are constant regardless of the input level of the differential AC signal V _IN . At this time, the first and second differential N
Compared to the case where both the PN transistors 4 and 5 are in operation, a maximum of twice the current flows through one differential NPN transistor 4 or 5.

As a result, the differential AC signal V input to the bases of the first and second differential NPN transistors 4 and 5
_{When IN} is within the dynamic range given by V _IN = 4 · kT / q, the currents I _PO and I _NO flowing through the emitters of the first and second differential NPN transistors 4 and 5 change according to the input level. Due to these changes in the currents I _PO and I _NO , the base-emitter voltages (V _BE4 and V _BE5 ) of the first and second differential NPN transistors 4 and 5, particularly the bases of the transistors through which more current flows,・ Because the voltage between emitters changes,
The output level changes. For this reason, there is a disadvantage that the linearity between the input level and the output level is deteriorated.

Here, the first differential NPN transistor 4
Current I flowing through_POAnd the second differential NPN transistor 5
Flowing current I_NO9 is shown in FIG. This current I_POAnd electricity
Style I _NOThe curve of the change of the equation
It was created based on it. In FIG. 9, the horizontal axis is
Differential AC signal V_INAnd the vertical axis is the first
And current flowing through second differential NPN transistors 4 and 5
I_PO, I_NOThe value of is taken.

In the above configuration, when the room temperature is 27 ° C., the dynamic range of 4 · kT / q is at the position of 4 · kT / q = 0.040 (V) in the graph of FIG.

Accordingly, it is an object of the present invention to provide a full-wave rectifier circuit that can improve the linearity (linearity) of an output level with respect to a differential input level.

[0018]

According to a first aspect of the present invention, there is provided a full-wave rectifier circuit comprising first and second differential input terminals (1, 2) for inputting a differential AC signal, and a first and a second differential input terminals. First and second differential transistors (4, 5) each having a second differential input terminal (1, 2) connected to a base and having an emitter commonly connected, and a first and second differential transistor A first current source (8) connected to the emitters of the transistors (4,5), and first and second differential transistors (4,5);
A current corresponding to a differential AC signal applied to the output terminal (3) connected to the emitter of (5) and the first and second differential input terminals (1, 2) is supplied to the first current source (8). And first and second transconductors (6, 7) for making the current flowing in the first and second differential transistors (4, 5) substantially constant irrespective of the level of the differential AC signal by flowing the current. ing.

According to this configuration, the first and second transconductors (6, 7) are provided to respond to the differential AC signal applied to the first and second differential input terminals (1, 2). Since the current flows through the first current source (8), the first and second current sources (8)
Of the differential transistors (4, 5) can be made substantially constant regardless of the level of the differential AC signal. As a result, the first and second signals depend on the level of the differential AC signal.
The base-emitter voltage of the differential transistor can be prevented from changing, and the linearity of the output level of the full-wave rectifier circuit with respect to the differential input level can be improved.

A full-wave rectifier according to a second aspect of the present invention comprises:
The full-wave rectifier circuit according to claim 1, wherein the first and second
Have the following configurations. That is, the first transconductor (6) includes third and fourth differential transistors each having the first and second differential input terminals (1, 2) connected to the base and having the emitter commonly connected. (11,1
2) and third and fourth differential transistors (11, 1
A second current source (13) connected to the emitter of (2);
A first current mirror transistor (9) having a collector and a base connected to a collector of the third differential transistor (11) and serving as an input-side element, and a collector of the fourth differential transistor (12) and first and second transistors. A second current mirror transistor (10) having a collector connected to the emitter of the second differential transistor (4, 5) and a base connected to the collector of the third differential transistor (11) and serving as an output-side element; It is composed of

Further, a second transconductor (7)
The fifth and sixth differential transistors (23, 22) having the second and first differential input terminals (2, 1) respectively connected to the base and having the emitters commonly connected.
And fifth and sixth differential transistors (23, 22)
A third current source (24) connected to the emitter of the
A third current mirror transistor (21) having a collector and a base connected to the collector of the differential transistor (23) and serving as an input-side element; and a collector and first and second transistors of a sixth differential transistor (22). And a fourth current mirror transistor (20) serving as an output-side element having a collector connected to the emitter of the differential transistor (4, 5) and a base connected to the collector of the fifth differential transistor (23). Have been.

According to this configuration, the same operation as the full-wave rectifier circuit according to the first aspect is provided.

According to a third aspect of the present invention, there is provided a full-wave rectifier circuit,
3. The full-wave rectifier circuit according to claim 2, wherein the second and the third
The current of the current source (24) is set to １ ／ of the current of the first current source (8).

According to this configuration, the same operation as the full-wave rectifier circuit according to the second aspect is provided.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a full-wave rectifier circuit according to an embodiment of the present invention. As shown in FIG. 1, the full-wave rectifier circuit includes a positive first differential input terminal 1 to which a differential AC signal V _IN is input and a negative second differential input terminal 2. Have been. The first differential input terminal 1 is connected to the base of a first differential NPN transistor 4, and the second differential input terminal 2 is connected to the base of a second differential NPN transistor 5. The first and second differential NPN transistors 4 and 5 have their collectors connected in common and connected to the power supply VCC, their emitters connected in common and connected to the ground GND via the first current source 8.

An output terminal 3 for outputting a full-wave rectified signal is provided to the commonly connected emitters of the first and second differential NPN transistors 4 and 5.

The first and second differential input terminals 1, 1
A current corresponding to the differential AC signal V _IN (voltage) applied to the first and second differential NPN transistors 4 and 5 is supplied to the first current source 8 so that the current of the first and second differential NPN transistors 4 and 5 in which the larger current flows flows First and second transconductors (voltage-current conversion circuits) 6, 7 for making the value substantially constant irrespective of the level of the differential AC signal V _IN are added to the above configuration.

Specifically, in the first transconductor 6, a pair of voltage input terminals 6a and 6b are connected to first and second differential input terminals 1 and 2, respectively, and a current output terminal 6c is connected to the first And second differential NPN transistors 4, 5
And a power supply terminal 6d and a ground terminal 6e are connected to a power supply VCC and a ground GND, respectively.

The second transconductor 7 also has
A pair of voltage input terminals 7a and 7b are connected to the first and second differential input terminals 2 and 1, respectively, and a current output terminal 7c
Are connected to the commonly connected emitters of the first and second differential NPN transistors 4 and 5, and the power supply terminal 7d
And a ground terminal 7e are connected to the power supply VCC and the ground GND, respectively.

The structure of the first and second differential NPN transistors 4 and 5 and the first current source 8, that is, the portion surrounded by a broken line denoted by reference numeral 25 is the full-wave rectifier of the conventional example (FIG. 8). Same as the circuit.

The operation of the conventional full-wave rectifier circuit configured as described above will be described below.

When the level of the differential AC signal V _IN applied to the first and second differential input terminals 1 and 2 changes, the full-wave rectifier circuit converts the first and second transformers accordingly. The current flowing from the conductors 6 and 7 to the first current source 8 changes. As a result, the first and second
Currents I _P and I flowing through the differential NPN transistors 4 and 5 of FIG.
_N can be corrected by the current flowing through the first and second transconductors 6,7. Therefore, regardless of the change in the level of the differential AC signal V _IN , the currents I _P , flowing through the first and second differential NPN transistors 4 and 5
It is possible to make I _N , in particular, the current value of the one through which a large amount of current flows approximately constant. Thereby, the base-emitter voltages V _BE4 and V _{BE5 of} the first and second differential NPN transistors 4 and 5 can be prevented from changing even if the level of the differential AC signal V _IN changes.

FIG. 2 shows a specific circuit diagram of the full-wave rectifier circuit shown in FIG. This figure specifically shows the circuit configuration of the first and second transconductors 6 and 7.

The first transconductor 6 includes third and fourth differential NPN transistors 11 and 12, a second current source 13, and first and second current mirrors PNP.
Transistors 9 and 10, an NPN transistor 14,
It comprises a diode 15 and a current source 16.

In the third and fourth differential NPN transistors 11 and 12, the first and second differential input terminals 1 and 2 are connected to the bases, respectively, and the emitters are commonly connected. The second current source 13 has one end connected to the emitters of the third and fourth differential NPN transistors 11 and 12, and the other end connected to the ground GND. The first current mirror PNP transistor 9 has a collector and a base connected to the collector of the third differential NPN transistor 11 and has an emitter connected to the power supply VCC, and serves as an input-side element. Second current mirror PN
The P transistor 10 has a collector connected to the collector of the fourth differential NPN transistor 12 and emitters of the first and second differential NPN transistors 4 and 5, and a base connected to the collector of the third differential NPN transistor 11. Then, the emitter is connected to the power supply VCC to become an output side element. The NPN transistor 14 has a collector connected to the power supply VCC, an emitter connected to the collector of the fourth differential NPN transistor 12, a base connected to the power supply VCC via the diode 15, and to the ground GND via the current source 16. It is connected.

The second transconductor 7 includes fifth and sixth differential NPN transistors 23 and 22, a third current source 24, and third and fourth current mirrors PNP.
Transistors 21 and 20 and NPN transistor 18
, A diode 17 and a current source 19.

The fifth and sixth differential NPN transistors 23 and 22 have the second and first differential input terminals 2 and 1 respectively connected to the bases and the emitters commonly connected. The third current source 24 has one end connected to the emitters of the fifth and sixth differential NPN transistors 23 and 22, and the other end connected to the ground GND. The third current mirror PNP transistor 21 has a collector and a base connected to the collector of the fifth differential NPN transistor 23 and an emitter connected to the power supply VCC, and serves as an input-side element. Fourth current mirror P
The NP transistor 20 has a collector connected to the collector of the sixth differential NPN transistor 22 and the emitters of the first and second differential NPN transistors 4 and 5.
The base is connected to the collector of the differential NPN transistor 23, and the emitter is connected to the power supply VCC, thereby forming an output side element. The NPN transistor 18 has a collector connected to the power supply VCC, an emitter connected to the collector of the sixth differential NPN transistor 22, a base connected to the power supply VCC via the diode 17, and a ground to the ground GND via the current source 19. It is connected.

In the full-wave rectifier circuit shown in FIG.
When the input level of the differential AC signal V _IN is equal to or greater than the dynamic range given by V _IN = 4 · kT / q, one of the first and second differential NPN transistors 4 and 5 is in operation. At this time, the first current source 8 for full-wave rectification and the first and second transconductors 6, 7
The current ratio of the second and third current sources 13 and 24 incorporated in the first and second differential NPN transistors 4 and 5 is 2: 1. About 1 /
2 is flowing.

The reason why the current ratio is set is that the current ratio is 2: 1 when both the transistor 4 and the transistor 5 are on and when one of them is on. That is, by setting the current ratio between the first current source 8 and the second and third current sources 13 and 24 to 2: 1,
Voltage V _IN current I _P at the 0, the position where I _N is equal, for example, to about half of the current of the current of the first current source 8 (e.g., 25 .mu.A).

More specifically, when the input level of the differential AC signal V _IN is equal to or greater than the dynamic range given by V _IN = 4 · kT / q and the input level of the first differential input terminal 1 is positive, Third differential NPN
The transistor 11 is turned on. At this time, the first
Has a current flowing through the third differential NPN transistor 11, and this current is applied to the first and second current mirrors PN constituting the current mirror circuit.
The current is supplied to the first current source 8 via the P-transistors 9 and 10 as a correction current.

At this time, the second transconductor 7
In this operation, the sixth differential NPN transistor 22 is in an operating state, and current flows from the power supply VCC to the third current source 24 via the transistor 18 and the sixth differential NPN transistor 22. Therefore, no current is supplied from the second transconductor 7 to the first current source 8.

When the input level of the differential AC signal is equal to or greater than the dynamic range given by V _IN = 4 · kT / q and the input level of the first differential input terminal 1 is negative, the fifth differential NPN
The transistor 23 is turned on. At this time, the second
Has a current flowing through the fifth differential NPN transistor 23, and this current is supplied to the third and fourth current mirrors PN constituting the current mirror circuit.
The current is supplied to the first current source 8 via the P transistors 20 and 21 as a correction current.

At this time, the first transconductor 6
In this operation, the fourth differential NPN transistor 12 is in an operating state, and current flows from the power supply VCC to the second current source 13 via the transistor 14 and the fourth differential NPN transistor 12. Therefore, no current is supplied from the first transconductor 6 to the first current source 8.

In the full-wave rectifier circuit of FIG. 2, when the input level of the differential AC signal V _IN is within the dynamic range given by V _IN = 4 · kT / q, the first and second Both the differential NPN transistors 4 and 5 are operating. At this time, the first current source 8 for full-wave rectification
And the second and third current sources 13 and 24 built in the first and second transconductors 6 and 7 have a current ratio of 2: 1 and the first and second differential NPN transistors 4 and 5
The value of the current flowing to the larger current of the first current source 8
電流 of the current flows.

Specifically, when the input level of the differential AC signal V _IN is within the dynamic range given by V _IN = 4 · kT / q and the input level of the first differential input terminal 1 is positive, Third differential NPN
The transistor 11 is turned on. At this time, the first
Has a current flowing through the third differential NPN transistor 11, and this current is applied to the first and second current mirrors PN constituting the current mirror circuit.
The current is supplied to the first current source 8 via the P-transistors 9 and 10 as a correction current. On the other hand, the fourth differential NPN transistor 12 is also in the ON state and a current flows, but its value is smaller than that of the third differential NPN transistor 11.

At this time, the second transconductor 7
In this operation, the sixth differential NPN transistor 22 is in an operating state, and current flows from the power supply VCC to the third current source 24 via the transistor 18 and the sixth differential NPN transistor 22. Therefore, no current is supplied from the second transconductor 7 to the first current source 8. On the other hand, the fifth differential NPN transistor 23 is also in the ON state and the current flows, but the value is smaller than that of the sixth differential NPN transistor 22.

When the input level of the differential AC signal V _IN is within the dynamic range given by V _IN = 4 · kT / q and the input level of the first differential input terminal 1 is negative, the fifth Differential NPN
The transistor 23 is turned on. At this time, the second
Has a current flowing through the fifth differential NPN transistor 23, and this current is supplied to the third and fourth current mirrors PN constituting the current mirror circuit.
The current is supplied to the first current source 8 via the P transistors 20 and 21 as a correction current. On the other hand, although the sixth differential NPN transistor 22 is also in the ON state and the current flows,
Its value is smaller than that of the fifth differential NPN transistor 23.

At this time, the first transconductor 6
In this operation, the fourth differential NPN transistor 12 is in an operating state, and current flows from the power supply VCC to the second current source 13 via the transistor 14 and the fourth differential NPN transistor 12. Therefore, no current is supplied from the first transconductor 6 to the first current source 8. On the other hand, the third differential NPN transistor 11 is also in the ON state and the current flows, but its value is smaller than that of the fourth differential NPN transistor 12.

At this time, the first and second differential NPN
Current I flowing through transistors 4 and 5 _P, I_NThe calculated value of
It looks like this:

Here, the first and second transconductors
Currents corrected from the _FWRAnd the first
And the differential inputs of the second differential NPN transistors 4 and 5
A differential AC signal is_IN(= V_Four-V_Five) And the first
The current of the current source 8 is set to 2I, and the second and third current sources 1
Let I be the current of 3,24.

[0052]

## _EQU4 ## _IFWR = I. [-1 + 2 / ｛1 + exp (V _IN
・ Q / k ・ T)｝]

[0053]

## _EQU5 ## I _P = [(2 · I + I _FWR ) / ｛1 + exp
(V _IN · q / k · T)}] exp (V _IN · q / k ·
T)

[0054]

## _EQU6 ## I _N = (2 · I + I _FWR ) / ｛1 + exp (V
_IN · q / k · T)｝ where T = 273 + t (absolute temperature), k = 1.38 ×
10 ^-23 (Boltzmann's constant), q = 1.6 × 10
^-19 (electron charge), t is the temperature in degrees Celsius.

Here, the first differential NPN transistor 4
A change in current I _N flowing through the current I _P and a second differential NPN transistor 5 flowing in shown in FIG. The currents I _P and I
The curve of the change in _N is created based on the calculation formulas of Equations 4, 5, and 6 above. In FIG. 3, the horizontal axis indicates the input level of the differential AC signal V _IN , and the vertical axis indicates the first level.
And the current I _P flowing through the second differential NPN transistors 4 and 5, taking the I _N.

Here, the current change (the transistor with the larger current) in the above embodiment is changed by providing the transconductors 6 and 7. Specifically, by adding the above-described transconductors 6 and 7, the peak points (positions where the inclination is 0) of the currents I _P and I _N flowing through the first and second transistors 4 and 5 are shown in FIG. From the center position (V _IN = 0). Further, when the input level of the differential AC signal V _IN is 0, the first and second respective transistors 4, 5 25 .mu.A to the flow (current I _P in FIG. 3, the intersection of I _N), First
And the currents I _P and I flowing through the second transistors 4 and 5
The peak point of _N is shifted from the position where the input level of the differential AC signal V _IN is 0. Further, the reason why the current flowing to the transistor having the smaller current of the transistors 4 and 5 also changes is that the gradient of the flowing current is changed.

[0057] Figure 4, the current I _P flowing through the first and second transistors 4, 5, I _N and a current I _P, shows the current I _T is the sum of I _N. At this time, the condition is that the bias current I is 25 × 10 ⁻⁶ (A) and the absolute temperature T is (273 + 50) degrees. The current _IT is represented by the following equation.

[0058]

## EQU7 ## I _T = 2I− | I−2I / ｛1 + exp (q ·
_{V IN / k · T)}} | in FIG. 5, the current I _P flowing through the first and second transistors 4 and 5, shows an enlarged view of the horizontal axis I _N. Also,
The Figure 6 shows the current I _P flowing through the first and second transistors 4 and 5, the slope of I _N, i.e. the input level of the current I _P, I _N differential AC signal V _IN to differential of abscissa I have. FIG. 7 shows the output voltage V in the embodiment.
_OUT and the output voltage V _OUTO in the conventional example are shown with the input level of the differential AC signal V _IN on the horizontal axis. It is apparent from FIG. 7 that the embodiment has improved linearity.

According to this configuration, the first and second transconductors 6 and 7 are provided to supply a current corresponding to the differential AC signal V _IN applied to the first and second differential input terminals 1 and 2. Since the current flows through the current source 8, the current flowing through the first and second differential NPN transistors 4, 5 can be made substantially constant regardless of the level of the differential AC signal. As a result, depending on the level of the differential AC signal V _IN , the first and second differential N
The base-emitter voltages of the PN transistors 4 and 5 can be kept from changing, and the linearity (linearity) of the output level of the full-wave rectifier circuit with respect to the differential input level
Can be improved.

[0060]

According to the full-wave rectifier circuit of the present invention, the first
And a second transconductor for flowing a current corresponding to a differential AC signal applied to the first and second differential input terminals to the first current source, so that the first and second differential NPs are provided.
The current flowing through the N transistor can be made substantially constant regardless of the level of the differential AC signal. As a result, the base-emitter voltages of the first and second differential transistors can be prevented from changing according to the level of the differential AC signal, and the linearity of the output level of the full-wave rectifier circuit relative to the differential input level ( Linearity) can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a full-wave rectifier circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit of the full-wave rectifier circuit of FIG.

FIG. 3 is a graph showing a relationship between a level of a differential AC signal and currents flowing through first and second differential NPN transistors in the embodiment.

FIG. 4 is a graph showing a relationship between a level of a differential AC signal, currents flowing through first and second differential NPN transistors, and a sum of those currents in the embodiment.

FIG. 5 is a graph showing a relationship between a level of a differential AC signal and currents flowing through first and second differential NPN transistors in the embodiment.

FIG. 6 is a graph showing the relationship between the level of a differential AC signal and the differentiation of the current flowing through the first and second differential NPN transistors in the embodiment.

FIG. 7 is a graph showing a relationship between a level of a differential AC signal and a level of an output voltage in the embodiment.

FIG. 8 is a circuit diagram showing a configuration of a conventional full-wave rectifier circuit.

FIG. 9 shows the level of the differential AC signal and the first level in the conventional example.
9 is a graph showing a relationship between the current flowing through the second differential NPN transistor and a current flowing through the second differential NPN transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st differential input terminal 2 2nd differential input terminal 3 output terminal 4 1st differential NPN transistor 5 2nd differential NPN transistor 6 1st transconductor 7 2nd transconductor 8 1st Current source 9 first current mirror PNP transistor 10 second current mirror PNP transistor 11 third differential NPN transistor 12 fourth differential NPN transistor 13 second current source 14 transistor 15 diode 16 current source 17 diode Reference Signs List 18 transistor 19 current source 20 fourth current mirror PNP transistor 21 third current mirror PNP transistor 22 sixth differential NPN transistor 23 fifth differential NPN transistor 24 third current source

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Miyaji 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (Reference) 5H006 CA01 CA13 CC04 5J066 AA01 AA12 CA21 FA05 HA08 HA19 KA02 KA05 KA09 MA21 ND01 ND22 ND23 TA02 TA06

Claims (3)

[Claims] A first and a second inputting a differential AC signal.
First and second differential input terminals (1, 2) and the first and second differential input terminals (1, 2) are respectively connected to a base, and the emitters are commonly connected. A transistor (4, 5); a first current source (8) connected to the emitters of the first and second differential transistors (4, 5); and the first and second differential transistors ( Output terminal (3) connected to the emitter of (4, 5)
Flowing a current corresponding to the differential AC signal applied to the first and second differential input terminals (1, 2) to the first current source (8), A full-wave rectifier circuit comprising first and second transconductors (6, 7) for making a current flowing through a differential transistor (4, 5) substantially constant regardless of the level of the differential AC signal. 2. A first transconductor (6) having a first and second differential input terminals (1, 2) respectively connected to a base and an emitter commonly connected to a third transconductor (6).
And fourth differential transistors (11, 12); a second current source (13) connected to the emitters of the third and fourth differential transistors (11, 12);
A first current mirror transistor (9) having a collector and a base connected to a collector of the differential transistor (11) and serving as an input-side element; a collector of the fourth differential transistor (12); A second current mirror transistor (10) which has a collector connected to the emitter of the second differential transistor (4, 5) and a base connected to the collector of the third differential transistor (11) and serves as an output-side element The second transconductor (7) comprises a fifth and a sixth transconductors (7) in which the second and first differential input terminals (2, 1) are respectively connected to a base and the emitters are commonly connected.
, A third current source (24) connected to the emitters of the fifth and sixth differential transistors (23, 22), and the fifth differential transistor (23). A third current mirror transistor (21) having a collector and a base connected to the collector of (23) and serving as an input-side element; and the sixth differential transistor (2).
A collector is connected to the collector of 2) and the emitters of the first and second differential transistors (4, 5), and a base is connected to the collector of the fifth differential transistor (23) to be an output-side element. 2. The full-wave rectifier circuit according to claim 1, comprising a fourth current mirror transistor (20). 3. The full-wave rectifier circuit according to claim 2, wherein the currents of the second and third current sources are set to one half of the current of the first current source.