JP2001345442A - Mis-type fet and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MIS-type FET which has low resistance, and is suitable for miniaturizing, easy to manufacture and proper for fine type whose gate length is approximately 0.2 μm or less and an SOI structure, and a method for manufacturing a semiconductor device of such an MIS-type FET or the like. SOLUTION: The semiconductor device has a gate electrode 10 on a substrate 50, and a source diffusion layer 30 and a drain diffusion layer 30 which are adjacent each via an insulation film 20 in the gate electrode 10. The semiconductor device has a gate side wall insulation film 60 which is formed in a side surface of the gate electrode 10 and covers a part of the source diffusion layer 30 and the drain diffusion layer 30 each; and first and second conductor layers 70A which are in contact with at least a part of a region excepting an area below the gate sidewall insulation film 60 of the source diffusion layer 30, and the drain diffusion layer 30 and extend from the contact position onto an isolation insulation film 40 which is adjacent to the source diffusion layer 30 and the drain diffusion layer 30 each.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor (MIS type FET: Metal Insulator Semiconductor).
In particular, the present invention relates to a semiconductor device having a source / drain structure which can provide a shallow pn junction suitable for miniaturization, a low parasitic resistance and a low parasitic capacitance, and is easy to manufacture. ,as well as,
It relates to the manufacturing method.

[0002]

2. Description of the Related Art In an MIS type FET, it is necessary to attach a low-resistance metal to a source diffusion layer and a drain diffusion layer in order to reduce parasitic resistance in source / drain regions and obtain good transistor physical properties. . To achieve this, the “salicide method” of forming a metal silicide film on the source diffusion layer and the drain diffusion layer in a self-aligned manner is widely used.

[0003] FIG. 11 is a diagram showing a MI by the general salicide method.
It is sectional drawing which shows the manufacturing procedure of S type FET (1st conventional example). First, as shown in FIG.
An element isolation insulator 240 is formed on 50, and a gate insulating film 220 is formed at a predetermined position. Next, a gate electrode 210 made of polysilicon is formed and processed on the gate insulating film 220.

Further, a shallow source / drain region 230A is formed by ion implantation using the gate electrode 210 as a mask. Subsequently, a gate side wall 260 made of an insulator is formed on both side surfaces of the gate electrode 210 and on the source / drain region 230A, and ion implantation using the gate electrode 210 and the gate side wall 260 as a mask allows the outside of the source / drain region 230A to be formed. And source / drain region 2
A source / drain region 230B deeper than 30A is formed.

Next, as shown in FIG. 11B, the entire surface of the silicon substrate 250 including the gate electrode 210, the gate side wall 260, the source / drain diffusion layer (region) 230B, and the element isolation insulator 240 is formed. A metal film 270 made of titanium, cobalt, or the like is deposited.

[0006] Further, as shown in FIG.
A heat treatment is performed on the entire surface of the semiconductor layer 70 to selectively cause a silicidation reaction only in a portion where the metal film 270 and silicon are in contact with each other. To form At this time, the metal layer 270C that does not contact the silicon
Is not silicided.

Next, as shown in FIG. 11D, after the metal film 270C that has not been silicided is removed by wet etching, an interlayer insulating film is formed on the entire surface of the silicon substrate 250 including the gate sidewall 260 and the metal silicide 270B. The film 300 is formed. Further, contact holes 28 are formed at positions corresponding to metal silicides 270A of interlayer insulating film 300.
After forming 0, a metal wiring 290 is connected via a metal plug formed in the contact hole 280.

A method of attaching a metal to a source / drain diffusion layer by utilizing selective growth of a metal in the manufacture of an MIS type FET is disclosed in International Electron Dev.
proposed by Hisamoto et al. in iceMeeting (second conventional example). This example is based on SOI (Silic) shown in FIGS.
On-On-Insulator) Applied to MIS type FET using substrate. 12, the same reference numerals are given to the components and elements common to FIG.

First, a known technique is applied to the SOI substrate 250 to obtain a structure shown in FIG. However, the SOI substrate 25
0, the source / drain region 230 and the channel region 320 of the MIS type FET are
The insulating film is formed on the buried insulating film 330 integrated with the insulating film 40. Because this silicon film is thin,
In this example, the deep source / drain diffusion layer 230B shown in FIG. 11 is not formed. The insulating film 330 on the gate electrode 210 is provided for the purpose of preventing tungsten from growing on the gate electrode 210.

Next, as shown in FIG.
The tungsten is selectively grown only on the exposed portions of the source / drain diffusion layers 230 by the
Form 1A. Since the metal layer 271A is deposited above without substantially eroding the source / drain regions, the source / drain extension structure is not required.
For this reason, the thickness of the gate sidewall 260 and the width of the source / drain region can be reduced irrespective of the restrictions imposed by the deep source / drain region 230B, thereby increasing the degree of integration.

Further, as shown in FIG. 12C, an interlayer insulating film 300 is formed on the entire surface of the element isolation insulator 240 including the buried insulating film 330, the gate side wall 260, and the metal layer 271A. Subsequently, after a contact hole 280 is formed at a position corresponding to the metal layer 271A in the interlayer insulating film 300, a metal wiring 290 is connected via a metal plug formed in the contact hole 280.

According to the different methods in the first and second conventional examples, the metal layer 270A or 271A is formed in a self-aligned manner with respect to the exposed portion of silicon.
0A or 271A automatically covers the entire exposed portion of the source / drain region, particularly up to the immediate vicinity of the gate electrode, and the parasitic resistance is effectively reduced.

[0013]

In the first prior art, the metal layer 270A is formed by reacting the deposited metal with silicon using the salicide method, so that the silicon diffusion layer is eroded by the metal layer 270A. Is done. Therefore, the formed metal layer 270A sinks into the silicon substrate. When the bottom surface of the metal layer 270A approaches the bottom surface of the source / drain diffusion layer 230B, the junction leakage current increases.
It must be formed sufficiently deeper than the thickness of 70A. On the other hand, in order to miniaturize the MIS type FET while suppressing the short channel effect, there is a demand for making the source / drain diffusion layers sufficiently shallow especially in the vicinity of the gate electrode 210.

In order to satisfy these two conflicting requirements at the same time, when the salicide method is used for an MIS type FET having a gate length of about 0.5 μm or less, the source / drain region is formed in a region near the gate electrode 210. 230A is shallow,
In the region 230B where the metal layer 270A is formed, the source / drain extension structure shown in FIG. This structure corresponds to the area 230A
Is relatively low, it is also called an LDD structure.

When miniaturization of the MIS type FET is advanced, it is desirable to reduce the area of the entire source / drain region and the width of the gate side wall 260 to improve the degree of integration. However, it is necessary to keep the thickness of the metal layer 270A sufficiently large for lowering the resistance, so that it is difficult to make the source / drain regions shallow. For this reason, the gate side wall 260 having a function of keeping the deep source / drain diffusion layer 230B away from the gate electrode 210 cannot be thinned, and the width of the source / drain region increases accordingly.

As described above, since the salicide method requires the deep source / drain diffusion layer 230B, even if the gate electrode 210 is miniaturized, the source / drain diffusion layer 230B is suitable.
There is a problem that the drain region cannot be miniaturized, and improvement in the integration degree of the MIS type FET is hindered. This problem becomes more serious as the gate length becomes shorter, and the gate length is generally greater than the depth of the source / drain diffusion layer 230B (typically 80 to 10).
0 nm or more) (ie, the gate length is
(0.2 μm or less).

Another problem in the salicide method is that a high-temperature heat treatment is required. That is, in the salicidation reaction, heating at about 900 ° C. is required, whereby impurities diffuse into the source / drain regions. This diffusion amount is the same as that of the conventional MI with a relatively large gate length.
This is not a problem in the S-type FET, but a problem such as an increase in the short channel effect is caused in the fine MIS-type FET.

On the other hand, in the second conventional example, the above problem can be reduced by using the selective growth of tungsten as described above. However, since the selective growth method is used, a highly integrated circuit can be manufactured with a high yield. Difficult to produce. That is, in the selective growth method, the presence or absence of film growth is controlled according to the subtle state difference of the underlayer. Therefore, a phenomenon such that the film does not grow in the region where growth is necessary or grows in the region where growth is unnecessary (selectivity). Failure).

Another problem in a fine MIS type FET is a parasitic capacitance in a source / drain diffusion layer. In order to operate the MIS type FET at high speed, it is desirable to reduce the parasitic capacitance as much as possible. For that purpose, it is effective to reduce the area of the source / drain diffusion layers. In each of the structures shown in FIGS. 11D and 12C, the metal layer is formed only immediately above the source / drain diffusion layers, while the contact hole 280 is covered with the metal layer. It is necessary to open the inside of the area.

Therefore, it is necessary to secure a sufficient area for the opening of the source / drain diffusion layer, which is obtained by adding a positioning margin to the size of the contact hole. For this reason, there is a problem that the area of the source / drain diffusion layer is larger than the minimum processable dimension determined by the lithography technique, and the parasitic capacitance is increased accordingly.

Further, in the structure shown in FIG. 12C, which does not use a deep source / drain diffusion layer, there is no need for a method of keeping the deep source / drain diffusion layer away from the gate electrode. Compared to the structure shown in FIG. 11D, this is advantageous in reducing the area of the source / drain diffusion layers, but it is desired to further reduce the diffusion layer area for higher performance.

In view of the above, the present invention provides a MIS type FET which has low resistance, is suitable for miniaturization, is easy to manufacture, and is suitable for a fine type or SOI structure having a gate length of about 0.2 μm or less, and It is an object of the present invention to provide a manufacturing method for manufacturing a semiconductor device such as the MIS type FET.

The present invention further achieves the above object,
MIS with a structure that can reduce parasitic capacitance in source / drain diffusion layers without being restricted by contact hole formation
It is intended to provide a type FET.

The present invention further achieves the above object,
An object of the present invention is to provide an MIS type FET having a structure in which contact resistance between a source / drain diffusion layer and a metal layer is reduced.

[0025]

In order to achieve the above object, an MIS type FET according to the present invention comprises a gate electrode, a source diffusion layer and a drain adjacent to the gate electrode via an insulating film. In a MIS type FET including a diffusion layer, a gate sidewall insulating film formed on a side surface of the gate electrode and covering each part of the source diffusion layer and the drain diffusion layer;
The source diffusion layer and the drain diffusion layer are in contact with at least a part of a region except under the gate sidewall insulating film, and are respectively formed on the insulators adjacent to the source diffusion layer and the drain diffusion layer from the contact position. First and second extending
And a conductor layer of

In the MIS type FET of the present invention, a conventional deep source / drain region for receiving the sink of the conductive layer is unnecessary, and the gate side wall insulating film is thinned to make the conductive layer as close as possible to the gate electrode. Therefore, a parasitic resistance is reduced, a structure suitable for miniaturization and easy to manufacture is obtained, and a structure suitable for a fine type or SOI structure having a gate length of about 0.2 μm or less is obtained. Further, since the first and second conductor layers have a structure in contact with at least a part of the source / drain diffusion layers, the area of the source / drain diffusion layers which should be electrically connected to the metal wiring through the contact holes can be reduced. Accordingly, the parasitic capacitance can be reduced.

Here, in the preferred MIS type FET of the present invention,
The respective upper surfaces of the first and second conductor layers are located farther from the substrate than the lower surface of the gate electrode. In this case, since the upper surface of the conductor layer is located above the gate insulating film originally located on the surface of the substrate, the thickness of the conductor layer is ensured while ensuring sufficient thickness of the first and second conductor layers. Sinking into the source / drain diffusion layers can be suppressed.

Preferably, each of the first and second conductor layers is formed of a laminated film made of two or more different materials. For example, when the lowermost layer of the laminated film is composed of a semiconductor, the contact resistance between the first and second conductor layers and the source / drain diffusion layers can be reduced.

Furthermore, it is preferable that the lowermost layer in the laminated film is made of a semiconductor having the same conductivity type as the source diffusion layer and the drain diffusion layer. In this case, since the semiconductor layer and the source / drain diffusion layers usually need to be doped with impurities of the same conductivity type, the parasitic resistance of the source / drain regions caused by the contact resistance can be reduced. By simultaneously doping the source / drain region and the semiconductor layer, a structure that reduces contact resistance can be easily manufactured in a short process. Further, a shallow source / drain junction can be easily formed by this method.

Further, an interlayer insulating film deposited on the substrate including the gate electrode, the source diffusion layer, the drain diffusion layer, the gate side wall insulating film, and the conductor layer; A contact hole communicating from the metal wire to the corresponding first and second conductor layers is formed in the interlayer insulating film, and formed in the contact hole. It is preferable that at least a portion of the bottom surface of the metal plug is located outside the source diffusion layer and the drain diffusion layer.

In this case, the first and second conductor layers are in contact with the upper surfaces of the source / drain diffusion layers and extend to the outside of the element isolation insulator. The contact hole for connecting the layer and the metal wiring can be designed so as to protrude outside the source / drain diffusion layer from the beginning, and the degree of freedom in design increases. Alternatively, when such a design is not made, even if the contact hole slightly deviates from the designed position due to a positional deviation at the time of manufacturing, the contact hole may protrude outside the source / drain diffusion layer. Can be tolerated.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a step on a substrate; depositing an anisotropic conductor on the substrate anisotropically; A step of thickly attaching the conductor to an upper surface, a step of removing the conductor from the side surface of the step by isotropic etching, and a step of processing the conductor remaining on the substrate into a desired planar shape. It is characterized by including.

In the method of manufacturing a semiconductor device according to the present invention, the conductor layer is attached to the source / drain diffusion layers by anisotropic deposition and isotropic etching, so that the size is smaller than when the salicide method is used. A source / drain region having a low resistance can be obtained in an area, and this can be realized with a higher yield as compared with the selective growth method. Further, based on this configuration, it is possible to realize a source / drain structure suitable for a fine MIS FET or an MIS FET having an SOI structure, in which the erosion of the substrate is small.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a substrate; forming a side insulator covering side surfaces of the gate electrode; Anisotropically depositing, a step of attaching the conductor thicker to the upper surface of the substrate than the side surface of the gate electrode, and a step of removing the conductor from the side surface of the gate electrode by isotropic etching. Processing the conductor remaining on the substrate into a desired planar shape.

In the method of manufacturing a semiconductor device according to the present invention, the conductor layer is attached to the source / drain diffusion layers by anisotropic deposition and isotropic etching, so that the size is smaller than that in the case where the salicide method is used. A source / drain region having a low resistance can be obtained in an area, and this can be realized with a higher yield as compared with the selective growth method. Based on this configuration, it is possible to realize a source / drain structure suitable for a fine MIS type FET or a MIS type FET having an SOI structure with little erosion of the substrate.

Here, it is preferable that at least one of the step of attaching the conductor and the step of removing the conductor is performed a plurality of times. This case is effective when a plurality of first to n-th layers can be continuously etched by the same means.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate electrode on a substrate; forming a side insulator covering the side surface of the gate electrode; Anisotropically depositing, attaching the semiconductor thicker to the upper surface of the substrate than to the side surface of the gate electrode, removing the semiconductor from the side surface of the gate electrode by isotropic etching, A step of introducing an impurity into a part of the substrate in contact with the lower surface of the semiconductor; and a step of processing the semiconductor into a desired planar shape.

In the method of manufacturing a semiconductor device according to the present invention, the conductor layer is attached to the source / drain diffusion layers by anisotropic deposition and isotropic etching, so that the size is smaller than when the salicide method is used. A source / drain region having a low resistance can be obtained in an area, and this can be realized with a higher yield as compared with the selective growth method. Based on this configuration, it is possible to realize a source / drain structure suitable for a fine MIS type FET or a MIS type FET having an SOI structure with little erosion of the substrate.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on embodiments of the present invention with reference to the drawings. FIG.
And FIG. 2 shows an MIS type FET according to the first embodiment of the present invention.
FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device.
(a)-(c) show each process step by step.

First, before describing this manufacturing method, the structure of the MIS type FET according to the present invention will be described with reference to FIG. 2C showing a completed state. This MIS type FET includes an element isolation insulating film 40 formed on a substrate 50 made of silicon or the like, a source / drain diffusion layer 30 formed in a region sandwiched between the element isolation insulating films 40, and a source / drain diffusion layer. A gate electrode 10 forming a step adjacent to the gate electrode 30 via a gate insulating film 20;
A gate sidewall insulating film 60 formed on both side surfaces of the gate electrode 10, a conductor layer 70B formed on the upper surface of the gate electrode 10, and respective end faces located on both sides of the gate electrode 10 and facing the gate electrode 10 side; And a pair of conductor layers 70 </ b> A in contact with the gate sidewall insulating film 60. A pair of conductor layers 7
0A contacts at least a part of a region of the source / drain diffusion layer 30 except under the gate sidewall insulating film 60;
From this contact position, each of them extends on the element isolation insulating film 40 (insulator) adjacent to the source / drain diffusion layer 30.

The MIS type FET further includes an interlayer insulating film 10 formed on the entire surface of the substrate 50 including the gate electrode 10, the gate side wall insulating film 60, the conductor layer 70A, and the element isolation insulating film 40.
0, a contact hole 80 opened at a position corresponding to the conductor layer 70A of the interlayer insulating film 100, and a contact hole 80
And a metal wiring 90 electrically connected to the conductor layer 70A via a metal plug filled therein.

In the present MIS type FET, the conductor layer 70A is in contact with the upper surface of the source / drain diffusion layer 30 and extends to the outside of the element isolation insulator 40. The contact hole 80 connecting the layer 30 and the metal wiring 90 can be designed so as to protrude outside the source / drain diffusion layer 30 from the beginning,
The degree of freedom in design increases. Alternatively, when such a design is not made, even if the contact hole 80 is slightly deviated from the designed position due to a positional shift at the time of manufacturing, the contact hole 80 may be out of the source / drain diffusion layer 30. Extrusion can be tolerated.

As a result, the area of the source / drain diffusion layers can be reduced without any restrictions for accommodating the contact holes 80, and the parasitic capacitance can be reduced accordingly. In addition, since the upper surface of the conductor layer 70A is located above the gate insulating film 20 originally located on the substrate surface, the source / drain diffusion layer 30A can be formed while sufficiently securing the thickness of the conductor layer 70A. Sinking of the conductor layer 70A into the conductor layer 70A can be reduced. This allows the source
The drain diffusion layer 30 can be formed shallowly, and the short channel effect of the MIS type FET can be suppressed. At the same time, since a deep source / drain diffusion layer for receiving the sink of the conductor layer is not required, the area of the source / drain diffusion layer can be reduced, and the parasitic capacitance can be reduced. Further, since a deep source / drain diffusion layer is not required, the gate sidewall insulating film 60 can be thinned and the conductor layer 70A can be close to the gate electrode, so that the parasitic resistance is reduced.

Next, a method of manufacturing the MIS type FET according to this embodiment will be described. First, as shown in FIG.
After the element isolation insulator 40 is formed on the substrate 50 and the gate insulating film 20 is formed, the gate electrode 10 made of polysilicon is formed on the gate insulating film 20 and processed. Thereafter, the source / drain diffusion layer 30 is formed by ion implantation using the gate electrode 10 as a mask.

Subsequently, as shown in FIG.
An insulating film made of a silicon oxide film, a silicon nitride film, or the like is formed on both side surfaces of the gate electrode 10, the source / drain diffusion layers 30 and the element isolation insulating film 40 by a method or the like so as to sufficiently cover the side surfaces of the gate electrode 10. Deposit 60. Next, as shown in FIG. 1C, the gate side wall insulating film 60 is anisotropically etched by a known method, and the insulating film 60 is left only on the side surfaces of the gate electrode 10.

Further, as shown in FIG.
Are deposited anisotropically so that the constituent particles thereof are perpendicularly incident on the substrate 50 from above. Thereby, the conductor 70
Is deposited thick on the upper surface of the substrate 50 and thinly on the surface of the gate electrode side wall 60 perpendicular to the substrate 50. If the incidence of the particles is vertical, the particles should ideally not adhere to the vertical surface, but actually, there are particles incident in a direction deviated from the vertical, so that the side surface of the gate electrode side wall 60 also exists. The conductor 70 adheres thinly.

Subsequently, as shown in FIG. 2A, the thin conductor 70 attached to the side surface of the gate electrode side wall 60 is removed by isotropic etching, but the thick conductor 70 on the upper surface remains. The conductor 70 is etched as described above.
That is, the conductor 70 is selectively removed only from the side surface by utilizing the difference in thickness between the side surface and the upper surface.

Next, as shown in FIG. 2B, the conductor 70 is cut into a desired planar shape by using a photolithography method or the like. At this time, the processing plane pattern can be appropriately set as necessary, such as a pattern in which two or more MIS type FETs are connected to each other as necessary. Thereby, the conductor 70 can be used also as a wiring layer.

Subsequently, as shown in FIG. 2C, an interlayer insulating film 100 is deposited on the entire surface of the substrate 50 including the gate electrode 10 and the conductor layer 70A. Further, the interlayer insulating film 100
A contact hole 80 is opened at a position corresponding to the conductor layer 70A in the above, and the conductor layer 70A is connected to the metal wiring 90 via a metal plug filled in the contact hole 80. FIG. 2 (c) shows a cross-sectional structure along the line AA in FIG. 4 (c).

In the case of the MIS type FET having the conventional structure, the contact hole 80 should be opened so as to fit in the source / drain diffusion layer 30 covered by the conductor 70A. But,
Since the MIS type FET according to the present embodiment has the above structure, the conductor 70A extended outside the source / drain diffusion layer 30 rides outside the source / drain region, so that the source / drain diffusion layer 30 The contact hole 80 is substantially widened, and the restriction when forming the contact hole 80 is reduced.
For this reason, the source / drain diffusion layers 30 can be designed appropriately small, and the parasitic capacitance can be reduced.

The order of the isotropic etching step in FIG. 2A and the planar shape processing step in FIG. 2B can be interchanged. When the isotropic etching is performed in two or more stages, some of the isotropic etching steps can be performed after the planar shape processing.

In the step of depositing the anisotropic conductor 70, known methods such as a collimator sputtering method, a remote distance sputtering method, and an ionization evaporation method can be used. These are techniques originally developed primarily for depositing metal at the bottom of deep contact holes, but are suitable for implementing the present invention.

Next, FIGS. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (c) which are plan views corresponding to FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (c), respectively. ), The MIS type FET of this embodiment will be described.

In FIG. 3A corresponding to FIG.
An element isolation insulating film 40 is formed on the entire upper surface, and a source / drain diffusion layer 30 is formed in a rectangular shape at a central portion of the element isolation insulating film 40, and a gate electrode 10 that bisects the center of the source / drain diffusion layer 30. Extends. The portion of the gate electrode 10 that is not located on the source / drain diffusion layer 30 is formed in a square shape having a larger area than other portions.

In FIG. 3B corresponding to FIG. 1B, an insulating film 60 is formed on the entire surface of the substrate 50 including the element isolation insulating film 40, the source / drain diffusion layers 30, and the gate electrode 10. In FIG. 3C corresponding to FIG. 1C, the gate side wall insulating film 60 is anisotropically etched, and the insulating film 60 remains only on the side surface of the gate electrode 10.
Element isolation insulating film 40 and source / drain diffusion layer 30
Is exposed. In FIG. 3D corresponding to FIG. 1D, the conductor 70 is thick on the upper surface of the substrate 50 and the gate electrode side wall 60 is formed.
Is deposited thinner than the upper surface of the substrate 50.

In FIG. 4A corresponding to FIG. 2A, the conductor 70 attached to the side surface of the gate electrode side wall 60 is removed by a predetermined thickness, and the thick conductor 70 on the upper surface of the gate electrode 10 remains. are doing. In this state, the conductor 70 is connected to the gate electrode 10.
, But are continuous and conductive in a region outside the gate electrode 10.

In FIG. 4B corresponding to FIG. 2B, the conductor 7
0 is cut into a planar shape to form a conductor layer 70A. The conductor 70 is removed by etching while leaving the region 110 shown in FIG. 4A, and the region 110 is configured to cross the vicinity of both ends of the gate electrode 10 in FIG. The conductor 70 is separated so as to correspond to each of the left and right source diffusion layers and drain diffusion layers.

In FIG. 4C corresponding to FIG.
Conductor layer 70A of interlayer insulating film 100 deposited on the entire upper surface
A contact hole 80 is opened at a position corresponding to the conductive layer 7 through a metal plug filled in the contact hole 80.
0A is connected to the metal wiring. In FIG. 4C, FIG.
The visibility is made clear by omitting the metal wiring 90 shown in FIG.

FIG. 5 is a block diagram showing an MI according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an S-type FET. In the present embodiment, FIG.
An SOI substrate is used instead of the substrate 50 shown in FIG. This MIS type FET has the configuration shown in FIG. 2 () except that the buried oxide film 130 is located below the source / drain diffusion layer 30 and the channel region 120, and the element isolation insulating film 40 is integrated with the buried oxide film 130. It has the same structure as the MIS type FET of the first embodiment shown in c).

In the SOI substrate of this embodiment, it is necessary to suppress the thickness of the semiconductor layer on the buried oxide film 130 in order to suppress the short channel effect, and it is difficult to provide a deep source / drain diffusion layer. . In the present embodiment, similarly to the first embodiment, the upper surface of the conductor layer 70A is formed so as to be located above the gate insulating film 20, and a deep source / drain diffusion layer as in the related art is not required. Therefore, the SOI substrate can be suitably used.

In FIG. 2C and FIG. 5, the conductor layer 70A has been described as being made of a single material. However, this is an example, and is shown in FIGS. Such a conductor layer 70A is made of two kinds of materials.
A laminate of A and 72A may be used, or a laminate structure of three or more materials may be used. The kind and the number of layers of the material to be used are required to make the conductor layer 70A (70A in FIG. 2 (c) include various laminated structures) exhibit desired performance or to facilitate manufacture. You just need to select a suitable combination.

First, the preferred first configuration example in the case of using one conductive layer 70A as shown in FIG. 2C has the advantage that the manufacturing process is simplified, It is necessary to select a material that can achieve a good balance of adhesion, low resistance, and barrier properties between the upper and lower layers (performance of preventing diffusion and mixing of a substance between the two layers). In this case, various metal nitrides such as titanium nitride, tungsten nitride, and tantalum nitride, and various metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, nickel silicide, and platinum silicide can be used.

On the other hand, in a desirable second configuration example in which the conductor layer 70A has a two-layer structure, a material excellent in low-resistance contact with the source / drain diffusion layer 30, which is an underlying layer, is used for the lower layer. For the upper layer, a material having a barrier property between the source / drain diffusion layer 30 and the contact material is used.
Titanium is suitable for the material of the lower layer, and various metal nitrides and metal silicides are suitable for the material of the upper layer. By such a combination of materials, the resistance due to the contact is reduced, and the driving capability of the MIS type FET is improved.

In a third preferred embodiment of the conductor layer 70A, a material having excellent adhesion and a barrier property between the upper layer and the base is used for the lower layer, and a material having particularly low resistance is used for the upper layer. . In this case, various materials such as metal nitride and metal silicide are suitable as the material of the lower layer, and tungsten, copper, silver, aluminum and the like are suitable as the material of the upper layer. By such a combination of materials, the layer resistance of the metal film is reduced, and the performance and the degree of design freedom particularly when the conductor layer 70A is used as the wiring are improved.

In a fourth preferred configuration example of the conductor layer 70A, a material excellent in low-resistance contact with the source / drain diffusion layer 30 as a base is used for the lower layer, and the source / drain diffusion layer 30 is used for the intermediate layer. A material having a barrier property between the material and the upper layer is used, and a material having particularly low resistance is combined with the upper layer. In this case, titanium or the like is suitable as the material of the lower layer, various metal nitrides or metal silicides are suitable as the material of the intermediate layer, and tungsten, copper, silver, aluminum, or the like is suitable as the material of the upper layer. With such a combination of materials, the resistance caused by the contact and the layer resistance of the metal film are simultaneously reduced.

In a fifth preferred configuration example of the conductor layer 70A, a layer having a barrier property between the low-resistance material and the contact material is further provided as the uppermost layer in each of the third configuration example and the fourth configuration example. Add. As the material to be added, various metal nitrides and metal silicides are suitable.

In the first, second and fifth configuration examples, the use of a material having excellent barrier properties as the uppermost layer facilitates the formation of contacts. That is, in the normal contact formation, after the contact hole is opened, a metal having a barrier property is buried at the bottom of the contact. However, in the case of a fine contact, the contact hole is deeper (having a higher aspect ratio) than the opening area, and It is difficult to embed a metal having a barrier property to the bottom of the substrate. However, by depositing a metal having a barrier property before the opening of the contact hole as in the first, second, and fifth configuration examples, the formation of the barrier metal after the opening of the contact hole can be omitted.

In a preferred sixth configuration example of the conductor layer 70A,
A semiconductor layer of the same conductivity type (n-type or p-type) as the source / drain diffusion layer 30 is further added as the lowermost layer to the first to fifth configuration examples. As described above, when layers made of different materials are stacked, the contact resistance between the layers is relatively small between the metals or between the semiconductors of the same conductivity type. Is higher than the above case, and this may be a problem.

As described with reference to FIGS. 1 and 2, when the conductor layer 70A is entirely made of metal, the contact area between the metal layer and the source / drain diffusion layer 30 which is a semiconductor becomes It is limited by the area of the diffusion layer 30. FIG. 6 is a sectional view showing an example in which the contact area between the semiconductor and the metal is increased. In this example, the lower conductive layer 71A is made of a semiconductor, the upper conductive layer 72A is made of a metal, and the contact area between the semiconductor and the metal is smaller than the conductive layer 71A.
Since A and 72A are increased by being extended on the element isolation insulator 40, the area of the source / drain diffusion layer 30 is reduced to reduce the parasitic capacitance, while preventing an increase in parasitic resistance due to contact resistance. can do. As the material of the added lowermost layer, silicon, germanium, a mixed crystal of silicon and germanium, or the like can be selected. In particular, the incorporation of germanium reduces the forbidden band width of the semiconductor, and is thus effective in reducing the contact resistance. With such a combination of materials, resistance due to contact can be further reduced.

As is clear from the embodiments described above, the feature that forms the basis of the method of manufacturing the MIS type FET according to the present invention is that the step pattern and the anisotropic conductor film deposition combine to reduce the step. It is to obtain a conductor layer separated in a self-aligned manner. As a result, a desired conductor layer can be formed on the source / drain diffusion layers in a self-aligned manner with respect to the gate electrode without eroding the substrate.
The deep source / drain diffusion layers required by the salicide method can be eliminated, so that the source / drain diffusion layers can be easily miniaturized and the SOI structure can be easily realized.

Further, since it is not necessary to use the selective growth method and the sputtering method or the vapor deposition method can be used, stable production is possible. Further, it is easy to extend the conductor layer outside the source / drain diffusion layers. For this reason, a structure that reduces the source / drain diffusion layer parasitic capacitance without being restricted by the contact hole opening already described,
Alternatively, it is possible to easily form a structure for reducing the contact resistance in the source / drain diffusion layers using a stacked film of a semiconductor and a metal.

Further, since high-temperature heat treatment is not required for forming the conductor layer, unnecessary diffusion of impurities is suppressed, which is advantageous for forming a fine MIS type FET. Furthermore, since a film can be formed by a deposition method that does not depend on a specific chemical reaction such as a sputtering method or a vapor deposition method, and a high-temperature heat treatment is not essential after the deposition, a wide range of materials (for example, compounds, heat Materials that are weak to the light). Furthermore, the gate sidewall insulating film can be made thinner, the parasitic capacitance can be reduced by reducing the source / drain diffusion layer area, or the parasitic resistance can be reduced by bringing a low-resistance conductor layer closer to the gate. .

As a method for forming the conductor 70, for example, a titanium nitride film is used as a metal to be deposited anisotropically, and wet etching using a mixed solution of ammonia and hydrogen peroxide is used as isotropic etching. be able to. Alternatively, dry etching using chlorine gas can be adopted as the isotropic etching using aluminum as the metal deposited anisotropically.

When the conductor 70 is made of a single material,
The conductor 70 is formed by laminating a plurality of materials as described above.
Can be easily realized by using the method described above. It has been difficult to realize a multilayer structure by the conventional salicide method or selective growth method, but according to the present invention, it is also easy to stack a plurality of types of films. At this time, with respect to the procedure of depositing the conductor film and etching the same, various modifications can be considered within a range that does not change the feature forming the basis of the present invention, but the most suitable method may be selected according to the material used.

Next, as a first example of a method of forming the conductor 70 composed of a plurality of layers, first, the first layer to the n-th layer are sequentially deposited anisotropically, and then the n-th layer to the n-th layer are deposited. A method of sequentially removing up to one layer by isotropic etching will be described. Here, n is an integer of 2 or more. This method is effective when the first to n-th layers can be continuously etched by the same means. As a desirable example corresponding to this method example, there is a method in which the first layer is formed of a titanium film and the second layer is formed of a titanium nitride film. For the isotropic etching of the titanium and titanium nitride stacked films, for example, wet etching using a mixed solution of ammonia and hydrogen peroxide can be employed.

As a second example of a method of forming the conductor 70 having a plurality of layers, first, a first layer is deposited anisotropically.
Next, a method of removing the thin portion of the first layer by isotropic etching, further depositing the second layer anisotropically, and then removing the thin portion of the second layer by isotropic etching will be described.
Thus, the deposition and etching are repeated for each layer. Here, each layer may be composed of a plurality of layers.

The second method example is suitable when the appropriate etching method differs for each layer. As a desirable example corresponding to this method example, a method in which the first layer is formed of a titanium nitride film on titanium, and the second layer is formed of tungsten. The isotropic etching of the titanium / titanium nitride laminated film forming the first layer is, for example, wet etching using a mixed solution of ammonia and hydrogen peroxide, and isotropic etching of tungsten forming the second layer. For example, dry etching using a mixed gas of chlorine and oxygen may be employed.

In a preferred example corresponding to the second method example,
The first layer is formed of a silicon film, the second layer is formed of a titanium nitride film on titanium, and the third layer is formed of tungsten. In this case, the isotropic etching of the silicon film forming the first layer is, for example, dry etching using chlorine gas, and the isotropic etching of the titanium / titanium nitride stacked film forming the second layer is, for example, ammonia and excess. Wet etching using a mixed solution with hydrogen oxide, and isotropic etching of tungsten forming the third layer may be dry etching using a mixed gas of chlorine and oxygen, for example.

As described above, an example has been described in which the layers constituting the conductor layer 70 are always deposited anisotropically. However, when a multilayer film is used, it is not always necessary to deposit all layers anisotropically. For example, the ratio of a certain layer X to the total thickness of the layer is small, and even if the layer X is deposited isotropically, the thickness of the entire layer on the side surface is still the thickness on the top surface in the state where the entire layer is deposited. Layer if it is smaller and can be removed by a subsequent isotropic etch.
X may be deposited isotropically. Alternatively, this also applies to the case where the isotropically deposited lower layer X can be etched using the anisotropically deposited upper layer Y as a mask. That is,
Lower layer X is deposited isotropically, then upper layer Y is deposited anisotropically,
Next, the upper layer Y is isotropically etched to remove a thin portion on the side surface of the step, and then the lower layer X exposed on the side surface of the step is etched only on the exposed portion. For this, it is necessary to have an appropriate etching means for etching only the layer X without etching the layer Y.

As described above, the manufacturing method in the case where the conductor layer 70 is a multilayer film has various modifications, and accordingly, there is a slight difference in the shape at the time of completion. The example is shown in FIGS. In these figures, FIG.
The same reference numerals are given to the same components and elements as those in (c).

FIG. 6 is a cross-sectional view showing the result when the second example of the method of forming a conductor layer composed of a plurality of layers is applied to a two-layer film. In this method, since the layer 71A is etched immediately after the layer 71A is deposited, the layer 71A is formed flat up to the gate side wall 60. Next, the layer 7 is formed on the layer 71A.
2A is formed. On the upper surface of the gate electrode 10, a layer 71
A layer 71B formed with A and a layer 72B formed with the layer 72A are provided.

FIG. 7 is a cross-sectional view showing the result when the first example of the method of forming a conductor layer composed of a plurality of layers is applied to a two-layer film. In this example method, layer 71A and layer 72A are deposited sequentially and then both layers 71A and 72A are etched, so that upper layer 72A is slightly separated from gate sidewall 60 by lower layer 71A.

FIG. 8 is a cross-sectional view showing the result when the first method example is applied as in FIG. This is a result of using etching means in which the progress of etching of the layer 71 is faster than that of the layer 72A. As a result, the layer 71A recedes downward at a portion along the gate side wall.

As described above, the completed structures of the conductor layers 71A and 72A can have various modifications, but all of them can be obtained based on the present invention.

FIGS. 9 and 10 are sectional views showing in detail the method of manufacturing the MIS type FET described with reference to FIG.
10 (a) to 10 (d) and FIGS. 10 (a) to 10 (d) show each step in a stepwise manner.
In this example, the conductor layer is composed of a plurality of layers 75A and 76A, and the lowermost layer 75A is composed of a semiconductor. Many parts in this example are common to those in the first embodiment described with reference to FIG. 1, and therefore, the description will mainly focus on differences from FIG. 1.

As shown in FIG. 9A, a gate electrode 10 and an element isolation insulator 40 are formed on a substrate 50. However, in FIG. 1 (a), the source
In this example, the drain diffusion layer 30 has not been formed yet. Next, as shown in FIG. 9B, an insulating film 60 made of a silicon oxide film, a silicon nitride film, or the like is deposited by a CVD method or the like so as to cover the side surface of the gate electrode 10. Further, as shown in FIG. 9C, the insulating film 60 is anisotropically etched so that the insulating film 60 remains only on the side surface of the gate electrode 1.

Subsequently, as shown in FIG. 9D, a semiconductor layer 75A made of silicon, germanium, or a mixed crystal thereof is differently arranged so that its constituent particles are perpendicularly incident on the substrate 50 from above. Deposits anisotropically. Furthermore,
By removing the semiconductor layer adhered to the gate side wall insulating film 60 using isotropic etching, the semiconductor layer 75A is removed.
And 75B.

Next, as shown in FIG. 10A, at least an impurity is introduced into the semiconductor layer 75A by ion implantation, and the impurity is subsequently activated by heat treatment. Through these steps, the semiconductor layer 75A is doped to a predetermined conductivity type, and at the same time, the introduced impurities are penetrated into the substrate 50, and the source / drain diffusion layers 30 are also doped. Here, the impurity is an n-channel MIS type FET
In the above, arsenic, phosphorus, antimony, etc.
In a channel MIS type FET, p-type boron, boron fluoride, or the like is used, respectively.

Next, as shown in FIG. 10 (b), anisotropic deposition and isotropic etching are again performed to
Form 6A and 76B. Conductor layers 76A and 76B
In general, various metals described above are used. Further, as shown in FIG. 10C, the conductors 75A and 76A are cut into a desired planar shape by using a photolithography method or the like. Next, as shown in FIG. 10D, an interlayer insulating film 100 is deposited on the entire surface of the substrate 50, and then the interlayer insulating film 1 is formed.
After opening the contact hole 80 at a predetermined position of 00, a metal wiring 90 is formed.

In the structure of FIG. 10D, the semiconductor layer 7
Since the contact area between 5A and the conductor layer 76A is large, the parasitic resistance between the source and the drain is reduced. In this example, the semiconductor layer 7 is the lowermost layer of the conductor layer 70A.
Since 5A is used, the semiconductor layer 75A and the source / drain diffusion layer 30 usually need to be doped with impurities of the same conductivity type.

In this embodiment, the impurity introduction process is simplified by simultaneously forming the source / drain diffusion layer 30 and doping the semiconductor layer 75A. In particular, the n-type and p-type MISs are formed on the same substrate. It facilitates the realization of a complementary structure (usually called CMOS) for fabricating a type FET. Source·
In the case where impurities are introduced into the drain diffusion layer 30 and the semiconductor layer 75A in separate steps, that is, if only the n-channel or p-channel FET is taken out and the manufacturing flow shown in FIG. realizable.

First, after protecting the p-type region with a photoresist, n-type source / drain diffusion layers are formed by ion implantation of n-type impurities. Next, after protecting the n-type region with a photoresist, p-type source / drain diffusion layers are formed by ion implantation of p-type impurities. Further, after the p-type region is protected by the photoresist, an n-type impurity is ion-implanted into the semiconductor layer. Subsequently, the n-type region is protected by the photoresist, and then the p-type impurity is ion-implanted into the semiconductor layer. This requires a total of four photolithography steps.

On the other hand, in the present embodiment described with reference to FIGS. 9 and 10, since the formation of the source / drain diffusion layers 30 and the doping of the semiconductor layer 75A are performed simultaneously, the number of lithography steps can be reduced to two. And the manufacturing process is simplified. This example also has an advantage that the source / drain diffusion layer 30 can be formed shallow. In particular, when an impurity is first implanted only into the semiconductor layer 75A and the source / drain diffusion layer 30 is formed by diffusion of the impurity from the semiconductor layer 75A, the depth of the source / drain diffusion layer 30 is reduced The depth can be made shallower than in the case where ions are directly implanted into the substrate 50.

As described above, in each of the above examples to which the present invention is applied, in the case where the salicide method is used by sticking the conductor layer to the source / drain diffusion layers by anisotropic deposition and isotropic etching. Source with a smaller area and lower resistance than
A drain diffusion layer can be obtained, and this can be realized with a higher yield as compared with the selective growth method. In addition, based on the same configuration, the erosion of the substrate is small, and the fine MIS type FET and SOI configuration MIS
A source / drain diffusion layer structure suitable for a type FET can be realized. Further, based on the same configuration, a structure in which the conductor layer on the source / drain diffusion layer extends outside the source / drain diffusion layer can be easily realized. Further, the conductor layer 70A, the conductor layers 71A and 72A, or the conductor layers 75A and 76A
Is extended to the outside of the source / drain diffused layer 30, the parasitic capacitance of the source / drain diffused layer can be reduced without being restricted by the contact hole formation. Further, since the semiconductor layer 75A is used as the lowermost layer of the conductor layer 70A, the semiconductor layer 75A and the source / drain diffusion layers 30 are usually doped with impurities of the same conductivity type.
In particular, the parasitic resistance of the source / drain diffusion layer caused by the contact resistance can be reduced. Further, by simultaneously doping the source / drain diffusion layer 30 and the semiconductor layer 75A, a structure for reducing contact resistance can be easily manufactured in a short process, and a shallow source / drain junction can be easily formed. .

As described above, the present invention has been described based on the preferred embodiment. However, the method of manufacturing the MIS type FET and the semiconductor device of the present invention is not limited to the configuration of the above embodiment. MIS type FETs and semiconductor device manufacturing methods in which various modifications and changes have been made from the configuration of the above embodiment are also included in the scope of the present invention.

[0096]

As described above, according to the present invention,
MIS with low resistance, suitable for miniaturization, easy to manufacture, and suitable for fine type and SOI structure with gate length of about 0.2μm or less
It is possible to obtain a manufacturing method for manufacturing a semiconductor device such as a type FET and such an MIS type FET.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a method for manufacturing an MIS-type FET according to a first embodiment of the present invention, wherein FIGS.

FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing the MIS type FET according to the first embodiment, and FIGS.

FIG. 3 is a plan view corresponding to FIG. 1, wherein (a) to (d) correspond to FIG. 1 (a) to (d), respectively.

FIG. 4 is a plan view corresponding to FIG. 2, wherein (a) to (c) correspond to FIGS. 2 (a) to (c), respectively.

FIG. 5 is a sectional view showing an MIS type FET according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a result when a second example of a method of forming a conductor layer composed of a plurality of layers is applied to a two-layer film.

FIG. 7 is a cross-sectional view showing a result when a first example of a method of forming a conductor layer composed of a plurality of layers is applied to a two-layer film.

FIG. 8 is a cross-sectional view showing a result when the first method example is applied, similarly to FIG. 7;

FIGS. 9A to 9D are cross-sectional views illustrating in detail a method of manufacturing the MIS-type FET described with reference to FIGS. 6A to 6D, wherein FIGS.

10A to 10D are cross-sectional views showing in detail a method of manufacturing the MIS-type FET described with reference to FIG. 6, wherein (a) to (d) show steps in a stepwise manner.

FIGS. 11A to 11D are cross-sectional views illustrating a procedure of manufacturing a MIS-type FET by a conventional salicide method. FIGS.

FIGS. 12A to 12C are cross-sectional views illustrating a procedure for manufacturing a MIS type FET using a conventional SOI substrate, and FIGS.

[Explanation of symbols]

 Reference Signs List 10: Gate electrode 20: Gate insulating film 30: Source / drain diffusion layer 40: Element isolation insulating film 50: Substrate 60: Gate side wall insulating film (side surface insulator) 70: Conductor 71: Various conductor films 72: Various conductor films Body film 75: Semiconductor film 76: Various conductive films 80: Contact hole 90: Metal wiring 100: Interlayer insulating film 110: Planar processing pattern 120: SOI channel 130: SOI embedded insulating film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 301 H01L 21/28 301T 301Z 29/78 301P 301G 29/786 301S 616K 616S 617L F term (reference ) 4M104 AA01 AA09 BB01 BB14 BB20 BB21 BB22 BB25 BB28 BB30 BB32 BB33 BB36 BB40 CC01 DD02 DD04 DD08 DD16 DD17 DD34 DD37 DD64 DD65 EE09 EE15 EE17 FF09 FF18 FF22 GG08 GG09 DG10 EC14 EC15 EC12 EC14 EC15 EC12 EC14 EC12 EC14 EC13 EH01 EH02 EH03 EH08 FA05 FA07 FC11 FC21 5F110 AA02 AA03 BB04 CC02 DD05 DD13 EE01 EE02 EE03 EE04 EE05 EE08 EE09 EE14 EE15 EE32 EE43 EE44 GG02 GG12 HJ01 HJ13 HJ04 HK01 HK21 HK01 HK21 HK01 HK21 HK01 HK02 NN62 NN66 QQ11 QQ17

Claims (9)

[Claims] 1. An MIS type FET having a gate electrode on a substrate and a source diffusion layer and a drain diffusion layer adjacent to the gate electrode via an insulating film, wherein the MIS FET is formed on a side surface of the gate electrode. A gate sidewall insulating film covering each part of the source diffusion layer and the drain diffusion layer; contacting at least a part of a region of the source diffusion layer and the drain diffusion layer other than below the gate sidewall insulating film; First and second extending from the contact position on an insulator adjacent to the source diffusion layer and the drain diffusion layer, respectively;
An MIS type FET comprising: 2. The MIS type FET according to claim 1, wherein upper surfaces of the first and second conductor layers are located farther from the substrate than lower surfaces of the gate electrodes. 3. The method according to claim 1, wherein the first and second conductor layers are each composed of 2
3. The MIS type FET according to claim 1, wherein the MIS type FET is formed of a laminated film made of at least one kind of different materials. 4. The MIS type FET according to claim 3, wherein a lowermost layer in the stacked film is made of a semiconductor having the same conductivity type as the source diffusion layer and the drain diffusion layer. 5. An interlayer insulating film deposited on the substrate including the gate electrode, the source diffusion layer, the drain diffusion layer, the gate sidewall insulating film, and the conductor layer; A contact hole communicating with the corresponding first and second conductor layers from the metal wire is formed in the interlayer insulating film, and formed in the contact hole. The MIS type FET according to any one of claims 1 to 4, wherein at least a part of the bottom surface of the metal plug is located outside the source diffusion layer and the drain diffusion layer. 6. A step of forming a step on a substrate; a step of anisotropically depositing a conductor on the substrate, and attaching the conductor to a top surface of the substrate thicker than a side surface of the step; A method for manufacturing a semiconductor device, comprising: a step of removing the conductor from a side surface of the step by isotropic etching; and a step of processing the conductor remaining on the substrate into a desired planar shape. . 7. A step of forming a gate electrode on a substrate, a step of forming a side insulator covering a side surface of the gate electrode, and anisotropically depositing a conductor on the substrate, Attaching the conductor thicker to the upper surface of the substrate than to the side surface, removing the conductor from the side surface of the gate electrode by isotropic etching, and removing the conductor remaining on the substrate by a desired amount. Processing the semiconductor device into a planar shape. 8. The method according to claim 7, wherein at least one of the step of attaching the conductor and the step of removing the conductor is performed a plurality of times. 9. A step of forming a gate electrode on a substrate, a step of forming a side insulator covering a side surface of the gate electrode, and anisotropically depositing a semiconductor on the substrate to form a side surface of the gate electrode. Attaching the semiconductor thicker to the upper surface of the substrate than removing the semiconductor from a side surface of the gate electrode by isotropic etching; and a part of the substrate contacting the semiconductor and the lower surface of the semiconductor. A method of manufacturing a semiconductor device, comprising: introducing an impurity into a semiconductor; and processing the semiconductor into a desired planar shape.