JP2009152486A - Manufacturing method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can reduce the resistance of an S/D layer of a MOS transistor formed on an SOI substrate and reduce its parasitic capacity, and to provide the semiconductor device. <P>SOLUTION: The method of forming the MOS transistor 50 on the SOI substrate 10 which has an Si layer 3 formed on an Si substrate 1 with an insulating film 2 interposed and an insulating film 4 formed on the Si substrate 1 while enclosing the Si layer 3 in plan view, the insulating film 4 being formed thicker than the insulating film 2 includes a step of forming a gate electrode 6 on the Si layer 3 with a gate insulating film 5 interposed and a step of forming S/D layers 20 on both sides of the gate electrode 6, the step of forming the S/D layers 20 including a step of forming an impurity layer 7 by introducing an impurity into the Si layer 3 in end areas disposed on both sides of an area where the gate electrode 6 is formed and a step of forming a conductive film 8 coming into contact with the impurity layer 7 from over the impurity layer 7 to over the insulating film 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, miniaturization and high integration of semiconductor devices are becoming more and more advanced. With the progress of miniaturization and high integration, there is a demand for further thinning of the SOI layer (that is, Si layer) and the Box layer (that is, insulating layer) in a semiconductor substrate having an SOI (Silicon on Insulator) structure. Yes. For example, according to the ITRS roadmap (International Technology Roadmap for Semiconductor), the film thickness of the SOI layer is set to about 80 nm in the case of PD (Partially-Depleted) -SOI even in the gate length 90 nm generation. In the case of SOI (Fully-Depleted), a thin film of about 30 nm is required. In the 90 nm generation, the Box layer is also required to be thinned to 70 to 80 nm for the purpose of suppressing the single channel effect and avoiding heat generation. For this reason, there is a problem that the diffusion layer resistance of the source or drain (hereinafter also referred to as S / D layer) is lowered and the parasitic capacitance is increased.

  As a countermeasure against such a problem, a method (so-called elevated) in which an S / D layer is lifted by selective epitaxial growth is conventionally known for a MOS field effect transistor (hereinafter referred to as a MOS transistor) having an SOI structure. According to this method, since the S / D layer becomes a thick film, the diffusion layer resistance of the S / D layer can be lowered to some extent. However, since the BOX layer below the source / drain region of the SOI layer is still thin, the increase in parasitic capacitance cannot be solved. In addition, this method has a problem that the manufacturing cost tends to be high.

On the other hand, Patent Document 1 discloses a method (so-called SBSI method) in which an SOI structure is partially formed on a bulk Si substrate. In the SBSI method, a Si layer / SiGe layer is sequentially formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in etching rate between Si and SiGe. A cavity is formed between the layers, and an insulating layer is formed in the cavity. Thereby, an SOI structure composed of the insulating layer and the Si layer is formed on the Si substrate. According to the above SBSI method, the film thickness of the SOI layer (Si layer) can be accurately controlled, and the film thickness can also be reduced. Further, since a special manufacturing method such as SIMOX and bonding is not required, there is an advantage that the SOI structure can be formed at low cost.
JP 2005-354024 A

However, even when the above SBSI method is used, the problem of the diffusion layer resistance and parasitic capacitance of the S / D layer cannot be sufficiently solved. Further, in the SBSI method, the planar size of the SOI structure that can be formed on the Si substrate is limited, and it is difficult to form a MOS transistor having a long channel length L, for example.
Therefore, the present invention has been made in view of such circumstances, and the resistance of the S / D layer of the MOS transistor formed on the SOI substrate can be reduced and the parasitic capacitance can be reduced. An object of the present invention is to provide a method of manufacturing a semiconductor device and a semiconductor device.

  [Invention 1 and 2] A method of manufacturing a semiconductor device according to Invention 1 includes a semiconductor layer formed on a semiconductor substrate via a first insulating film, and formed on the semiconductor substrate so as to surround the semiconductor layer in a plan view. A method for manufacturing a MOS field effect transistor on an SOI substrate having a thickness greater than that of the first insulating film, wherein the second insulating film is thicker than the first insulating film. A step of forming a gate electrode on a layer through a gate insulating film and a step of forming a source or drain on both sides of the gate electrode, wherein the step of forming the source or drain is formed by the gate electrode A step of introducing an impurity into the semiconductor layer in the end region located on both sides of the region to be formed to form an impurity layer, and a conductive film in contact with the impurity layer from the impurity layer to the second insulating film. Over Forming, it is characterized in that it has a.

A method for manufacturing a semiconductor device according to a second aspect is characterized in that, in the method for manufacturing a semiconductor device according to the first aspect, in the step of forming the conductive film, the conductive film is formed thicker than the semiconductor layer.
Here, the “semiconductor substrate” is, for example, a bulk silicon SOI substrate. In addition, the “gate electrode” and the “conductive film” are, for example, a semiconductor film or a metal film having conductivity by including impurities. An example of the semiconductor film is a polysilicon (Poly-Si) film.

  According to the method for manufacturing a semiconductor device of the first and second aspects, the source or drain (hereinafter referred to as S / D layer) can be constituted by the impurity layer and the conductive film. A metal, a semiconductor, or silicide can be used for the conductive film. In addition, the conductive film can be formed thicker than the semiconductor layer, or the impurity concentration of the conductive film can be higher than that of the impurity layer, whereby the resistance of the conductive film can be reduced. Further, since the second insulating film is thicker than the first insulating film, the parasitic capacitance of the conductive film can be made smaller than that of the impurity layer. Therefore, the resistance of the entire S / D layer can be reduced and the parasitic capacitance can be reduced.

[Invention 3] The method for manufacturing a semiconductor device according to Invention 3 is the method for manufacturing a semiconductor device according to Invention 1 or Invention 2, in which insulating protection is provided on the side surface and the upper surface of the gate electrode before the step of forming the conductive film. A step of forming a film; and a step of exposing a surface of the semiconductor layer in the end region, wherein the step of forming the conductive film includes forming the protective film and forming the end region in the end region. A step of forming a semiconductor film on the SOI substrate with the surface of the semiconductor layer exposed; and introducing impurities into the semiconductor film to make the polarity of the semiconductor film the same conductivity type as the impurity layer And a step of etching the semiconductor film to form the semiconductor film into the shape of the conductive film.
According to such a method, the upper surface and the side surface of the gate electrode are protected by the protective film when the semiconductor film is etched (that is, patterned). Therefore, even if the opening position of the mask is slightly shifted, the protective film functions as an etching stopper, so that the gate electrode can be prevented from being unintentionally cut.

[Invention 4] The method for manufacturing a semiconductor device according to Invention 4 is the method for manufacturing a semiconductor device according to Invention 1 or 2, wherein the surface of the semiconductor layer in the end region is exposed before the step of forming the gate electrode. The step of forming the gate electrode and the step of forming the conductive film in a state where the gate insulating film is formed and the surface of the semiconductor layer in the end region is exposed. A step of forming a semiconductor film on the SOI substrate, a step of introducing impurities into the semiconductor film to make the polarity of the semiconductor film the same conductivity type as the impurity layer, and etching the semiconductor film, The step of forming the semiconductor film in the shape of the gate electrode and the shape of the conductive film is shared.
According to such a method, the gate electrode and the conductive film can be formed at the same time, and the semiconductor film forming process and the patterning process can be performed only once. Therefore, it can be expected to reduce the manufacturing cost of the semiconductor device.

  [Invention 5] The manufacturing method of a semiconductor device of Invention 5 further includes the step of forming the SOI substrate in the manufacturing method of the semiconductor device of Inventions 1 to 4, wherein the step of forming the SOI substrate includes the semiconductor substrate. A step of sequentially forming a sacrificial semiconductor layer and the semiconductor layer thereon; a step of etching the semiconductor layer and the sacrificial semiconductor layer to form a first groove penetrating the semiconductor layer and the sacrificial semiconductor layer; Forming a first insulating layer in at least the first groove and supporting the semiconductor layer by the first insulating layer; and etching the at least the semiconductor layer to expose the sacrificial semiconductor layer. A step of forming a groove, a step of forming a cavity between the semiconductor layer and the semiconductor substrate by etching the sacrificial semiconductor layer through the second groove, and the cavity Forming a first insulating film and embedding the cavity, and after embedding the cavity, forming a second insulating layer in the second groove and embedding the second groove. The second insulating film includes the first insulating layer and the second insulating layer.

According to such a method, the so-called SBSI method is used, and a special manufacturing method such as SIMOX or bonding is not required when forming the SOI structure, so that the manufacturing cost of the SOI substrate can be suppressed. Can do.
In the SBSI method, there is a limit to the planar size of the SOI structure including the first insulating film and the semiconductor layer. However, according to the present invention, an electrode (for example, a contact wiring made of aluminum or a plug electrode made of tungsten) for transmitting / receiving a signal to the S / D layer is arranged on the conductive film. Therefore, the portion (that is, the impurity layer) formed in the semiconductor layer in the S / D layer can be reduced. Therefore, the length of the channel region (that is, the channel length L) can be increased by the size of the impurity layer.

[Invention 6]
A semiconductor device according to a sixth aspect of the present invention is a semiconductor device comprising an SOI substrate and a MOS field effect transistor formed on the SOI substrate, wherein the SOI substrate includes the semiconductor substrate and a first insulating film on the semiconductor substrate. And a second insulating film that is thicker than the first insulating film and formed on the semiconductor substrate so as to surround the semiconductor layer in plan view, The MOS field effect transistor has a gate electrode formed on the semiconductor layer via the gate insulating film, and a source or drain formed on both sides of the gate electrode, and the source or drain is An impurity layer formed in the semiconductor layer in an end region located on both sides of the gate electrode, and a conductive film formed in contact with the impurity layer and over the impurity layer to the second insulating film And it is characterized in that it comprises a.
According to the semiconductor device of the invention 6, the resistance of the entire S / D layer can be reduced, and the parasitic capacitance can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) First Embodiment (Configuration of Semiconductor Device)
1 and 2 are schematic views showing a configuration example of the semiconductor device according to the first embodiment of the present invention. FIG. 1 is a plan view, and FIG. 2 is a view taken along line A1-A′1 in FIG. FIG.

As shown in FIGS. 1 and 2, this semiconductor device includes an SOI substrate 10 and a plurality of MOS transistors 50 formed on the SOI substrate 10. As shown in FIG. 2, the SOI substrate 10 includes a bulk silicon (Si) substrate 1, a single crystal Si layer 3 formed on the Si substrate 1 with an insulating film 2 interposed therebetween, and the Si layer 3 in plan view. And an insulating film 4 formed on the Si substrate 1 so as to be surrounded by In this SOI substrate 10, a so-called SOI structure is formed by the insulating film 2 and the Si layer 3. As shown in FIG. 2, the insulating film 4 is formed thicker than the insulating film 2. The insulating films 2 and 4 are made of, for example, a SiO ₂ film, a Si ₃ N ₄ film, or a film in which these are laminated. Hereinafter, the insulating film 2 is also referred to as a BOX layer, and the Si layer 3 is also referred to as an SOI layer.

On the other hand, the MOS transistor 50 includes a gate electrode 6 formed on the Si layer 3 via the gate insulating film 5 and S / D layers 20 formed on both sides of the gate electrode 6. The S / D layer 20 includes an impurity layer 7 formed on the Si layer 3 in the end region located on both sides of the gate electrode 6 and a conductive film 8 in contact with the impurity layer 7.
As shown in FIG. 2, the conductive film 8 is formed from the impurity layer 7 to the insulating film 4 so as to be separated from the gate electrode 6 (that is, separated from the gate electrode 6). The portion is in direct contact with the impurity layer 7.

  Here, the conductive film 8 is made of, for example, a metal film or a polysilicon (Poly-Si) film having the same conductivity type as the impurity layer 7. That is, when the impurity layer 7 is n-type, the conductive film 8 is made of, for example, an n-type polysilicon film. When the impurity layer 7 is p-type, the conductive film 8 is made of, for example, a p-type polysilicon film. As described above, when the conductive film 8 is formed of a polysilicon film having the same conductivity type as the impurity layer 7, the potential barrier at the contact interface between the conductive film 8 and the impurity layer 7 becomes minute. For this reason, the above contact interface can be treated as having almost no resistance.

  The MOS transistor 50 has an FD (Fully Depleted) -SOI structure or a fine PD (Partial Depleted) -SOI structure in the channel region. In the channel region of the FD-SOI structure or the fine PD-SOI structure, both the SOI layer and the BOX layer are thin. For example, the thickness of the Si layer 3 (that is, the SOI layer) is 20 to 100 nm, and the thickness of the insulating film 2 (that is, the BOX layer) is 100 nm or less. For this reason, a short channel effect can be suppressed and a good subthreshold characteristic can be shown.

  Further, the heat generation in the channel region can be released through this thin BOX layer. Furthermore, the conductive film 8 forming a part of the S / D layer 20 is formed on the thick insulating film 4 and has a thickness of, for example, 100 to 500 nm. That is, the conductive film 8 can be set thicker than the Si layer 3 (that is, the SOI layer). Therefore, the resistance of the entire S / D layer 20 can be reduced and the parasitic capacitance can be reduced. Next, a method for manufacturing a semiconductor device including the MOS transistor 50 will be specifically described.

(About manufacturing method of semiconductor device)
3 to 19 are views showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 3A to 19A are plan views, and FIGS. (B) is sectional drawing when FIG. 3 (a)-FIG. 19 (a) are each cut | disconnected by A3-A'3-A19-A'19 line, FIG.3 (c)-FIG.19 (c) are figures. It is sectional drawing when 3 (a)-FIG. 19 (a) are each cut | disconnected by the B3-B'3-B19-B'19 line | wire.

3A to 3C, first, a single crystal silicon buffer (Si-buffer) layer (not shown) is formed on a bulk Si substrate 1, and single crystal silicon germanium (SiGe) is formed thereon. A layer 11 is formed, and a single crystal silicon (Si) layer 3 is formed thereon. The Si-buffer layer, the SiGe layer 11, and the Si layer 3 are continuously formed by, for example, an epitaxial growth method. The thickness of the Si layer 3 is, for example, 20 to 100 nm, and the thickness of the SiGe layer 11 is, for example, 100 nm or less. Next, an SiO ₂ film 13 is formed on the entire upper surface of the Si substrate 1, and a silicon nitride (Si ₃ N ₄ ) film 15 is formed thereon. The SiO ₂ film 13 and the Si ₃ N ₄ film 15 are formed by, for example, a CVD method (Chemical Vapor Deposition) method.

Next, as shown in FIGS. 4A to 4C, the Si ₃ N ₄ film 15, the SiO ₂ film 13, the Si layer 3, the SiGe layer 11, and the Si-buffer are used by using a photolithography technique and an etching technique. Each layer (not shown) is partially etched. Thus, the support hole h having the Si substrate 1 as the bottom surface is formed in a region overlapping with the element isolation region (that is, the region where the SOI structure is not formed) in plan view. In this etching step, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

Next, as shown in FIGS. 5A to 5C, for example, a SiO ₂ film 17 is formed on the entire surface of the Si substrate 1 so as to fill the support hole h. This SiO ₂ film 17 is formed by, for example, a CVD method. Then, as shown in FIGS. 6A to 6C, the SiO ₂ film 17, the Si ₃ N ₄ film 15, the SiO ₂ film 13, the Si layer 3, and the SiGe layer 11 using a photolithography technique and an etching technique. And the Si-buffer layer (not shown) are partially etched sequentially. Thus, the support 18 composed of the SiO ₂ film 17, the Si ₃ N ₄ film 15 and the SiO ₂ film 13 is formed, and the groove H having the Si substrate 1 as the bottom surface is formed in a region overlapping the element isolation region in plan view. To do. In the step of forming the groove H, the etching may be stopped on the surface of the Si substrate 1, or the Si substrate 1 may be over-etched to form a recess.

  Next, for example, a hydrofluoric acid solution is brought into contact with the side surfaces of the Si layer 3 and the SiGe layer 11 through the groove H, and the SiGe layer 11 is selectively etched and removed. Thereby, as shown in FIGS. 7A to 7C, a cavity 19 is formed between the Si layer 3 and the Si substrate 1. In wet etching using a fluorinated nitric acid solution, the etching rate of SiGe is higher than that of Si (that is, the etching selectivity with respect to Si is large), so only the SiGe layer is etched and removed while leaving the Si layer 3. Is possible. After the formation of the cavity 19, the upper surface and the side surface of the Si layer 3 are supported by the support 18.

In the step of etching the SiGe layer 11, hydrofluoric acid overwater, ammonia overwater, or acetic acid overwater may be used instead of the hydrofluoric acid solution. Overwater is hydrogen peroxide water. Also in this case, since the etching rate of SiGe is larger than that of Si, the SiGe layer can be selectively removed.
Next, in FIGS. 8A to 8C, the Si substrate 1 is thermally oxidized to form SiO ₂ films 21 on the lower surface of the Si layer 3 facing the inside of the cavity 19 and the upper surface of the Si substrate 1, respectively. To do. Subsequently, as shown in FIGS. 9A to 9C, for example, a SiO ₂ film 23 is formed on the entire upper surface of the Si substrate 1 by, for example, a CVD method to completely fill the cavity. As a result, a BOX layer composed of the SiO ₂ films 21 and 23 (that is, the insulating film 2 shown in FIG. 2) is completed. The thickness of the BOX layer is, for example, 100 nm or less.

Next, in FIGS. 10A to 10C, isotropic etching is performed on the SiO ₂ film 23, followed by anisotropic etching. The isotropic etching may be either dry etching or wet etching. Thus, the SiO ₂ film 23 is removed from the side surface of the Si layer 3 and the Si substrate 1 other than the cavity. The above isotropic etching is performed to remove the SiO ₂ film 23 from the side surface of the Si layer 3 and the like, but this also slightly removes the SiO ₂ film 23 in a portion slightly inside from the entrance of the cavity. Will be. Note that the steps of FIGS. 10A to 10C may not be performed, that is, the process may proceed to the step of FIG. 11 while the SiO ₂ film 23 remains.

Next, as shown in FIGS. 11A to 11C, for example, a SiO ₂ film 25 is formed on the entire surface of the Si substrate 1 by, for example, a CVD method to fill the groove H. Then, the SiO ₂ film covering the entire surface of the Si substrate 1 is removed while being planarized by, for example, CMP (Chemical Mechanical Polish), and the surface of the Si ₃ N ₄ film 15 is removed as shown in FIGS. To expose. In this CMP, the Si ₃ N ₄ film 15 functions as a stopper for the polishing pad. Subsequently, the Si ₃ N ₄ film 15 is removed by wet etching, for example, with hot phosphoric acid, and the SiO ₂ film 13 is removed by wet etching, for example, using a diluted hydrofluoric acid solution. As shown in (c), the surface of the Si layer 3 is exposed. Thus, the SOI substrate 10 having the SOI structure composed of the SiO ₂ films 21 and 23 (that is, the BOX layer) and the Si layer (that is, the SOI layer) 3 is completed on the bulk Si substrate 1.

Next, the MOS transistor 50 shown in FIGS. 1 and 2 is formed on the SOI substrate 10 described above. That is, as shown in FIGS. 14A to 14C, the gate insulating film 5 is formed on the surface of the Si layer 3. The gate insulating film 5 is, for example, a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON) formed by thermal oxidation, or a High-k material film. Next, a polysilicon (poly-Si) film is formed on the entire surface of the SOI substrate 10 on which the gate insulating film 5 is formed. The polysilicon film is formed by, for example, a CVD method. Here, impurities are introduced into the polysilicon film by ion implantation or in-situ to make the polysilicon film conductive.

  Specifically, when a pMOS transistor is formed on the SOI substrate 10, p-type impurities such as boron are introduced into the polysilicon film by ion implantation or in-situ to have p-type conductivity. Make it. Further, when an nMOS transistor is formed on the SOI substrate 10, an n-type conductivity such as phosphorus or arsenic is introduced into the polysilicon film by ion implantation or in-situ, etc., so as to have n-type conductivity. . Further, when both the pMOS transistor and the nMOS transistor are formed on the SOI substrate 10, for example, the pMOS transistor is formed in a state where the entire region where the nMOS transistor is formed (hereinafter referred to as nMOS region) is covered with a photoresist. A p-type impurity is ion-implanted into a polysilicon film in a region to be formed (hereinafter referred to as a pMOS region), and then an n-type impurity is implanted into the polysilicon film in the nMOS region with the entire pMOS region covered with a photoresist After ion implantation, the entire SOI substrate 10 is subjected to heat treatment to simultaneously diffuse p-type impurities and n-type impurities. As a result, the polysilicon film in the pMOS region can have p-type conductivity, and the polysilicon film in the nMOS region can have n-type conductivity.

Next, for example, a SiO ₂ film is formed on the polysilicon film. Then, the SiO ₂ film and the polysilicon film are sequentially partially etched using a photolithography technique and an etching technique. Thereby, as shown in FIGS. 15A to 15C, the gate electrode 6 is formed on the gate insulating film 5 in the channel region.
Next, impurities are ion-implanted into the Si layer 3 exposed from under the SiO ₂ film 31 and the gate electrode 6 and heat treatment is performed to form an LDD (Lightly Doped Drain) layer 33. Here, when the p-type LDD layer 33 is formed, a p-type impurity such as boron is ion-implanted into the Si layer 3 using the SiO ₂ film 31 and the gate electrode 6 as a mask. When the n-type LDD layer 33 is formed, n-type impurities such as phosphorus or arsenic are ion-implanted into the Si layer 3 using the SiO ₂ film 31 and the gate electrode 6 as a mask. Further, when the p-type LDD layer 33 is formed on the Si layer 3 in the pMOS region and the n-type LDD layer 33 is formed on the Si layer 3 in the nMOS region, for example, the entire nMOS region is covered with a photoresist. In this state, p-type impurities are ion-implanted into the Si layer 3 in the pMOS region, and then n-type impurities are ion-implanted into the Si layer 3 in the nMOS region with the entire pMOS region covered with a photoresist. The entire 10 is subjected to heat treatment to simultaneously diffuse p-type impurities and n-type impurities. Thereby, the n-type LDD layer 33 and the p-type LDD layer 33 can be formed simultaneously.

Next, for example, a SiO ₂ film is formed on the Si layer 3, and this SiO ₂ film is etched back. The formation of the SiO ₂ film is performed by, for example, a CVD method. As a result, as shown in FIGS. 16A to 16C, sidewalls 35 made of a SiO ₂ film are formed on the side surfaces of the gate electrode 6. In the step of forming the sidewall 35, the gate insulating film 5 is etched in the end regions 36 located on both sides of the gate electrode 6 to expose the surface of the Si layer 3 (ie, the LDD layer 33).

  Next, as shown in FIGS. 17A to 17C, on the SOI substrate 10 so as to be in direct contact with the surface of the Si layer 3 (that is, the LDD layer 33) in the end region 36. A polysilicon film 37 is formed on the entire surface. The polysilicon film 37 has a thickness of, for example, 100 to 500 nm, and is formed by, for example, a CVD method. Here, the polysilicon film 37 is preferably formed thicker than the Si layer 3.

Next, the polysilicon film 37 is partially etched using the resist pattern as a mask, and as shown in FIGS. 18A to 18C, the Si layer 3 (that is, the LDD layer 33) on both sides of the sidewall 35 is obtained. ) The polysilicon film 37 is left over the SiO ₂ film 17 and the polysilicon film 37 is removed from other portions. Thereby, the polysilicon film 37 is separated into the source side and the drain side with the gate electrode 6 interposed therebetween.

  Next, as shown in FIGS. 19A to 19C, impurities are ion-implanted into the polysilicon film and subjected to heat treatment to form the conductive film 8 made of the polysilicon film and the impurity layer 7 as well. . Here, not only the polysilicon film but also the Si layer 3 (that is, the LDD layer 33) in direct contact with the polysilicon film is thermally diffused to form the impurity layer 7 having an impurity concentration higher than that of the LDD layer 33. To do. In this way, the S / D layer 20 composed of the impurity layer 7 and the conductive film 8 is formed.

  19A to 19C, when the p-type S / D layer 20 is formed, p-type impurities such as boron are ion-implanted into the polysilicon film. Further, when the n-type S / D layer 20 is formed, an n-type impurity such as phosphorus or arsenic is ion-implanted into the polysilicon film. Further, when the p-type S / D layer 20 is formed in the pMOS region and the n-type S / D layer 20 is formed in the nMOS region, for example, the pMOS region with the entire nMOS region covered with a photoresist. P-type impurities are ion-implanted into the polysilicon film, and then the n-type impurities are ion-implanted into the polysilicon film in the nMOS region in a state where the entire pMOS region is covered with the photoresist. To diffuse the p-type impurity and the n-type impurity simultaneously. Thereby, the p-type S / D layer 20 and the n-type S / D layer 20 can be formed simultaneously.

  In the step of forming the S / D layer 20, the impurity concentration is uniform from the upper side of the conductive film 8 to the lower side of the impurity layer 7 in a sectional view (that is, the impurity concentration of the conductive film is N, When the impurity concentration of the layer 7 is N ′, N≈N ′), ion implantation conditions, heat treatment conditions, and the like are set. Alternatively, ion implantation conditions, heat treatment conditions, and the like may be set so that the impurity concentration of the conductive film 8 is higher than that of the impurity layer 7 (that is, N> N ′). When N> N ′, it is assumed that the conductivity of the impurity layer 7 is sufficiently ensured.

Next, an interlayer insulating film (not shown) is formed on the entire surface of the SOI substrate 10 by CVD. This interlayer insulating film is, for example, a silicon oxide film. Then, the surface of the interlayer insulating film is planarized by, for example, CMP. Next, the interlayer insulating film is partially etched using a photolithography technique and an etching technique. Thus, contact holes are formed on the gate electrode 6 and the conductive film 8, respectively.
Thereafter, a plug electrode made of a refractory metal such as aluminum (Al) wiring or tungsten (W) is formed in the contact hole, whereby the gate electrode 6 and the S / D layer 20 are drawn on the interlayer insulating film. . Thus, the SOI structure MOS transistor 50 is completed.

As described above, according to the first embodiment of the present invention, the S / D layer 20 can be configured by the impurity layer 7 and the conductive film 8. Further, the conductive film 8 can be formed thicker than the Si layer 3 and the impurity concentration of the conductive film 8 can be made higher than that of the impurity layer 7, thereby reducing the resistance of the conductive film 8. it can. Further, SiO ₂ film 21 and 23 (i.e., the insulating film 2) SiO ₂ film 17 than (i.e., the insulating film 4) for thicker towards, be made smaller than the impurity layer 7 parasitic capacitance of the conductive film 8 it can. Therefore, the resistance of the entire S / D layer 20 can be reduced and the parasitic capacitance can be reduced.

Further, according to the first embodiment of the present invention, the so-called SBSI method is used, and a special manufacturing method such as SIMOX or bonding is not required when forming the SOI structure. The manufacturing cost can be reduced.
Furthermore, in the SBSI method, there is a limit to the planar size of a so-called SOI structure composed of the insulating film 2 and the Si layer 3. However, according to the present invention, since the Al wiring or the plug electrode can be disposed on the conductive film 8, the portion (that is, the impurity layer 7) formed in the Si layer 3 in the S / D layer 20 is formed. Can be small. Therefore, the channel region can be enlarged by the amount that the impurity layer 33 is reduced. As a result, for example, as shown in FIG. 1, a MOS transistor 50 having a long channel length L and a long channel width W can be formed on the SOI substrate 10.

In the first embodiment, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, the SiGe layer 11 corresponds to the “sacrificial semiconductor layer” of the present invention, and the Si layer 3 corresponds to the “semiconductor layer” of the present invention. is doing. The SiO ₂ films 21 and 23 (that is, the insulating film 2) correspond to the “first insulating film” of the present invention, and the SiO ₂ films 17 and 25 (that is, the insulating film 4) correspond to the “second insulating film” of the present invention. Corresponds to "membrane". Further, the SiO ₂ film 17 corresponds to the “first insulating layer” of the present invention, and the SiO ₂ film 25 corresponds to the “second insulating layer” of the present invention. The SiO ₂ film 31 and the sidewall 35 correspond to the “protective film” of the present invention. Further, the support hole h corresponds to the “first groove” of the present invention, and the groove H corresponds to the “second groove” of the present invention.

(2) Second Embodiment In the first embodiment described above, the case where the gate electrode 6 and the conductive film 8 are formed of separate polysilicon films has been described, but the present invention is not limited to this. For example, the gate electrode 6 and the conductive film 8 may be formed of the same polysilicon. In the first embodiment described above, the MOS transistor 50 is formed such that the longitudinal direction of the gate electrode 6 in plan view is orthogonal to the longitudinal direction of the SOI layer in plan view (that is, the AA ′ line). However, the present invention is not limited to this. For example, the MOS transistor 50 may be formed so that the longitudinal direction of the gate electrode 6 in plan view is parallel to the line AA ′. In the second embodiment, these points will be described.

  20 to 23 are views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIGS. 20 (a) to 23 (a) are plan views, and FIGS. 20 (b) to 23. (B) is sectional drawing when FIG. 20 (a)-FIG. 23 (a) are each cut | disconnected by A20-A'20-A23-A'23 line, FIG.20 (c)-FIG.23 (c) are figures. It is sectional drawing when 20 (a)-FIG. 23 (a) are each cut | disconnected by B20-B'20-B23-B'23 line | wire.

  20A to 20C, the steps up to the step of forming the gate insulating film 5 are the same as those in FIGS. 3 to 14 of the first embodiment. In the second embodiment, as shown in FIGS. 20A to 20C, both sides of the region where the gate electrode is formed by partially etching the gate insulating film 5 by the photolithography technique and the etching technique. The surface of the Si layer 3 in the end region 51 located at is exposed. In this etching process, the gate insulating film 5 is continuously left on the Si layer 3 in the channel region and on the Si layer 3 in the region to be the LDD layer.

  Next, as shown in FIGS. 21A to 21C, for example, a polysilicon film 53 is formed on the entire surface of the SOI substrate 10. As a result, in the end region 51, the Si layer 3 and the polysilicon film 53 are in direct contact. Then, impurities are ion-implanted into the polysilicon film 53 and subjected to heat treatment to introduce impurities into the polysilicon film 53 and the Si layer 3 that is in direct contact with the polysilicon film 53. Thereby, the polysilicon film 53 is made conductive and the impurity layer 7 is formed.

  Here, when forming a pMOS transistor, a p-type impurity such as boron is ion-implanted into the polysilicon film 53 and heat treatment is performed to form the p-type polysilicon film 53 and the p-type impurity layer 7 is formed. Form. When forming an nMOS transistor, an n-type impurity such as phosphorus or arsenic is ion-implanted into the polysilicon film 53 and subjected to heat treatment to form the n-type polysilicon film 53 and the n-type impurity layer 7. Form. Further, when both the pMOS transistor and the nMOS transistor are formed, for example, a p-type impurity is ion-implanted into the polysilicon film 53 in the pMOS region in a state where the entire nMOS region is covered with a photoresist, and then the entire pMOS region is formed. Then, n-type impurities are ion-implanted into the polysilicon film 53 in the nMOS region with the photoresist covered, and then heat treatment is performed on the entire SOI substrate 10 to simultaneously diffuse the p-type impurities and the n-type impurities. Thereby, the p-type polysilicon film 53, the p-type impurity layer 7, the n-type polysilicon film 53, and the n-type impurity layer 7 can be formed simultaneously.

Next, as shown in FIGS. 22A to 22C, the polysilicon film 53 is partially etched by photolithography and etching techniques. Thereby, the gate electrode 6 is formed on the gate insulating film 5 in the channel region, and at the same time, the conductive film 8 is formed from the impurity layer 7 to the SiO ₂ film 25. In this etching process, the polysilicon film is removed from the Si layer 3 in the region to be the LDD layer, and the surface of the gate insulating film 5 is exposed in the region.

  Next, using the etched polysilicon film (that is, the gate electrode 6 and the conductive film 8) as a mask, impurities are ion-implanted into the Si layer 3 and heat treatment is performed to form the LDD layer 33. Here, when the p-type LDD layer 33 is formed, a p-type impurity such as boron is ion-implanted into the Si layer 3. When the n-type LDD layer 33 is formed, an n-type impurity such as phosphorus or arsenic is ion-implanted into the Si layer 3. Further, when the p-type LDD layer 33 is formed on the Si layer 3 in the pMOS region and the n-type LDD layer 33 is formed on the Si layer 3 in the nMOS region, for example, the entire nMOS region is covered with a photoresist. In this state, p-type impurities are ion-implanted into the Si layer 3 in the pMOS region, and then n-type impurities are ion-implanted into the Si layer 3 in the nMOS region with the entire pMOS region covered with a photoresist. The whole 10 is subjected to a heat treatment to anneal the p-type impurity and the n-type impurity simultaneously. Thereby, the p-type LDD layer 33 and the n-type LDD layer 33 can be formed simultaneously. In this step, since the gate electrode 6 is used as a mask, the LDD layer 33 can be formed in a self-aligning manner.

Thereafter, as shown in FIGS. 23A to 23C, an interlayer insulating film 55 is formed on the entire upper surface of the SOI substrate 10 by a CVD method. The interlayer insulating film 55 is, for example, a SiO ₂ film or a Si ₃ N ₄ film. The interlayer insulating film 55 fills a gap between the gate electrode 6 and the conductive film 8.
The subsequent steps are the same as those in the first embodiment. That is, a contact hole is formed in the interlayer insulating film 55. Then, a plug electrode made of an Al wiring or a refractory metal film such as tungsten (W) is formed in the contact hole, and the gate electrode 6 and the conductive film 8 are drawn out on the interlayer insulating film 55. As a result, the SOI structure MOS transistor 50 is completed on the SOI substrate 10.

  Thus, according to the second embodiment of the present invention, as in the first embodiment, the resistance of the entire S / D layer 20 including the conductive film 8 can be reduced and the parasitic capacitance can be reduced. Can do. Moreover, since the SBSI method is used, the manufacturing cost of the SOI substrate 10 can be suppressed. Furthermore, the impurity layer 7 formed in the Si layer 3 can be reduced, and the channel region can be increased accordingly. As a result, for example, as shown in FIG. 1, a MOS transistor having a long channel length L and a long channel width W can be formed on the SOI substrate 10.

In the second embodiment, similarly to the first embodiment, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, the SiGe layer 11 corresponds to the “sacrificial semiconductor layer” of the present invention, and the Si layer 3 corresponds to the present invention. This corresponds to the “semiconductor layer”. The SiO ₂ films 21 and 23 (that is, the insulating film 2) correspond to the “first insulating film” of the present invention, and the SiO ₂ films 17 and 25 (that is, the insulating film 4) correspond to the “second insulating film” of the present invention. Corresponds to "membrane".

(3) Third Embodiment In the first and second embodiments described above, the insulating film 2 is constituted by the SiO ₂ film 21 formed by the thermal oxide film and the SiO ₂ film 23 formed by the CVD method. Explained the case. However, the present invention is not limited to this.
24A and 24B are diagrams showing a configuration example of the semiconductor device according to the third embodiment of the present invention. FIG. 24A is a plan view, and FIG. 24B is a plan view of FIG. FIG. 24C is a cross-sectional view taken along line B24-B′24 of FIG. 24A. For example, as shown in FIGS. 24A to 24C, the insulating film 2 is composed of only the SiO ₂ film 23 formed by the CVD method or the Si ₃ N ₄ film formed by the CVD method. May be. Even if it is such a structure, the effect similar to 1st, 2nd embodiment can be acquired.
In the third embodiment, the SiO ₂ film 23 (that is, the insulating film 2) corresponds to the “first insulating film” of the present invention. Other correspondences are the same as those in the first embodiment.

Schematic diagram showing a configuration example of a semiconductor device according to the first embodiment (part 1). FIG. 2 is a schematic diagram (part 2) illustrating a configuration example of the semiconductor device according to the first embodiment. FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 13 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 13). FIG. 14 is a view (No. 14) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 15 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 15). FIG. 16 is a view showing the method for manufacturing the semiconductor device according to the first embodiment (No. 16). FIG. 17 is a view (No. 17) illustrating the method for manufacturing the semiconductor device according to the first embodiment; The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 9 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to the second embodiment. FIG. 8 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. The figure which shows the structural example of the semiconductor device which concerns on 3rd Embodiment.

Explanation of symbols

1 Si substrate, 2, 4, 66 insulating film, 3,68 Si layer, 5 gate insulating film, 6 gate electrode, 7 impurity layer, 8 conductive film, 10 SOI substrate, 11, 73 SiGe layer, 13, 17, 21 , 21a, 21b, 23, 25, 31, SiO ₂ film, 15 Si ₃ N ₄ film, 18 support, 19, 75 cavity, 20 S / D layer, 33 LDD layer, 35 sidewall, 37, 53 poly Silicon film, 51 end region, 55, 71 interlayer insulating film, h support hole, h1 opening, H groove, H1-H3 contact hole

Claims (6)

A semiconductor layer formed on the semiconductor substrate via a first insulating film; and a second insulating film formed on the semiconductor substrate so as to surround the semiconductor layer in plan view, the second insulating film Is a method for manufacturing a semiconductor device in which a MOS field effect transistor is formed on an SOI substrate formed thicker than the first insulating film,
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming a source or drain on both sides of the gate electrode,
The step of forming the source or drain includes
Introducing an impurity into the semiconductor layer in the end region located on both sides of the region where the gate electrode is formed to form an impurity layer;
Forming a conductive film in contact with the impurity layer from the impurity layer to the second insulating film.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the conductive film, the conductive film is formed thicker than the semiconductor layer. Before the step of forming the conductive film,
Forming an insulating protective film on a side surface and an upper surface of the gate electrode;
Exposing the surface of the semiconductor layer in the end region, and
The step of forming the conductive film includes
Forming a semiconductor film on the SOI substrate in a state where the protective film is formed and a surface of the semiconductor layer in the end region is exposed;
Introducing impurities into the semiconductor film to make the semiconductor film have the same conductivity type as the impurity layer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: etching the semiconductor film to form the semiconductor film in the shape of the conductive film. Before the step of forming the gate electrode,
Exposing the surface of the semiconductor layer in the end region,
The step of forming the gate electrode and the step of forming the conductive film include
Forming a semiconductor film on the SOI substrate in a state where the gate insulating film is formed and a surface of the semiconductor layer in the end region is exposed;
Introducing impurities into the semiconductor film to make the semiconductor film have the same conductivity type as the impurity layer;
3. The semiconductor device according to claim 1, wherein a step of etching the semiconductor film to form the semiconductor film in the shape of the gate electrode and the shape of the conductive film is shared. Manufacturing method. The method further includes the step of forming the SOI substrate, and the step of forming the SOI substrate includes:
Sequentially forming a sacrificial semiconductor layer and the semiconductor layer on the semiconductor substrate;
Etching the semiconductor layer and the sacrificial semiconductor layer to form a first groove penetrating the semiconductor layer and the sacrificial semiconductor layer;
Forming a first insulating layer in at least the first groove and supporting the semiconductor layer by the first insulating layer;
Etching at least the semiconductor layer to form a second groove exposing the sacrificial semiconductor layer;
Etching the sacrificial semiconductor layer through the second trench to form a cavity between the semiconductor layer and the semiconductor substrate;
Forming the first insulating film in the cavity and embedding the cavity;
A step of forming a second insulating layer in the second groove and embedding the second groove after the cavity is embedded;
5. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film includes the first insulating layer and the second insulating layer. 6. A semiconductor device comprising an SOI substrate and a MOS field effect transistor formed on the SOI substrate,
The SOI substrate is
A semiconductor substrate, a semiconductor layer formed on the semiconductor substrate via a first insulating film,
A second insulating film that is thicker than the first insulating film and formed on the semiconductor substrate so as to surround the semiconductor layer in plan view,
The MOS field effect transistor is:
A gate electrode formed on the semiconductor layer via the gate insulating film;
A source or drain formed on both sides of the gate electrode,
The source or drain is
An impurity layer formed in the semiconductor layer in the end region located on both sides of the gate electrode;
And a conductive film formed in contact with the impurity layer and from the impurity layer to the second insulating film.

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