JP2001339093A - Phototransistor and phtocoupler provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to set impurity concentration in a base to be high while maintaining a high DC current amplification factor. SOLUTION: In this phototransistor 100, a resistor 11 is incorporated between the base 13 and an emitter 14. The base layer 13 is constituted of an Si1-XGeX (x>0) layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phototransistor used as a switching element by photoexcitation for use in an optical sensor or an optical coupling device, and a photocoupler incorporating the same.

[0002]

2. Description of the Related Art In a phototransistor, generally,
The collector-emitter breakdown voltage V _CE is obtained by the following equation (1).

[0003] ^{_{V CE ≒ V CB / n √hFE}} (1) (V CE: Collector-emitter breakdown voltage, V _CB: collector-base breakdown voltage, hFE: current transfer ratio, n ≒
3-6) As can be seen from equation (1), the collector-emitter breakdown voltage V _CE decreases as the DC current gain (hFE) increases. This is because the dark current generated at the collector-base junction is amplified by hFE times, which causes an avalanche breakdown process. Therefore, usually, in order to obtain a desired collector-emitter breakdown voltage, the upper limit of the range of the DC current amplification factor is necessarily limited. However, the output limit is limited corresponding to the upper limit of the DC current amplification factor. You.

As a means for overcoming this, there is known a technique of incorporating a resistor between a base and an emitter. FIG. 10 is a sectional view of a conventional phototransistor having a built-in resistor between the base and the emitter. The configuration will be described below while describing the formation method.

First, an N-type silicon (Si) layer 10a and N
^The P-type resistive layer 11 is formed by selectively implanting P-type impurity ions such as boron into the silicon substrate 10 using the-type silicon layer 10b by using an ion implantation method or the like.
Further, the selective implantation of P-type impurity ions is repeated,
^{The +} type base layer 113 is formed. At this time, the resistance layer 11
Are connected to each other (not shown).

Next, after the surface of the base layer 113 is oxidized and etched, N-type impurity ions such as phosphorus are selectively implanted by thermal diffusion, so that N
^{The +} type emitter layer 114 is formed.

At the same time as the formation of the emitter layer 114, an N ⁺ type channel stopper 15 is formed on the outer periphery of the chip.
Next, a thermal oxide film 16 is formed on the substrate surface, further chip peripheral portion, the upper portion of the emitter layer 114, P ⁺ -type base layer 11
The oxide film on the upper part of the gate electrode 3 and on the part that will be the contact part between the P-type resistance layer 11 and the emitter electrode 24 to be formed later is partially removed. A metal film such as aluminum (A1) is deposited so as to cover the portions where these oxide films have been removed. This metal film is etched into a desired shape and heat-treated to form a base electrode 23, an emitter electrode 24, and card rings 31, 32. Although the emitter electrode 24 and the card ring 31 play different roles, they have a common metal film structure.

[0008] Finally, a collector electrode 20 of a metal film such as gold (Au) is provided on the back surface of the N-type silicon substrate 10.
In this example, the N-type silicon substrate 10 functions as a collector layer of a phototransistor. The region 50 is a light receiving region.

According to the configuration of FIG. 10, the dark current generated at the collector-base junction is caused to flow between the base and the emitter via the resistance layer 11, so that the dark current is not amplified, and the DC current amplification factor is reduced. A decrease in the breakdown voltage between the collector and the emitter due to an increase in the value can be prevented.

[0010]

Conventionally, a phototransistor for a photocoupler has a withstand voltage of 90 V or more and a DC current amplification factor (hFE), although it varies depending on the application.
Are required to be 1500 or more. However, in a phototransistor having a built-in resistor between the base and the emitter as shown in FIG. 10, the DC current gain had to be suppressed to 1000 or less in order to maintain the withstand voltage of 90 V or more. This is because when forming an emitter region or a base region by diffusion or ion implantation in a silicon substrate, the base width must be narrowed or the impurity concentration of the base must be reduced in order to obtain a high DC current amplification factor. Also in this case, punch-through is likely to occur, and the breakdown voltage between the collector and the emitter and between the collector and the base is reduced.

In a phototransistor having a resistor (resistance layer 11) formed between the base and the emitter, if the resistance is too large, the dark current generated at the collector-base junction does not easily flow through the resistor, and the resistance between the collector and the emitter decreases. Cannot be maintained at a high level, and the effect of inserting a resistor is reduced. Conversely, if the resistance value is too small, the low current characteristic of the DC current gain with respect to the base current decreases,
There is no practical level of amplification.

As described above, it is particularly difficult for a phototransistor having a resistor provided between a base and an emitter to obtain a high level of DC current amplification factor and a high collector-emitter breakdown voltage.

Another problem in the conventional example shown in FIG. 10 is that the response speed is slow. This is because the light receiving portion of the phototransistor is formed on a silicon substrate. The absorption coefficient of the silicon light receiving portion for incident light having a wavelength of 950 nm is 400.
Since low as cm ^-1, when absorbing long-wavelength light of 950 nm, the penetration depth into the silicon of the incident light becomes longer, the diffusion movement time of carriers becomes longer. As a result, the response speed at the time of switching is reduced. Incidentally, JP-A-63-122
In Japanese Patent Publication No. 285, G
It discloses the use of e _lx Si _x mixed crystal layer.

As for a photocoupler having a conventional phototransistor as shown in FIG. 10, a CMR (Common Mode Rejection) characteristic as a withstand voltage and a noise characteristic and a high-speed response contradictory thereto. However, there is a trade-off between high output and it is difficult to improve both characteristics at the same time. Therefore, various types of photocouplers having various characteristics have been required according to the use of each photocoupler.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a phototransistor and a phototransistor capable of setting a high impurity concentration in a base while maintaining a high DC current amplification factor. Provided is a photocoupler having the same.

[0016]

A phototransistor according to the present invention is a phototransistor having a built-in resistor between a base layer and an emitter layer, wherein the base layer of the transistor is _Silx Ge _x (x> 0). It is formed by layers, thereby achieving the above object.

In one embodiment, a part of the base layer also functions as a light receiving section. More preferably, the base layer is formed over the entire light receiving region. Still more preferably, the planar shape of the base layer has a mesh shape or a stripe shape. In one embodiment, the spacing between the meshes or stripes is the same as the width of the depletion layer extending from the base region to the collector region when the transistor is operated when the emitter is grounded.

Note that a heterojunction is formed between the base layer and the emitter layer.

A photocoupler according to the present invention includes a phototransistor as described above, thereby achieving the above object.

The operation of the present invention will be described below.

As described above, in the phototransistor having a built-in resistor between the base and the emitter according to the present invention, the base layer is formed of a silicon-germanium mixed crystal. Because of this, the heterojunction between silicon and silicon-germanium mixed crystal is formed between the emitter and base,
The band gap becomes narrower than the silicon-silicon bond when silicon is used for the base layer. Therefore, the barrier against the minority carriers moving from the base to the emitter is increased, and the injection of the minority carriers from the base to the emitter can be more effectively suppressed.

As a result, when a DC current gain equivalent to that of a transistor whose base is formed of silicon single crystal is obtained, the impurity concentration in the base can be increased. As a result, the punch-through voltage increases and the collector
The breakdown voltage between the emitters can be maintained at a high level, and the sensitivity of the phototransistor is improved. Further, the DC current gain of the phototransistor can be set to a high value of 1500 or more. By increasing the sensitivity of the phototransistor, it is possible to design a photocoupler exhibiting the same CTR (current transfer ratio) characteristics as before even if a phototransistor having a light receiving unit of a smaller size is used.

The silicon-germanium mixed crystal is about 7
Since the absorption coefficient in the red to infrared wavelength region of 00 nm or more is several tens to several hundreds times higher than that of silicon, silicon-germanium mixed crystals can absorb light at a depth shallower than silicon single crystals. Therefore, the generated optical carrier is p
The distance to reach the n-junction is reduced, the probability of carrier extinction due to lifetime is reduced, and the travel distance of the optical carrier is reduced. As a result, the sensitivity of the phototransistor to light in the above wavelength range is improved, and the response speed is improved.

Further, by making the planar state of the base layer of the silicon / germanium layer also serving as a light receiving portion into a mesh or stripe, the transition capacitance between the base and the collector can be reduced, and the rise time during the switching operation of the phototransistor can be reduced. And the descent time can be reduced. By setting the mesh or stripe interval to be the same as the width of the depletion layer extending from the base region to the collector region when operating the transistor when the emitter is grounded, the transit time of minority carriers generated in the base region can be reduced. The influence can be eliminated, and a high-speed switching operation can be realized.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A basic feature of the present invention is that in a phototransistor having a built-in resistor between a base and an emitter, a portion which operates as a base is made of a silicon-germanium mixed crystal ( _Silx Ge _x , x > 0) layer. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) As a first embodiment, a phototransistor according to the present invention will be described. FIG.
Is a top configuration of the phototransistor 100 of the present embodiment,
FIG. 2 schematically shows a cross-sectional configuration along the broken line II-II in FIG. The configuration will be described below while describing a method for forming the phototransistor 100.

First, an N-type silicon (Si) layer 10a and N
^The P-type resistive layer 11 is formed by selectively implanting P-type impurity ions such as boron into the silicon substrate 10 using the-type silicon layer 10b by using an ion implantation method or the like.
Further, the selective implantation of P-type impurity ions is repeated,
^{The +} type base diffusion layer 12 is formed. At this time, the resistance layer 1
One end and the base diffusion layer 12 are connected to each other as shown in the upper part of FIG.

Subsequently, by epitaxial growth,
P-type silicon germanium (Si _lx G) so as to extend over the P ⁺ type base diffusion layer 12 divided into two portions.
e _{x, x>} 0) to form a P-type base layer 13 by selectively growing the mixed crystal layer. Next, after oxidizing and etching the surface of the base layer 13, N-type impurity ions such as phosphorus are selectively implanted by thermal diffusion or N ⁺ -type polysilicon is deposited, so that the surface of the base layer 13 is N ⁺
The mold emitter layer 14 is formed. (FIG. 2 shows a case where the emitter layer 14 is formed by ion implantation.)
Simultaneously with the formation of the emitter layer 14, an N ⁺ type channel stopper 15 is formed on the outer periphery of the chip. Next, a thermal oxide film 16 is formed on the surface of the substrate, and furthermore, the outer peripheral portion of the chip, the upper portion (24c) of the emitter layer 14, the P ⁺ type base diffusion layer 12
The oxide film on the upper portion (23c) and the portion serving as the contact portion 11c (see FIG. 1) between the P-type resistance layer 11 and the emitter electrode 24 to be formed later is partially removed. A metal film such as aluminum (A1) is deposited so as to cover these portions from which the oxide film has been removed. This metal film is etched into a desired shape and subjected to a heat treatment so that the base electrode 23, the emitter electrode 24 and the card rings 31, 32 are formed.
To form The emitter electrode 24 and the card ring 3
1 has different roles, but is constituted by one common metal film.

Finally, a collector electrode 20 made of a metal film such as gold (Au) is provided on the back surface of the N-type silicon substrate 10.
In the present embodiment, the N-type silicon substrate 10 functions as a collector layer of the phototransistor 100. The region 50 is a light receiving region.

The equivalent circuit of the phototransistor 100 formed as described above has a collector terminal 41, an emitter terminal 42, and an NPN transistor 4 as shown in FIG.
3, a photodiode 44 and a base-emitter resistor 45.

In the present invention, the base layer 13 of the transistor is made of silicon germanium ( _Silx Ge _x , x>
0) Since it is formed by a mixed crystal, the DC current gain (h) is the same as in the conventional case where the base layer is formed of silicon.
When FE) is obtained, the impurity concentration in the base layer can be set higher. Therefore, the punch-through voltage increases, and the breakdown voltage between the collector and the emitter can be maintained at a high level.

Further, since the base layer 13 and the emitter layer 14 of the silicon-germanium layer form a heterojunction, the band gap is narrower than that of the conventional silicon-silicon junction using silicon. Thereby, injection of minority carriers from the base layer to the emitter layer is suppressed, and a high DC current gain of 1500 or more can be realized.

(Second Embodiment) Hereinafter, another embodiment of the phototransistor according to the present invention will be described. FIG.
Corresponds to FIG. 2 and schematically illustrates a cross-sectional configuration of the phototransistor 200 according to the present embodiment. The difference from the first embodiment is that the phototransistor 20 of the present embodiment is different from the first embodiment.
0, the base layer is provided so as to cover the light receiving region of the transistor.

Hereinafter, the structure of the phototransistor 200 will be described while describing a method of forming the phototransistor 200.

First, the N-type silicon (Si) layer 10a and N
^The P-type resistive layer 11 is formed by selectively implanting P-type impurity ions such as boron into the silicon substrate 10 using the-type silicon layer 10b by using an ion implantation method or the like.
Further, the selective implantation of P-type impurity ions is repeated,
^{A +} type base diffusion layer 62 is formed. At this time, the resistance layer 1
One end of the base 1 and the base diffusion layer 62 are connected to each other as in the case of the first embodiment.

Subsequently, by epitaxial growth, 2
P-type silicon germanium (Si _lx G) so as to straddle the P ⁺ type base diffusion layer 62 divided into two portions.
e _x, to form a P-type base layer 63 by selectively growing the x> 0) layer. The P-type base layer 63 covers the entire light receiving area 50 as shown in FIG. In other words, in the present embodiment, a part of the P-type base layer 63 also functions as a light receiving unit.

Next, after oxidizing and etching the surface of the base layer 63 in the same manner as in the first embodiment, N-type impurity ions such as phosphorus are selectively implanted by thermal diffusion or N ⁺ -type ions. By depositing polysilicon,
The N ⁺ -type emitter layer 14 is formed on the surface of the base layer 63. (FIG. 4 shows a case where the emitter layer 14 is formed by ion implantation.) Simultaneously with the formation of the emitter layer 14, an N ⁺ type channel stopper 15
To form Next, a thermal oxide film 16 is formed on the substrate surface,
The outer periphery of the chip, the upper part (24c) of the emitter layer 14, the upper part (23c) of the base layer 63, and the contact part 11c between the P-type resistance layer 11 and the emitter electrode 24 to be formed later.
The oxide film at the part which becomes the part (see FIG. 1 of the first embodiment) is partially removed. A metal film such as aluminum (A1) is deposited so as to cover these portions from which the oxide film has been removed. This metal film is etched into a desired shape and heat-treated to form a base electrode 23, an emitter electrode 24, and card rings 31, 32.

Finally, a collector electrode 20 made of a metal film such as gold (Au) is provided on the back surface of the N-type silicon substrate 10.
The N-type silicon substrate 10 is a phototransistor 200
Function as a collector layer of

In this embodiment, since the base layer 63 also serving as the light receiving portion is formed of a silicon-germanium layer, the base layer 63 has a higher absorption coefficient in the red to infrared wavelength region than the case of the silicon base layer. Will have. Therefore, the incident light is absorbed by the shallow portion of the light receiving portion, and the sensitivity of the phototransistor is further increased as compared with the first embodiment using the light receiving portion made of silicon and the conventional structure. In addition, since the diffusion movement distance of the carrier is shorter than that in the case of the light receiving portion made of silicon, the response time can be shortened.

In FIG. 4, the base layer 63 has a light receiving region 5
However, even if the base layer 63 is provided in a part of the light receiving region 50, the above-described effects according to the present invention can be obtained to some extent.

Referring to FIG. 4, the base layer 63 has a continuous 1
Although described as a single layer, the plane configuration of the base layer also serving as the light receiving section may be a mesh shape (73a) as shown in FIG. 5 or a stripe shape (73b) as shown in FIG. The cross-sectional structure of the phototransistor in these cases is as shown in FIG. By using such a base layer, the transition capacitance between the base and the collector can be reduced, and the rise time and the fall time during the switching operation can be reduced without affecting the accumulation time and other characteristics.

Further, as shown in FIG. 8, the above-mentioned mesh or stripe interval D (FIGS. 5 and 6)
When operating the transistor when the emitter is grounded,
Width W of depletion layer 80 extending from base region to collector region
By doing so, it is possible to avoid an adverse effect on the response time of the traveling time of the minority carrier generated in the light receiving section.

Third Embodiment As a third embodiment, a photocoupler having a phototransistor according to the present invention will be described. FIG. 9 shows a photocoupler 30 of the present embodiment.
0 is schematically shown.

In the photocoupler 300, the phototransistor 91 is disposed so as to face the light emitting element 92, and an optical path is formed therebetween by the transparent silicon resin layer 93. The periphery of the above structure is sealed with a light-shielding epoxy resin layer 94 to form one package. still,
The lead frame 95 is for supplying an input signal to the photocoupler and extracting an output signal.

As the phototransistor 91, the phototransistor according to the first or second embodiment is used. As a result, the response time at the time of the switching operation of the photocoupler is shortened, it is possible to cope with various uses, and it is possible to increase the withstand voltage and the sensitivity. Further, since the chip pattern itself is not different from the conventional one such as the shape of the guard ring, the CMR (common mode) by increasing the sensitivity is improved.
rejection) properties do not deteriorate. In addition, CT
The area occupied by the light receiving portion of the phototransistor can be reduced without lowering the R (current transfer ratio) characteristic.

[0046]

According to the present invention, in a phototransistor having a built-in resistor between a base and an emitter, a portion which operates as a base is made of silicon germanium (Si _lx).
Ge _x , x> 0). This prevents a significant drop in the breakdown voltage between the collector and emitter,
A phototransistor having a high DC current gain (hFE) of 1500 or more can be obtained.

By forming the portion of the base layer also serving as the light receiving portion of the phototransistor from the silicon-germanium layer, the sensitivity to long-wavelength incident light is increased, and the response time at the time of switching operation is shortened. Is possible. Further, the response time can be further shortened by forming the base layer also serving as the light receiving section into a mesh structure or a stripe structure. Furthermore, the response can be further speeded up by making the interval between the meshes or stripes the same as the width of the depletion layer extending from the base region to the collector region when operating the transistor when the emitter is grounded. .

A photocoupler equipped with the above-described phototransistor can provide a high-speed response and can improve the sensitivity of the phototransistor even if the light-receiving portion of the phototransistor is reduced as compared with the conventional art. It is possible to design the device without any additional components.

[Brief description of the drawings]

FIG. 1 is a plan view of a phototransistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG. 1;

FIG. 3 is an equivalent circuit thereof.

FIG. 4 is a sectional configuration diagram of a phototransistor according to a second embodiment of the present invention;

FIG. 5 is a plan view of a modified example of the base layer therein.

FIG. 6 is a plan view of another modification of the base layer in the phototransistor of FIG.

FIG. 7 is a cross-sectional configuration diagram of a phototransistor including the base layer illustrated in FIG. 5 or 6.

FIG. 8 is a partially enlarged view showing a state of a depletion layer extending from a base region to a collector region when a transistor is operated in the case of a common emitter.

FIG. 9 is a configuration diagram of a photocoupler according to a third embodiment of the present invention.

FIG. 10 is a cross-sectional configuration diagram of a phototransistor according to a conventional technique.

[Explanation of symbols]

Reference Signs List 10 N-type Si substrate 11 P-type resistance layer 11 c Contact part between P-type resistance layer and emitter 12, 62 P-type base diffusion layer 13, 63, 73 a, 73 b P-type base layer (silicon-germanium mixed crystal layer) 14 N Type emitter layer 15 Channel stopper 16 Oxide film 20 Collector electrode 23 Base electrode 23c Contact part between base layer (base diffusion layer) and base electrode 24 Emitter electrode 24c Contact part between emitter layer and emitter electrode 31 P-type diffusion junction guard Ring 32 channel stopper junction guard ring 50 light receiving area 91, 100, 200 phototransistor 300 photocoupler

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5F049 MA12 MB03 MB12 NA03 NA20 PA10 PA14 QA09 QA12 QA14 SE05 WA01 5F089 AA10 AB03 AC02 CA12 DA02 DA14 EA04

Claims (7)

[Claims] 1. A base layer of the transistor is Si _lx Ge _x
A phototransistor formed of (x> 0) layers and having a built-in resistor between the base layer and the emitter layer. 2. The phototransistor according to claim 1, wherein a part of said base layer also functions as a light receiving section. 3. The phototransistor according to claim 2, wherein said base layer is formed over the entire light receiving region. 4. The phototransistor according to claim 2, wherein the planar shape of the base layer has a mesh shape or a stripe shape. 5. The phototransistor according to claim 4, wherein a distance between the meshes or stripes is equal to a width of a depletion layer extending from a base region to a collector region when the transistor is operated in a case where the emitter is grounded. . 6. The phototransistor according to claim 1, wherein a heterojunction is formed between said base layer and said emitter layer. 7. A photocoupler using the phototransistor according to claim 1.