JP2001326338A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for reducing an occurrence of a contact fault by providing a good contact of a source or a drain of a MISFET with a plug and a method for manufacturing it. SOLUTION: A method for manufacturing the semiconductor integrated circuit device comprises the steps of anisotropically etching an insulating film (silicon nitride film 13, a silicon oxide film 16) on the source or the drain (n- type semiconductor region 11), then forming a conductive film in contact holes 18, 19 formed by isotropically etching an exposed semiconductor substrate 1, and then forming the plug having a first embedding part existing on the substrate 1 and a second embedding part existing in the substrate 1 and having a diameter larger than that of the first embedding part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a fine MISFE.
T (Metal Insulator Semiconductor Field Effect Tra
nsistor) and the technology that is effective in its manufacture.

[0002]

2. Description of the Related Art A source or a drain of a MISFET is connected to a metal wiring or the like via a plug formed by embedding a conductive film in a contact hole formed on the source or the drain. Alternatively, a metal film is formed on a substrate including the inside of the contact hole, and is patterned into a desired shape to form a metal wiring, and connection with a source or a drain is achieved.

[0003]

However, as the aspect ratio of the contact hole increases with the miniaturization of the semiconductor integrated circuit device, the area of the contact portion between the plug and its base decreases, and the height of the plug increases. The size is growing. As a result, contact failure may occur due to physical and thermal stress at the contact portion.

For example, when the substrate is deformed such as warp,
Physical stress is applied to the contact portion, and the contact portion is peeled off, which may cause poor contact. The semiconductor substrate singulated after the formation of the semiconductor element is packaged with a mold resin or the like. Also in this packaging step, physical stress is applied, which may cause the above-mentioned contact failure.

Further, during heat treatment after forming a conductive film such as a plug in a contact hole, a contact portion may be peeled off due to a difference in coefficient of thermal expansion between the conductive film and its underlying coating layer, resulting in poor contact. Further, even after the end of the manufacturing process, the operating temperature of the device tends to increase as the speed of the semiconductor integrated circuit device increases, so that thermal stress is applied even during the operation of the device, and contact failure may occur.

In particular, in the memory cell portion, the source or drain of the memory cell selection MISFET and the information storage capacitor element are connected by a plug. Becomes In a COB (Capacitor Over Bitline) structure, the source or drain of the MISFET and the information storage capacitor are connected via a plurality of plugs to dispose the information storage capacitor above the bit line. Therefore, the problem of contact failure becomes significant. Further, since the source or drain of the memory cell selecting MISFET and the bit line are also connected via the plug, the number of plugs electrically connected to a single memory cell selecting MISFET increases, and Countermeasures for defects are important.

Further, between the source or drain of the memory cell selection MISFET and the information storage capacitor, polycrystalline silicon is often used to reduce leakage, and polycrystalline silicon is harder than metal or the like. It is difficult to alleviate physical stress, and the problem of poor contact becomes significant.

An object of the present invention is to achieve good contact between a source or a drain of a MISFET and a plug, and to reduce occurrence of contact failure. Another object of the present invention is to provide a technique for promoting high integration of a semiconductor integrated circuit device constituted by MISFETs.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor integrated circuit device of the present invention
(A) an element formed on the main surface of the semiconductor substrate and having a contacted region; and (b) an insulating film formed on the element and excluding the contacted region.
(C) a conductive film formed on the contacted region, wherein the first buried portion is present on the element; and the conductive film is present in the element and has a larger diameter than the first buried portion. And a plug comprising a second embedded portion.

(2) The semiconductor integrated circuit device of the present invention
(A) a source and a drain formed in the semiconductor substrate, and (b) a gate electrode formed on the semiconductor substrate between the source and the drain via a gate insulating film;
(C) an insulating film formed on the gate electrode, the source and the drain, excluding the contacted region on the source or the drain; and (d) on the contacted region on the source or the drain. A conductive film formed on the semiconductor substrate;
Embedded in the semiconductor substrate and the first
And a second embedding portion having a larger diameter than the embedding portion.

(3) The semiconductor integrated circuit device of the present invention
(A) a source and a drain formed in the semiconductor substrate, and (b) a gate electrode formed on the semiconductor substrate between the source and the drain via a gate insulating film;
(C) a first insulating film formed on the gate electrode, the source and the drain, excluding a contacted region on the source or the drain; and (d) a first insulating film on the source or the drain. A conductive film formed on the contact region, a first buried portion present on the semiconductor substrate, and a second buried portion present in the semiconductor substrate and having a larger diameter than the first buried portion. A first plug comprising an embedded portion; and (e) a first plug formed on the first insulating film and the first plug, excluding a contacted region on the first plug. (F) a conductive film formed on the contacted region on the first plug, a first buried portion present on the first plug, In the plug of the first The second one whose diameter is larger than that of the buried part
And (g) an information storage capacitor formed on the second plug.

(4) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming an insulating film on the element.
(C) forming a contact hole by exposing a part of the element by anisotropically etching the insulating film and then isotropically etching the exposed part of the element; (D) forming a conductive film in the contact hole.

(5) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming a source and a drain in a semiconductor substrate; and (b) forming a gate on the semiconductor substrate between the source and the drain. Forming an insulating film and a gate electrode, (c) forming a first insulating film on the gate electrode, source and drain, and (d) anisotropically etching the insulating film. Forming a first contact hole by isotropically etching the exposed source or drain after exposing the source or drain surface; and (e)
Forming a first conductive film on the first insulating film including the inside of the first contact hole; and (f) etching the first conductive film until the first insulating film is exposed. Or polishing; and (g) forming a second insulating film on the first conductive film and the first insulating film;
(H) exposing the surface of the first conductive film by anisotropically etching the second insulating film and then isotropically etching the exposed first conductive film; Forming a second contact hole by
(I) forming a second conductive film on the second insulating film including the inside of the second contact hole; and (j) exposing the second conductive film to the second insulating film. And (k) forming an information storage capacitor on the second conductive film.

According to the above means, the element (MISFE)
A plug (conductive film) on a contacted region of a contact (T, wiring, plug, etc.) in a first buried portion existing on the device and in the device, and having a diameter larger than that of the first buried portion; The conductive film can be formed in the contact hole formed by anisotropically etching the insulating film on the contacted region and then anisotropically etching the insulating film on the contacted region. Forming
Since the connection with the contacted region can be achieved, even if a physical or thermal stress is applied to the contact portion, the contact portion is not easily peeled off, and the contact failure can be reduced. Further, higher integration of the semiconductor integrated circuit device can be achieved.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

A DRAM (Dyna) according to an embodiment of the present invention
1 to 10 show a method of manufacturing a mic random access memory).
Will be described in the order of the steps. The left part of each drawing showing the cross section of the substrate shows a region (memory cell array) in which a memory cell of the DRAM is formed, and the center part shows a cross-sectional view of the center part (AA in FIG. 1) of the memory cell array. The right part shows the peripheral circuit area.

First, as shown in FIG.
An element isolation groove 2 having a depth of about 350 nm is formed by etching a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon having a specific resistance of about Ωcm.

Thereafter, the substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film 6 having a thickness of about 10 nm on the inner wall of the groove. The silicon oxide film 6 is used to recover the damage caused by the dry etching generated on the inner wall of the groove and to relieve the stress generated at the interface between the silicon oxide film 7 embedded in the groove and the substrate 1 in the next step. Form.

Next, CVD is performed on the substrate 1 including the inside of the groove.
(Chemical Vapor deposition)
A silicon oxide film 7 having a thickness of about 0 nm is deposited, and subsequently, the substrate 1 is thermally oxidized at about 1000 ° C. to improve the film quality of the silicon oxide film 7 (burning).
, Chemical mechanical polishing (CMP; Chemical Mecha)
The surface of the silicon oxide film 7 is polished by polishing the silicon oxide film 7 on the upper portion of the groove by a mechanical polishing method.

Next, after p-type impurities (boron) and n-type impurities (for example, phosphorus) are ion-implanted into the substrate 1,
By diffusing the impurities by heat treatment at about 1000 ° C., a p-type well 3 is formed on the substrate 1 of the memory cell array, and a p-type well 3 and an n-type well 4 are formed on the substrate 1 in the peripheral circuit region.

Next, the substrate 1 was washed with a hydrofluoric acid-based cleaning solution.
After the surfaces of the (p-type well 3 and n-type well 4) are wet-cleaned, a clean gate oxide film having a thickness of about 6 nm is formed on each surface of the p-type well 3 and the n-type well 4 by thermal oxidation at about 800 ° C. 8 is formed. This gate oxide film 8 may be formed of a silicon oxynitride film containing silicon nitride in part. By using a silicon oxynitride film, the hot carrier resistance of the gate oxide film 8 can be improved.

Next, as shown in FIG.
A low-resistivity polycrystalline silicon film 9a doped with phosphorus (P) having a thickness of about 100 nm is deposited on the upper surface of the substrate by CVD, and a WN film (not shown) having a thickness of approximately 10 nm is formed thereon by sputtering. A W film 9c having a thickness of about 50 nm is deposited,
Further, a silicon nitride film 10 having a thickness of about 200 nm is deposited thereon by CVD. Next, for the purpose of stress relaxation of the W film 9c and densification (densification) of the WN film,
A heat treatment at about 800 ° C. is performed in an atmosphere of an inert gas such as nitrogen.

Next, the silicon nitride film 10 is dry-etched using a photoresist film (not shown) as a mask, thereby leaving the silicon nitride film 10 in a region where a gate electrode is to be formed.

Next, using the silicon nitride film 10 as a mask, the W film 9c, the WN film (not shown) and the polycrystalline silicon film 9a are dry-etched, so that the polycrystalline silicon film 9a is formed in the memory cell array and the peripheral circuit region. , WN
A gate electrode 9 (gate length 0.
15 μm). Note that the gate electrode 9 formed in the memory cell array functions as a word line WL.

Next, after a thin oxide film (not shown) of about 4 nm is formed on the side wall of the polycrystalline silicon film 9a by wet hydrogen oxidation, the n-type is formed in the p-type well 3 of the memory cell array on both sides of the gate electrode 9. Impurity (phosphorus) is ion-implanted (20 keV, 2 × 10 ¹³ / cm ² ) to form an n ⁻ -type semiconductor region 11, and an n-type impurity (arsenic) is ion-implanted in the p-type well 3 in the peripheral circuit region. implantation ^{(20keV, 2 × 10 14 /} cm 2) n by ^- -type semiconductor region 11, ion implantation of p-type impurity (boron) in the n-type well ^{4 (20keV, 2 × 10 14} /
cm ² ) to form the p ⁻ type semiconductor region 12. In order to suppress the short channel effect, when forming the n ⁻ -type semiconductor region 11 of the p-type well 3 and the p ⁻ -type semiconductor region 12 of the n-type well 4 in the peripheral circuit region, boron is 25 keV and 1 kV, respectively. in × 10 ¹³ / cm ^2, also by ion implantation of phosphorus at 50 keV, 2 × 10 ¹³ / cm ^2, the p-type well 3 in the peripheral circuit region n ^- -type semiconductor region 11 and the n-type well 4 p ^- -type semiconductor region 1
An opposite conductivity type semiconductor region (not shown) is formed around the 2p ⁻ type semiconductor region 12.

Next, as shown in FIG.
After depositing a silicon nitride film 13 having a thickness of about 50 nm by the method D, the upper part of the substrate 1 of the memory cell array is covered with a photoresist film (not shown), and the silicon nitride film 13 in the peripheral circuit region is anisotropically etched. By doing so, the side wall spacer 1 is formed on the side wall of the gate electrode 9 in the peripheral circuit region.
3a is formed.

Next, an n ⁺ -type semiconductor region 14 (source, drain) is formed by ion-implanting an n-type impurity (phosphorus or arsenic) into the p-type well 3 in the peripheral circuit region. A p ⁺ type semiconductor region 15 (source, drain) is formed by ion implantation of a type impurity (boron). In the steps up to this point, the source of the LDD (Lightly Doped Drain) structure is
An n-channel MISFET Qn and a p-channel MISFET Qp having a drain are formed.

Subsequently, after a silicon oxide film 16 having a thickness of about 700 nm to 800 nm is deposited on the gate electrode 9 by a CVD method, the silicon oxide film 16 is polished by a CMP method to flatten its surface. Alternatively, a film thickness of 300 nm
After applying an SOG (spin-on-glass) film (not shown), the substrate 1 is heat-treated at about 800 ° C. to densify (bake) the SOG film. After depositing the silicon oxide film 16 having a thickness of about 500 nm to 600 nm, the surface may be planarized by polishing the silicon oxide film 16 by a CMP method. The SOG film is
The gap between the gate electrodes 9 (word lines WL) is reduced to a minimum size determined by the resolution limit of photolithography because the gap fill property between fine wirings is superior to a silicon oxide film deposited by the CVD method. Can be satisfactorily embedded.

Next, contact holes 18 and 19 are formed above the n ⁻ type semiconductor region 11 of the memory cell array,
The plug 20 is formed therein, and this step will be described in detail with reference to FIG.

FIGS. 4A and 4B are enlarged views of the memory cell array portion. As shown in FIG. 4A, using a photoresist film (not shown) as a mask, the silicon oxide film 16 is anisotropically dry-etched to remove the surface of the silicon nitride film 13 on the n ⁻ type semiconductor region 11. Expose. Next, the silicon nitride film 13 on the n ⁻ type semiconductor region 11 is anisotropically dry-etched, so that the substrate 1 (n
^- exposing the surface of the semiconductor region 11).

The etching of the silicon oxide film 16 is performed as follows.
The etching is performed under conditions such that the etching rate of silicon oxide is higher than that of silicon nitride, so that the silicon nitride film 13 is not completely removed. The etching of the silicon nitride film 13 is performed under such a condition that the silicon nitride film 13 is anisotropically etched, and is etched so as to leave the silicon nitride film 13 on the side wall of the gate electrode 9 (word line WL). Thus, contact holes 18 and 19 having a fine diameter are formed in a self-alignment (self-alignment) with the gate electrode 9 (word line WL).

Next, as shown in FIG. 4B, the exposed surface of the substrate 1 (the n ⁻ type semiconductor region 11) is
By performing the dry etching of about 0 nm, an undercut is generated in the substrate 1 under the silicon nitride film 13.

The etching of the silicon oxide film 16 and the silicon nitride film 13 can be performed by the same apparatus by changing etching conditions such as an etching gas. Further, since it is possible to change from anisotropic etching to isotropic etching by changing the etching conditions, the isotropic etching of the substrate 1 (n ⁻ type semiconductor region 11) is the same. It can be done with the device. On the other hand, the substrate 1 (the n ⁻ type semiconductor region 1
The isotropic etching of 1) can be wet etching.

Next, as shown in FIG. 5, an n-type impurity (phosphorus or arsenic) is ion-implanted through the contact holes 18 and 19 into the p-type well 3 (n ^- type semiconductor region 11) of the memory cell array. , N ⁺ type semiconductor regions 17 (source, drain) are formed. Through the steps so far, the memory cell selecting MISFETs Qs formed of the n-channel type are formed in the memory cell array.

Next, a plug 20 is formed inside the contact holes 18 and 19. To form the plug 20,
First, contact hole 1 using a cleaning solution containing hydrofluoric acid
After the insides of the contact holes 8 and 19 are wet-cleaned, the upper portion of the silicon oxide film 16 including the insides of the contact holes 18 and 19 is doped with an n-type impurity such as phosphorus (P) at a dose of about 4 × 10 ²⁰ / cm ^3. A polycrystalline silicon film is deposited by a CVD method, and then this polycrystalline silicon film is etched back (or polished by a CMP method) and left only in the contact holes 18 and 19.

[0038] Thus, n ^- by dry-etching the silicon oxide film 16 and the silicon nitride film 13 on the semiconductor region 11 is anisotropically, the substrate 1 ^- to expose the surface of the (n type semiconductor region 11) After that, the exposed substrate 1
The surface of the (n ⁻ -type semiconductor region 11) is isotropically dry-etched to form the substrate 1 under the silicon nitride film 13.
Contact holes 18, 19 with undercuts
Forming a so it was decided to form a plug buried polycrystalline silicon film in the contact hole, the shape of the plug, as shown in FIG. 6 is an enlarged view of the plug 20 in FIG. 5, the substrate 1 (n ^- A portion A having a diameter a above the surface of the n ^- type semiconductor region 11) and a portion B existing below the surface of the substrate 1 (n ⁻ type semiconductor region 11) and having a diameter b larger than the diameter a. Therefore, even if physical or thermal stress is generated between the substrate 1 (the n ⁻ -type semiconductor region 11) and the plug 20, the diameter “b” of the portion B is changed to the diameter “a” of the portion A.
The contact between the substrate 1 (the n ⁻ type semiconductor region 11) and the plug 20 can be maintained because the substrate 1 (the n ⁻ type semiconductor region 11) does not easily peel off.

Next, as shown in FIG. 7, a silicon oxide film 21 having a thickness of about 20 nm is deposited on the silicon oxide film 16 by a CVD method, and then dried using a photoresist film (not shown) as a mask. By dry-etching the silicon oxide film 21 in the peripheral circuit region and the silicon oxide film 16 thereunder by etching, the n-channel MIS is formed.
Source and drain of the FET Qn (n ⁺ type semiconductor region 1)
A contact hole 22 is formed above 4), and a contact hole 23 is formed above the source and drain (p ⁺ type semiconductor region 15) of the p-channel type MISFET Qp. At the same time, the p-channel MISFET and the n-channel MISFET in the peripheral circuit region (not shown)
A contact hole is formed above the gate electrode of ET. Furthermore, the contact hole 18 of the memory cell array
A through hole 25 is formed in the upper part of the substrate.

The contact holes 22 and 23 are anisotropically dry-etched using the silicon oxide film 21 as a mask with a photoresist film (not shown) to form a surface of the substrate 1 (the n ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region 15). Is exposed, and then the surface of the exposed substrate 1 (the n ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region) is isotropically dry-etched, whereby an undercut occurs in the substrate 1 under the silicon oxide film 16. It forms by doing.

Similarly, a contact hole on a gate electrode of a MISFET (not shown) is
6 and 21 are anisotropically dry-etched using a photoresist film (not shown) as a mask to expose the surface of the gate electrode, and then isotropically dry-etched the exposed surface of the gate electrode to form a silicon nitride film. It is formed by generating an undercut underneath.

Further, the through holes 25 are similarly anisotropically dry-etched with the silicon oxide films 16 and 21 using a photoresist film (not shown) as a mask to expose the surface of the plug 20. It is formed by undercutting under the silicon oxide film 21 by isotropically dry etching the surface.

When the ends of contact holes 22 and 23 extend over silicon nitride film 10, contact holes 18 and 19 of the above-described memory cell array are formed.
Similarly to the conditions described above, the condition that the etching rate of silicon oxide is higher than that of silicon nitride
The contact holes 18 and 19 can be formed by self-alignment (self-alignment) with respect to the gate electrode 9 under the condition that 3 is anisotropically etched.

Next, as shown in FIG. 8, the contact holes 22 and 23, the contact holes on the gate electrode of the MISFET (not shown), and the upper part of the silicon oxide film 21 including the inside of the through holes 25 are formed by the CVD method. After depositing a W film of about 300 nm, the silicon oxide film 2
1 is polished by a CMP method, and these films are polished to the inside of the contact holes 22 and 23 and the through hole 25.
The plug 27 is formed by leaving the plug 27 only inside.
Note that a thin WN film may be formed below the W film by a CVD method, and the plug 27 may be formed of two layers of the WN film and the W film.

As described above, the silicon oxide films 21 and 16 are anisotropically dry-etched to form the substrate 1 (n).
After exposing the surface of the contacted portion of the MISFET such as the ⁺ type semiconductor region 14 and the p ⁺ type semiconductor region 15), the surface of the gate electrode, and the surface of the plug 20, the exposed substrate 1
The contact holes 22, 23, etc. are formed by isotropically dry-etching the surface of the plug, etc., a metal film such as a W film is buried in the contact holes, and the plug 27 is formed. , A portion above the substrate 1 and the like and a portion below the substrate 1 having a larger diameter than the substrate 1 and the like. Even if it occurs in the middle, it is not easily peeled off, and the contact between the substrate 1 and the like and the plug 27 can be maintained.

Next, as shown in FIG. 9, a bit line BL is formed on the silicon oxide film 21 in the memory cell array, and first-layer wirings 30 to 33 are formed on the silicon oxide film 21 in the peripheral circuit region. To form The bit line BL and the first-layer wirings 30 to 33 are formed, for example, of the silicon oxide film 21.
Is formed by depositing a W film having a thickness of about 100 nm on the upper surface by sputtering, and then dry-etching the W film using a photoresist film as a mask. In addition,
A thin WN film is formed under the W film by a CVD method,
The bit line BL and the first-layer wiring may be composed of two layers of a film and a W film.

Next, a silicon oxide film 34 having a thickness of about 300 nm is deposited on the bit line BL and the first layer wirings 30 to 33 by the CVD method.

The bit line BL and the wirings 30 to 33
When a step occurs on the surface of the silicon oxide film 34 due to the step, the surface is flattened by chemically and mechanically polishing the silicon oxide film 34.

Next, CVD is performed on the silicon oxide film 34.
After a polycrystalline silicon film 35 having a thickness of about 200 nm is deposited by the method, the polycrystalline silicon film 35 in the memory cell array is dry-etched using the photoresist film as a mask, thereby forming the polycrystalline silicon film 35 above the contact hole 19. After the grooves 36 are formed, sidewall spacers 37 are formed on the side walls of the grooves 36.

The side wall spacer 37 is formed in the groove 3
After a polycrystalline silicon film is deposited on the polycrystalline silicon film 35 including the inside of the substrate 6 by the CVD method, the polycrystalline silicon film is anisotropically etched and left on the side wall of the groove 36.

Next, the silicon oxide film 34 and the underlying silicon oxide film 21 and the like are dry-etched using the sidewall spacers 37 and the polycrystalline silicon film 35 as masks to form through holes 38, thereby forming a memory cell. Even if the size is reduced, a matching margin between the bit line BL and the through hole 38 is ensured. as a result,
In the next step, a short circuit between the plug 39 embedded in the through hole 38 and the bit line BL can be prevented.

In forming the through hole 38,
First, the surface of the plug 20 is exposed by anisotropically dry-etching the silicon oxide film 34 and the underlying silicon oxide film 21 using the side wall spacers 37 and the polycrystalline silicon film 35 as masks. By dry-etching the surface of the formed plug 20 isotropically, an undercut occurs in the substrate 1 under the silicon oxide film 21.

Next, after removing the polycrystalline silicon film 35 and the sidewall spacers 37 by dry etching, plugs 39 are formed in the through holes 38 as shown in FIG. Plug 39 is through hole 3
A low-resistance polycrystalline silicon film doped with an n-type impurity (phosphorus) is formed on the silicon oxide film 34 including the inside of the substrate 8 by CVD.
After deposition by a method, the polycrystalline silicon film is formed by etching back and leaving it only inside the through hole 38.

As described above, after the surface of the plug 20 is exposed by anisotropically dry-etching the silicon oxide films 34 and 21, the exposed surface of the plug 20 is isotropically dry-etched. Hall 38
Is formed, a polycrystalline silicon film is buried in the through hole 38, and the plug 39 is formed. Therefore, the shape of the plug is changed from the portion above the surface of the plug 20 and the surface of the plug 20 having a larger diameter than this portion. Since a two-part structure with the lower part can be used, even if physical or thermal stress is generated between the plug 20 and the plug 39, the plug is not easily separated, and the plug 20 and the plug 39 are not separated. Contact can be maintained.

Next, CVD is performed on the silicon oxide film 34.
A silicon nitride film 40 having a thickness of about 100 nm is deposited by the
Subsequently, a silicon oxide film 41 is deposited on the silicon nitride film 40 by the CVD method, and then the silicon oxide film 41 and the silicon nitride film 40 of the memory array are dry-etched to form a groove 42 on the through hole 38. I do.

Next, a low-resistance polycrystalline silicon film having a thickness of about 50 nm doped with an n-type impurity such as phosphorus (P) is formed on the silicon oxide film 41 including the inside of the groove 42 by CVD.
After deposition by a method, a photoresist film or the like is buried in the groove 42, and the polycrystalline silicon film on the silicon oxide film 41 is etched back to leave only on the inner wall of the groove 42. Thus, the lower electrode 43 of the information storage capacitor C is formed along the inner wall of the groove 42.

Next, a capacitor insulating film 44 composed of a tantalum oxide film or the like and an upper electrode 45 composed of a TiN film or the like are formed on the lower electrode 43. The capacitor insulating film 44 and the upper electrode 45 are formed by first depositing a thin tantalum oxide film having a thickness of about 20 nm on the silicon oxide film 41 including the upper portion of the lower electrode 43 by a CVD method, and then forming the thin tantalum oxide film on the tantalum oxide film. After a TiN film is deposited by CVD and sputtering so as to fill the inside of the groove 42, T is etched by dry etching using a photoresist film (not shown) as a mask.
It is formed by patterning the iN film and the tantalum oxide film.

As a result, an information storage capacitance element C composed of the lower electrode 43 composed of a polycrystalline silicon film, the capacitance insulating film 44 composed of a tantalum oxide film, and the upper electrode 45 composed of a TiN film is formed. You. Further, by the above steps, a DRAM memory cell including the memory cell selecting MISFET Qs and the information storage capacitor C connected in series to the MISFET Qs is completed.

Next, C is placed above the information storage capacitor C.
A silicon oxide film 50 having a thickness of about 100 nm is deposited by the VD method, and a second-layer wiring is formed thereon.
The drawing is omitted. The steps up to the formation of the second-layer wiring include first-layer wirings 30 and 3 in the peripheral circuit region.
The through-holes are formed by dry-etching the silicon oxide films 50 and 41, the silicon nitride film 40, and the silicon oxide film 34 on the upper part of 3. Then, after forming a plug inside the through hole, the silicon oxide film 5 is formed.
A second layer wiring is formed on the upper part of 0. This plug may also be formed after the first layer wirings 30 and 33 exposed by the dry etching are further isotropically dry etched.

Next, by forming a silicon oxide film on the second layer wiring, the DR of the present embodiment is formed.
AM is almost completed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

In particular, in the above embodiment, the present invention is applied to all plugs. However, the type of the conductive film constituting the plug, the material of the contacted portion, the diameter of the contact hole, and the like are taken into consideration. In addition, the present invention can be applied only to locations where connection failures are likely to occur.

In the above embodiment, the case where the present invention is applied to a DRAM has been described. However, the present invention is not limited to this, and is widely applied to an LSI having a plug embedded in a fine contact hole. Can be.

[0064]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the plug (conductive film) on the contacted region is formed between the first buried portion existing on the device and the first buried portion present in the device. Since the contact portion can be constituted by the second buried portion having a large diameter, even if a physical or thermal stress is applied to the contact portion, the contact portion is less likely to be out of order, and contact failure can be reduced. Further, higher integration of the semiconductor integrated circuit device can be achieved.

(2) According to the present invention, the MISFE
A first buried portion in which a plug (conductive film) on the source or drain of T is present on the semiconductor substrate; and a second buried portion which is present in the semiconductor substrate and has a larger diameter than the first buried portion. Therefore, even if a physical or thermal stress is applied to the contact portion, the contact portion is not easily disconnected, and the contact failure can be reduced. In addition, if the present invention is applied to a memory cell selecting MISFET in which polycrystalline silicon harder than metal or the like is often used to reduce leakage due to progress in miniaturization, M
Contact defects between the source or drain of the ISFET and the information storage capacitor can be reduced.

(3) Further, M is transmitted through a plurality of plugs.
A good contact can also be obtained in a memory cell selecting MISFET having a COB structure in which the source or drain of the ISFET is connected to the information storage capacitor.

(4) According to the present invention, an insulating film on an element is anisotropically etched, and then a conductive film is formed in a contact hole formed by isotropically etching. Since the upper contacted region and the conductive film are connected, even if a physical or thermal stress is applied to the contact portion, the contact portion is less likely to be out of order and the contact failure can be reduced. Further, higher integration of the semiconductor integrated circuit device can be achieved.

(5) Further, if the present invention is applied to a MISFET for selecting a memory cell in which polycrystalline silicon, which is harder than metal or the like, is often used to reduce leakage due to progress in miniaturization, the source or drain of the MISFET can be reduced. Contact failure with the information storage capacitor can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 6 is a diagram showing a structure of a plug of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation trench 3 p-type well 4 n-type well 6 silicon oxide film 7 silicon oxide film 8 gate oxide film 9 a polycrystalline silicon film 9 c W film 9 gate electrode 10 silicon nitride film 11 n ^- type semiconductor region 12 p ⁻ Type semiconductor region 13 silicon nitride film 13 a sidewall spacer 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 16 silicon oxide film 17 n ⁺ type semiconductor region 18 contact hole 19 contact hole 20 plug 21 silicon oxide film 22 contact hole 23 Contact hole 25 Through hole 27 Plug 30-33 Wiring 34 Silicon oxide film 35 Polycrystalline silicon film 36 Groove 37 Side wall spacer 38 Through hole 39 Plug 40 Silicon nitride film 41 Silicon oxide film 42 Groove 43 Lower electrode 44 Insulating film 45 Upper electrode 50 Silicon oxide film A Part on substrate a Part A diameter B Part in substrate b Part B diameter C Information storage capacitance element Qn n-channel MISFET Qp p-channel MISFET Qt Memory cell selection MISFET WL Word line BL Bit line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 BB01 BB40 CC01 DD04 DD08 DD16 DD17 DD43 DD63 FF06 FF21 FF27 GG14 GG16 5F033 JJ04 KK01 MM01 NN01 NN29 NN37 PP06 QQ22 QQ33 QQ37 QQ48 RR04 RR06 AD16 AD08 TT06 AD48 JA39 JA40 MA06 MA17 MA19 NA01 PR03 PR06 PR12 PR21 PR22 PR23 PR29 PR33 PR36 PR39 PR40

Claims (5)

[Claims] (A) formed on a main surface of a semiconductor substrate;
An element having a contacted area; (b) an insulating film formed on the element, excluding the contacted area; and (c) a conductive film formed on the contacted area. And a plug comprising a first buried portion present on the element and a second buried portion present in the element and having a diameter larger than that of the first buried portion. Semiconductor integrated circuit device. (A) a source and a drain formed in the semiconductor substrate; (b) a gate electrode formed on the semiconductor substrate between the source and the drain via a gate insulating film; A) an insulating film formed on the gate electrode, the source and the drain, excluding the contacted region on the source or the drain; and (d) formed on the contacted region on the source or the drain. A first buried portion present on the semiconductor substrate, and a second buried portion present in the semiconductor substrate and having a larger diameter than the first buried portion. A semiconductor integrated circuit device, comprising: a plug; (A) a source and a drain formed in the semiconductor substrate; (b) a gate electrode formed on the semiconductor substrate between the source and the drain via a gate insulating film; A) a first insulating film formed on the gate electrode, the source and the drain, excluding a contacted region on the source or the drain; and (d) a contacted region on the source or the drain. A first buried portion present on the semiconductor substrate, the second buried portion being present in the semiconductor substrate and having a diameter larger than that of the first buried portion. And (e) a second plug formed on the first insulating film and the first plug, excluding a contacted region on the first plug. Insulating film and (F) a conductive film formed on a contacted region on the first plug, a first buried portion present on the first plug, and a conductive film present in the first plug; ,
A second plug including a second buried portion having a diameter larger than that of the first buried portion; and (g) an information storage capacitor formed on the second plug. Semiconductor integrated circuit device. (A) forming an element on the main surface of the semiconductor substrate; (b) forming an insulating film on the element; and (c) etching the insulating film anisotropically. Forming a contact hole by isotropically etching the exposed part of the element after exposing a part of the element; and (d) forming a conductive film in the contact hole. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. A step of: (a) forming a source and a drain in a semiconductor substrate; (b) forming a gate insulating film and a gate electrode on the semiconductor substrate between the source and the drain; A) forming a first layer on said gate electrode, source and drain;
(D) exposing the source or drain surface by anisotropically etching the insulating film, and then isotropically etching the exposed source or drain. Forming a first contact hole; (e) forming a first conductive film on the first insulating film including the inside of the first contact hole; and (f) forming the first conductive film. Etching or polishing the conductive film until the first insulating film is exposed; and (g) forming a second insulating film on the first conductive film and the first insulating film; (H) exposing the surface of the first conductive film by anisotropically etching the second insulating film and then isotropically etching the exposed first conductive film; Second contact hole (I) forming a second conductive film on a second insulating film including the inside of the second contact hole; and (j) forming the second conductive film on the second insulating film. A step of etching or polishing until the insulating film is exposed; and (k) a step of forming an information storage capacitor on the second conductive film. Method.