JP2001326197A - Polishing method of semiconductor wafer and polishing apparatus thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the polishing method of a semiconductor water, which suppresses sagging in the outer periphery of a wafer and an enhance planarity of the wafer, and to provide the polishing apparatus of the wafer. SOLUTION: The ground surface of a silicon wafer W is polished with a polishing cloth 11, while one part of the outer peripheral part of the wafer W projects to the outside of the polishing cloth 11. At this time, the outer peripheral part of the wafer W passes through the non-polishing region of the cloth 11, each time the wafer W is rotated at a prescribed angle. Hereby, the contact area of the outer peripheral part of eth wafer with the ground surface per unit time is reduced, in comparison with that of the center part of the wafer with the ground surface per unit time and the planarity of the wafer is increased. Moreover, the end surfaces, which are located on the side of the cloth 11, of a template 14 and the height of the ground surface are made almost uniform with each other. As the result, the quantity of rebound R1 of the cloth 11 at the polishing of the ground surface is reduced, and a pressure per unit area to the outer peripheral part of the wafer is reduced more than that per unit area to the center part of the wafer. Hereby, sagging in the outer peripheray of the wafer can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for polishing a semiconductor wafer, and more particularly, to a method and an apparatus for polishing a semiconductor wafer for improving the flatness by preventing the sagging of the peripheral portion of the wafer during the polishing of the semiconductor wafer. .

[0002]

2. Description of the Related Art An SOI substrate is prepared by bonding mirror surfaces of an active layer wafer and a support substrate wafer at room temperature.
Finishing is performed by performing a bonding heat treatment for strengthening the bonding strength of the bonding, chamfering the outer peripheral portion of the active layer wafer, thinning the surface of the active layer wafer by surface grinding, and then performing mirror polishing. The polishing sag at the outer peripheral portion of the wafer (hereinafter, sometimes referred to as “peripheral sagging”) generated during polishing of the wafer for the active layer and the wafer for the support substrate is said to be a major cause of void defects when the two wafers are bonded to each other. ing. Also, during polishing of the SOI substrate, the outer peripheral sag of the active layer wafer is generated, and the outer peripheral sag causes deterioration of the guaranteed exclusion region of the active layer wafer. For these reasons, it is important from the viewpoint of improving the yield of each of the active layer wafer, the support substrate wafer and the SOI substrate to suppress the peripheral sag during polishing.

As a polishing apparatus used at the time of polishing, for example, a polishing apparatus 100 shown in FIGS.
It has been known. That is, a polishing platen 102 on which a polishing cloth 101 is spread on an upper surface, and a polishing head 104 provided with a template 103 for fixing a wafer W to be polished are provided on the lower surface.
This is a device in which a back pad 105 made of, for example, a nonwoven fabric having a water retention property is stored. FIG. 13 is an explanatory view of a semiconductor wafer polishing apparatus according to a conventional means. FIG.
FIG. 2 is an enlarged cross-sectional view of a main part during use of a semiconductor wafer polishing apparatus according to a conventional means.

At the time of polishing, pure water is supplied to the back pad 105, and the wafer W is held from the back side by its surface tension. The wafer W is placed on the template 103 such that the polished surface protrudes from the lower edge of the template 103.
Is held. Then, the polishing head 104 is rotated on the polishing platen 102 while the polishing agent (slurry) containing the abrasive grains is supplied to the polishing surface, and is oscillated in the radial direction of the platen indicated by an arrow in FIG. Polishing surface of polishing cloth 101
Mirror polishing. Wafer W is back pad 1
Rotated by the polishing head 104 while being fixed at 05. In addition, the abrasive usually contains, in addition to calcined silica and colloidal silica (silica sol) as abrasive grains, an amine as a processing accelerator, an organic polymer as a haze inhibitor, and the like.

[0005]

However, according to the prior art wafer polishing apparatus, the template 103
14, the polished surface of the wafer W protruded from the lower edge of the template 103 by about 100 μm, as shown in FIG. As a result, the rebound amount R of the polishing pad 101 during polishing increases (for example, 50 to 100 μm), and the outer peripheral portion of the wafer W is larger than the polishing pad
The pressure per unit area in contact with No. 1 was increased, and the outer peripheral sag of the wafer W was promoted. The rebound of the polishing cloth refers to a deformation height when a peripheral portion of a polishing cloth portion that abuts on a wafer polishing surface during polishing bulges (rebounds) toward the polishing head.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and an apparatus for polishing a semiconductor wafer capable of suppressing the outer peripheral sag of the wafer and improving the flatness of the wafer surface.

[0007]

According to a first aspect of the present invention, a semiconductor wafer held inside a rotating template is pressed and polished while a polishing agent is supplied to a polishing surface of a polishing cloth. In the method for polishing a semiconductor wafer, the height of the polishing surface of the semiconductor wafer and the end face of the template on the polishing cloth side are substantially aligned, and a part of the outer peripheral portion of the semiconductor wafer is protruded by 1 to 15 mm outside the polishing cloth,
This is a semiconductor wafer polishing method in which the semiconductor wafer is rotated and polished in this state. As a polishing apparatus employed in the method for polishing a semiconductor wafer, for example, a waxless type polishing apparatus which does not use wax is used. Of course, a wax polishing type may be used. A general waxless device uses a template in which a back pad (such as a suede pad) is arranged in a hole slightly larger than the diameter of the wafer, and a foam layer (nap portion) on the surface of the back pad and a back surface of the wafer. And supply the pure water to the wafer, and use the surface tension of the pure water to handle the wafer.

[0008] Examples of the semiconductor wafer include a silicon wafer and a gallium arsenide wafer. Examples of the polishing cloth include a hard urethane pad, a CeO ₂ pad, and a non-woven cloth pad.

As the polishing agent (slurry), for example, a mixture of baked silica, colloidal silica (polishing abrasive), amine (processing accelerator), organic polymer (haze inhibitor) and the like can be used. Colloidal silica is present as a transparent or opaque milky white colloid liquid dispersed in water as primary particles without agglomeration of silicate fine particles. Here, when the height of the polishing cloth side end surface of the template and the polishing surface of the semiconductor wafer are made substantially equal, the polishing cloth rebound amount is 0 during polishing.
It refers to a range of the difference in height between the polishing cloth side end surface and the wafer polished surface so as to be 10 μm. The size of the polishing surface is
There is no limitation as long as the outer peripheral edge of this surface is located radially inward of the outermost peripheral circle of the wafer rotation trajectory. Therefore, for example, part or all of the outer peripheral portion of the polishing pad may be arbitrarily cut. The semiconductor wafer may not only protrude from the polishing surface when the polishing head rotates but also protrude when the polishing head swings. In the case of a single-wafer type polishing apparatus, the polishing usually occurs during the swing.

If the amount of protrusion of the outer peripheral portion of the wafer to the outside of the polishing pad is less than 1 mm, there is a disadvantage that the contact area per unit area with the polishing pad and the pressure are almost the same as those of the conventional method. On the other hand, if it exceeds 15 mm, the contact area and the pressure are too small, and the polishing of the central portion of the wafer is promoted, resulting in a concave wafer. These matters also correspond to claim 2.

According to a second aspect of the present invention, there is provided a polishing platen on which a polishing cloth is spread, a rotatable polishing head arranged to face the polishing platen, and a water holding property which is attached to the polishing head. Via a back pad, a template in which a semiconductor wafer is held from the back side in a space inside the ring, and a semiconductor wafer being rotated by the polishing head while supplying an abrasive to the polishing surface of the polishing cloth. In a semiconductor wafer polishing apparatus for pressing and polishing,
The thickness of the template is such that the end face of the template on the polishing cloth side is substantially the same as the height of the polishing surface of the semiconductor wafer, and the size of the polishing action surface of the polishing cloth is the outer peripheral portion of the semiconductor wafer during polishing. Part of it is 1-15m outside the polishing cloth
This is a semiconductor wafer polishing apparatus having a size protruding only by m.

[0012]

According to the present invention, the semiconductor wafer is rotated and the polished surface (usually, the wafer surface) is polished while part of the outer peripheral portion of the wafer protrudes outside the polishing pad. During polishing, the outer peripheral portion of the wafer is polished while passing through the non-polishing region every time the semiconductor wafer rotates by a predetermined angle. Therefore, the contact area per unit time at the outer peripheral portion of the semiconductor wafer is smaller than that at the central portion of the wafer. This increases the flatness of the wafer surface. At this time, the template is designed to have a thickness such that the height of the end face on the polishing cloth side and the polished surface of the semiconductor wafer are substantially equal. Therefore, the amount of rebound of the polishing cloth during polishing is reduced. As a result, the pressure per unit area is relatively smaller at the outer peripheral portion of the semiconductor wafer than at the central portion of the wafer. Therefore, sag on the outer periphery of the semiconductor wafer is reduced.

In the case of a bonded SOI substrate in which an active layer wafer and a supporting substrate wafer are bonded to each other, the height of the polishing pad side of the semiconductor wafer and the height of the polishing surface of the semiconductor wafer are substantially equalized. The effect of suppressing the sagging of the outer peripheral portion of the layer wafer is that when the outer peripheral portion of the active layer wafer is chamfered, the grinding with the grinding wheel passes through the active layer wafer and reaches the outer peripheral portion of the support substrate wafer. Only for notched chamfered wafers. That is, in the case of a mirror-chamfered wafer in which the outer peripheral portion grinding is stopped up to the wafer for the active layer, it is conventional that the thickness of the template is, for example, 0 to 50 μm thinner than the thickness of the polished semiconductor wafer. Is small.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front view of a polishing apparatus for a semiconductor wafer according to one embodiment of the present invention. FIG. 2 is an enlarged sectional view of a main part of a semiconductor wafer polishing apparatus according to an embodiment of the present invention during use. In FIG. 1, reference numeral 10 denotes a polishing apparatus for a semiconductor wafer (hereinafter, sometimes referred to as a polishing apparatus).
Surface plate 12 on which is spread, and 1
And a polishing head 13. Specifically, a single wafer type waxless polishing apparatus is employed as the polishing apparatus 10. The polishing cloth 11 has a diameter of 300 to 600 mm,
A closed cell type hard polyurethane pad having a thickness of 1 mm or less is used. A template 14 for fixing the silicon wafer W is provided on the lower surface of the polishing head 13, and a back pad 1 having water retention is provided inside the template 14.
5 are stored. As the back pad 15, a pad made of a nonwoven fabric is employed.

Next, a method for polishing a silicon wafer W using the polishing apparatus 10 will be described. At the time of polishing, pure water is supplied to the back pad 15, and the silicon wafer W is held from the back side by the surface tension. This silicon wafer W is held by the template 14 such that the end face of the template 14 on the side of the polishing cloth 11 and the polished surface (surface) of the silicon wafer W are aligned. That is, the polished surface of the silicon wafer W is flush with the lower edge of the template 14. Then, 100 to 300 gf / cm ²
The silicon wafer W is pressed against the surface (polishing surface) of the polishing cloth 11 spread on the polishing platen 12 with the pressure of. While maintaining this state, and while supplying the abrasive onto the polishing pad 11, the polishing platen 12 is rotated at a predetermined rotation speed. In addition, simultaneously with this rotation, the polishing head 13 is rotated at a predetermined rotation speed, a predetermined pressure, and a predetermined rocking width in the radial direction of the platen while rotating at a predetermined rotation speed. As a result, the polished surface of the wafer is polished for a predetermined time while a part of the outer peripheral portion of the silicon wafer W protrudes outside the polishing pad 11 by the head position variable L.

When such polishing is performed, the outer peripheral portion of the wafer being polished is polished while passing through the non-polishing region every time the silicon wafer W rotates by a predetermined angle. On the other hand, in the conventional polishing method that does not protrude (the head position variation is 0 mm), the polishing amount at the outer peripheral portion of the wafer is larger than that at the central portion of the wafer. On the other hand, the polishing apparatus 1
At 0, the contact area per unit time between the outer peripheral portion of the wafer and the polishing pad 11 is smaller than the central portion of the wafer. Thereby, the flatness deterioration rate, which is one of the indexes of the polishing accuracy, is reduced, and the wafer flatness can be increased. Here, the flatness deterioration rate indicates a rate indicating how many μm the GBIR deteriorates every time polishing is performed by 1 μm.
On the negative side, the closer to zero, the better.

On the other hand, the thickness of the template 14 of one embodiment is made larger than that of a conventional plate, and the end face of the template 14 on the side of the polishing pad 11 is substantially aligned with the height of the wafer polishing surface. Therefore, the polishing cloth 11 during polishing is
The rebound amount R1 (for example, 0 to 10 μm) of FIG.
The rebound amount R of the conventional product shown in FIG.
m). As a result, the pressure per unit area is relatively reduced in the outer peripheral portion of the wafer as compared with the central portion of the wafer. As a result, polishing sag on the outer peripheral portion of the wafer is reduced.

Here, referring to FIGS. 3 to 12, the outer peripheral sag and the wafer flatness when the active layer wafer of the SOI substrate is actually polished using the polishing apparatus 10 of this embodiment will be described. GBIR). FIG. 3 is a schematic view of a polishing apparatus using a semiconductor wafer polishing apparatus according to the present invention.
It is a principal part expanded sectional view of an OI board. FIG. 4 is an explanatory diagram showing measurement positions on an active layer wafer of an SOI substrate to be polished using the semiconductor wafer polishing apparatus of the present invention.
5 to 12 are graphs showing the state of sagging of the outer periphery of the sample substrate in each of the comparative examples and the test examples.

The polishing conditions are as follows. That is, S
OI substrate diameter: 6 inches, average thickness of SOI substrate; 6
22 μm, template thickness; conventional thickness (Comparative Examples 1 to 5)
3), the same thickness as the wafer (Comparative Example 4 and Example 1,
2) Amount of protrusion of the SOI substrate from the outer periphery of the platen during polishing (polishing head position variation L): 0 mm, 7 mm, 15 mm
It is. In addition, this evaluation is based on a measuring instrument manufactured by NanoSpec Co., which can measure the thickness of the outer peripheral portion of the active layer wafer. Here, the measurement range of this measuring instrument is set to a range from the outermost periphery of the silicon oxide film to 20 mm inward in the wafer radial direction. The graphs of FIGS. 5 to 8 show the state of sagging on the outer periphery of Comparative Examples 1 to 4, and FIGS.
The graph of shows the state of sagging on the outer periphery in Test Examples 1 and 2. In each graph, the measurement results at three measurement points in FIG. 4 are represented by three different line graphs. In Comparative Examples 1 to 3, the thickness of the template is the conventional thickness, and in Comparative Example 4 and Test Examples 1 and 2, the thickness of the template is equivalent to that of the wafer. Based on this, the graph of FIG. 11 shows the average value of the measured values at the above three points in Comparative Examples 1 to 3,
The graph of FIG. 12 shows the average value of the measured values at the above three points in Comparative Example 4 and Test Examples 1 and 2. Table 1 below shows the measurement results such as the flatness of each active layer wafer.

[0020]

[Table 1]

As is clear from comparison between the graphs of Comparative Examples 1 to 4 and the graphs of Test Examples 1 and 2, when the thickness of the template was changed from the conventional thickness to the same thickness as the wafer, The outer peripheral sag of the active layer wafer was reduced. Further, when a part of the outer peripheral portion of the wafer was protruded outside the polishing cloth and polished (variable head position: 7 mm, 15 mm), the flatness deterioration rate was reduced and the wafer flatness was increased.

[0022]

According to the present invention, the height of the end face of the template on the polishing cloth side and the height of the polishing surface of the semiconductor wafer are substantially equalized, and a part of the outer peripheral portion of the rotating semiconductor wafer protrudes outside the polishing cloth. Since the polishing is performed by polishing, the sagging of the outer peripheral portion of the wafer can be suppressed, and the flatness of the semiconductor wafer can be improved.

[Brief description of the drawings]

FIG. 1 is a front view of a semiconductor wafer polishing apparatus according to one embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a main part of the semiconductor wafer polishing apparatus according to one embodiment of the present invention during use.

FIG. 3 is an enlarged sectional view of a main part of an SOI substrate to be polished by using the semiconductor wafer polishing apparatus of the present invention.

FIG. 4 is a front view showing a measurement position on an active layer wafer of an SOI substrate to be polished by the semiconductor wafer polishing apparatus of the present invention.

FIG. 5 is a graph showing the state of sagging on the outer periphery of a sample substrate according to Comparative Example 1.

FIG. 6 is a graph showing a state of sagging of an outer periphery of a sample substrate according to Comparative Example 2.

FIG. 7 is a graph showing a state of sagging of an outer periphery of a sample substrate according to Comparative Example 3.

FIG. 8 is a graph showing the state of sagging on the outer periphery of a sample substrate according to Comparative Example 4.

FIG. 9 is a graph showing the state of sagging on the outer periphery of the sample substrate according to Test Example 1.

FIG. 10 is a graph showing the state of sagging on the outer periphery of another sample substrate according to Test Example 2.

FIG. 11 is a graph showing the state of sagging of the outer periphery of each sample substrate according to Comparative Examples 1 to 3.

FIG. 12 is a graph showing the state of sagging of the outer periphery of each sample substrate according to Comparative Example 4 and Test Examples 1 and 2.

FIG. 13 is a front view of a semiconductor wafer polishing apparatus according to a conventional means.

FIG. 14 is an enlarged sectional view of a main part during use of a semiconductor wafer polishing apparatus according to a conventional means.

[Explanation of symbols]

 Reference Signs List 10 polishing device for semiconductor wafer, 11 polishing cloth, 12 polishing platen, 13 polishing head, 15 back pad, W silicon wafer (semiconductor wafer).

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masamitsu Fukuda 1-5-1, Otemachi, Chiyoda-ku, Tokyo F-term (reference) 3C058 AB04 AC04 BA02 BA07 CB01 CB02 DA17

Claims (2)

[Claims] 1. A method of polishing a semiconductor wafer, wherein a polishing liquid is supplied to a polishing surface of a polishing cloth while pressing a semiconductor wafer held inside a rotating template, thereby polishing the semiconductor wafer. The height of the end surface of the semiconductor wafer and the height of the polished surface of the semiconductor wafer are substantially aligned, and a part of the outer peripheral portion of the semiconductor wafer is protruded by 1 to 15 mm outside the polishing cloth, and the semiconductor wafer is rotated and polished in this state. Polishing method. 2. A polishing platen on which a polishing cloth is spread, a rotatable polishing head disposed opposite to the polishing platen, and a ring via a back pad attached to the polishing head and having water retention. A template in which the semiconductor wafer is held from the back side in the inner space, and a semiconductor wafer to be polished by pressing the rotating semiconductor wafer by the polishing head while supplying an abrasive to the polishing surface of the polishing cloth. In the polishing apparatus, the thickness of the template, the thickness of the end surface of the template on the polishing cloth side is substantially the same as the height of the polishing surface of the semiconductor wafer, the size of the polishing action surface of the polishing cloth, the semiconductor during polishing An apparatus for polishing a semiconductor wafer having a size such that a part of an outer peripheral portion of the wafer protrudes outside the polishing cloth by 1 to 15 mm.