JP2001326107A - Chip-type laminated varistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip-type laminated varistor which is protected against crackings, when soldered to a circuit board in an equipment, and can be kept stable in electrical properties, and which contains SrTiO3 as a main component. SOLUTION: Ceramic layers 2 and NiO inner electrode layers 3 and 4 are laminated alternately into a laminate, and the laminate is sintered into a sintered body 7. The sintered body 7 is specified of NiO content, and provided that the thickness of the sintered body 7 including the uppermost to lowermost layer of the inner electrode layers 3 and 4 is represented by T1, the thickness of the uppermost ceramic layer 5 and lowermost ceramic layer 6 is represented by T2, the width of the sintered body 7 including its front or rear to the inner electrode layers 3 and 4 is represented by W1, the width of a part where the inner electrode layers 3 and 4 overlap with each other in the direction of the front or the rear is represented by W2, a gap formed between a line extending from the one or the other end of the laminate toward the opposed surface and the opposed surface is represented by L1, and a part where the inner electrode layers 3 and 4 overlap with each other through the intermediary of the ceramic layer 2 is represented by L2. These T1, T2, W1, W2, L1, and L2 are prescribed respectively to provide the constitution of a chip-type laminated varistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type laminated varistor having both characteristics of a capacitor function and a varistor function.

[0002]

2. Description of the Prior Art FIG.
It is the perspective view which cut out some of them. In FIG.
Is a ceramic layer 23 containing SrTiO ₃ as a main component and Ni
A sintered body obtained by alternately laminating internal electrode layers 24 and 25 containing O as a main component and sintering a ceramic layer 26 on the uppermost and lowermost layers, and sintering the surface of the final body 22 External electrodes 27 and 2 connected to the electrode layers 24 and 25, respectively.
A chip type varistor 8 having both characteristics of a varistor and a capacitor is formed between the external electrodes 27 and 28.

[0003] A method of manufacturing the chip-type laminated varistor configured as described above will be described below.

First, SrTiO ₃ is used as a main component, and Nb, Ta, V, W, Dy, Nd, Y, L
a ceramic layer 23 formed by mixing an oxide such as a, Ge, etc., a voltage non-linear characteristic improving material Mn, and a sintering aid Si,
A plurality of internal electrode layers 24 and 25 made of O are alternately laminated, and a ceramic layer 26 is further laminated on the uppermost and lowermost layers to form a laminate. Next, the laminated body is debubbled and calcined at about 1000 ° C., and then fired at about 1300 ° C. in a reducing atmosphere to obtain a sintered body 22. Thereafter, the sintered body 22 is re-oxidized in an oxidizing atmosphere. External electrode paste is applied to both end surfaces of the sintered body 22 and baked to form external electrodes 27 and 28.
Was formed to obtain a chip-type laminated varistor 21.

[0005]

However, in the above-mentioned prior art, since there is a difference in shrinkage in firing the internal electrode layers 24 and 25 and the ceramic layer 23, the internal electrode layers 24 and 25 are not fired in the reducing atmosphere. There is a problem that stress remains near the boundary between the ceramic layer 25, the ceramic layer 23, and the uppermost and lowermost ceramic layers 26, and cracks are likely to occur when soldering to the circuit board of the device.

The present invention solves the above-mentioned problems, and reduces the residual stress near the boundary between the internal electrode layer of the sintered body and the ceramic layer, thereby preventing cracks when soldering to a circuit board of equipment. It is an object of the present invention to provide a chip-type laminated varistor capable of preventing occurrence.

[0007]

Means for Solving the Problems In order to achieve the above object, the present invention has the following arrangement.

[0008] The invention described in claim 1 of the present invention is a method for preparing SrT
In a sintered body obtained by alternately laminating and sintering a ceramic layer mainly composed of iO ₃ and an internal electrode layer mainly composed of NiO, the NiO content in the sintered body is set to 8 wt% or less,
Assuming that the thickness from the uppermost layer to the lowermost layer of the internal electrode layers in the sintered body is T1, and the thickness of the uppermost and lowermost ceramic layers is T2, T1 and T2 are 0.4 ≧ T1 /
W1 is the range of T2, and W1 is the width direction dimension separated from the front or back surface of the sintered body to the internal electrode layer, and W2 is the dimension of the internal electrode layer overlapping the front or back direction of the laminate, and W1 and W2 are respectively 0.4 ≧ W1 / W2, and extends from one end or the other end of the sintered body toward the opposing surface to have a length dimension L1 distant from the opposing surface of the laminate and overlaps with the ceramic layer interposed therebetween. This is a chip-type multilayer varistor in which the dimensions of the internal electrode layer are L2 and L1 and L2 are each in the range of 0.4 ≧ L1 / L2, whereby distortion between the internal electrode layer and the ceramic layer is reduced, and the internal electrode layer is reduced. Residual stress can be reduced near the boundary between the chip and the ceramic layer, cracks can be prevented when this chip type varistor is soldered to the circuit board of equipment, and the electrical characteristics are not impaired. Effect that it is possible to obtain a highly sexual Multilayer Varistors, effects can be obtained.

According to a second aspect of the present invention, the ratio of the NiO internal electrode layer laminated per ceramic layer is 10 wt% based on the sum of the weight of the ceramic layer and the internal electrode layer. The chip-type laminated varistor according to claim 1, wherein a gap due to delamination does not occur between the internal electrode layer and the ceramic layer,
The effect of preventing the occurrence of cracks during soldering,
The effect is obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, the first embodiment of the present invention will be described with reference to the first embodiment.

FIG. 1 is a partially cutaway perspective view of a chip-type laminated varistor according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line XX in FIG. 1, and FIG. It is YY sectional drawing. 1 to 3, reference numeral 1 denotes a chip-type multilayer varistor.
The ceramic layer 2 mainly composed of O ₃ and the internal electrode layers 3 and 4 mainly composed of NiO are alternately laminated, and the ceramic layers 5 and 6 are laminated and sintered on the uppermost and lowermost layers. 7 and external electrodes 8 and 9 connected to the internal electrode layers 3 and 4 respectively are formed on the surface of the sintered body 7.

In the sintered body 7, the thickness from the uppermost layer 10 to the lowermost layer 11 of the internal electrode layers 3, 4 is T2, and the thickness of the uppermost and lowermost ceramic layers 5, 6 is T2. As T1, T1 and T2 are each set to 0.
4 ≦ T1 / T2, and the front surface 12 to the rear surface 13 of the sintered body 7
The width dimension of the internal electrode layers 3 and 4 extending in the direction is W2, the dimension from the front surface 12 of the sintered body to the internal electrode layers 3 and 4, and the rear surface 13 of the sintered body to the internal electrode layers 3 and 4. Is W1 and W1 and W2 are each 0.4
≦ W1 / W2, and one end 14 of the sintered body 7
From the other end 15 of the sintered body 7
Internal electrode layer 3 having a distance L1 between the first internal electrode layer 3 and the first internal electrode layer 3
And a second internal electrode layer 4 extending from the other end 15 of the sintered body toward the one end 14 to form a gap of L1 between the one end 14 of the sintered body 7 and the first internal electrode layer 4. The internal electrode layer 3 and the second internal electrode layer 4 have a size of L2 overlapping with each other, and a chip type laminated varistor in which L1 and L2 are each in the range of 0.4 ≦ L1 / L2.

The manufacturing method of the multilayer ceramic varistor 1 configured as described above will be described below.

First, Nb, Ta, and Ca as semiconductor materials are added to the main component SrTiO ₃ as Nb ₂ O ₅ , Ta ₂ O ₅ ,
In place of CaCO ₃ , M
n, instead Al to each MnCO _3, Al ₂ O _3, the Si as a sintering aid in place of the SiO ₂ after mixing each prescribed weighed so as to have the composition shown in Table 1,
Calcination was performed at a temperature of 1100 ° C. in an air atmosphere.

[0015]

[Table 1]

Next, the particle size of the calcined material is 0.6 to 0.1.
After finely pulverizing each with a ball mill so as to have a thickness of 7 μm, a binder, a dispersant, a plasticizer and the like are added to the obtained material powder and kneaded to prepare a slurry, and then a 50 μm-thick ceramic is formed using a known doctor blade method. A green sheet was produced.

Next, as shown in Table 2, the dimensions W1, W2, L1,
Screen printing the internal electrode layer 3 at the position of L2,
The ceramic green sheet provided with the internal electrode layer 3 is
The layers are laminated while being alternately shifted one by one in the longitudinal direction of the internal electrode layer 3, and after laminating, T1 is placed on the uppermost and lowermost layers of the laminate.
Ceramic green sheets satisfying /T2=0.4 were laminated and pressed to produce a laminated green block.

At the same time, the thickness of the internal electrode layer 3 to be screen-printed was adjusted to obtain the NiO content in the sintered body (Table 2) and the NiO content per one ceramic layer 2.

[0019]

[Table 2]

Next, the laminated green block is cut into a 1 × 2 type shape having a size of 2 mm long and 1.25 mm wide after firing, and one end of each of the internal electrode layers 3 and 4 is cut. A ceramic layer 2 is provided on both end surfaces facing each other in the longitudinal direction.
A layered body was formed alternately and exposed every other layer.

Next, the above-mentioned laminate is placed in an air atmosphere at 80.degree.
After debubbling at a temperature of 0 ° C, 1215 in a reducing atmosphere
The sintering was performed at a temperature of ° C. to produce a sintered body 7.

Thereafter, an electrode paste containing Ag as a main component is applied so as to be electrically connected to the internal electrode layers 3 and 4 exposed at both end surfaces of the sintered body 7, and the external electrodes 8 and 9 are exposed to air at 800 ° C. The sintered body was re-oxidized simultaneously with baking in the atmosphere.

Next, nickel plating and solder plating (not shown) were applied to the external electrodes 8 and 9 to secure solderability, thereby completing the chip-type multilayer varistor 1.

After the obtained chip-type laminated varistor 1 is fixed to an epoxy substrate with an adhesive and immersed in a solder bath set at 300 ° C. for 5 seconds, the crack occurrence rate and delamination occurrence rate of the chip-type laminated varistor 1 are determined. (Table 2).

As shown in Table 2, NiO in the sintered body 7
When the content of the internal electrode exceeds 8 wt%, the crack generation rate increases. If the dimensional relationships T1 / T2, W1 / W2, and L1 / L2 of the ceramic layer 2, the uppermost ceramic layer 5, the lowermost ceramic layer 6, and the internal electrode layers 3 and 4 each exceed 0.4, cracks occur. The rate increases. This is because the thermal expansion coefficients of the internal electrode layers 3 and 4 and the ceramic layer 2 in the sintered body 7 are different from each other, so that the sintered body 7 is greatly strained through firing of the laminated body.
It is considered that the internal stress remained in the vicinity of the boundary between 5, 6 and the internal electrode layers 3 and 4 and cracks were easily generated. As a result of polishing the cracked sample and observing the inside with a metallographic microscope, Gaps were detected between the internal electrode layers 3, 4 and the ceramic layers 2, 5, 6.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to Embodiment 2. Note that the chip-type multilayer varistor 1 according to the second embodiment has basically the same configuration as the chip-type multilayer varistor 1 shown in FIG.

As shown in the second embodiment, the ceramic layer 2
The chip-type laminated varistor 1 shown in Table 3 was produced by changing the thickness of the NiO electrode paste to be printed per layer.

[0028]

[Table 3]

After the obtained chip-type laminated varistor 1 was fixed to an epoxy substrate with an adhesive and immersed in a solder bath set at 300 ° C. for 5 seconds, the crack occurrence rate and delamination occurrence rate of the chip-type laminated varistor were measured. The results are shown in Table 3.

As shown in (Table 3), the content of the NiO internal electrode contained in one layer of the ceramic layer 2 was 10 wt.
%, The occurrence of cracks and delamination can be further prevented.

[0031]

As described above, the chip-type multilayer varistor of the present invention has a ceramic layer mainly composed of SrTiO ₃ and an N-type laminated varistor.
In a sintered body obtained by alternately laminating and sintering internal electrode layers containing iO as a main component, the content of the NiO internal electrode in the sintered body, the dimensions of the internal electrode layer, and the like are defined, whereby the ceramic layer is formed. Internal stress near the boundary between the chip and the internal electrode layer can be reduced, preventing cracks and delamination from occurring when soldering this chip-type multilayer varistor to the circuit board of equipment, and impairing electrical characteristics Therefore, a highly reliable chip-type laminated varistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a partially cutaway perspective view of a chip-type multilayer varistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the first embodiment taken along line XX in FIG. 1;

FIG. 3 is a sectional view taken along the line YY in FIG. 1 of the first embodiment.

FIG. 4 is a perspective view of a chip-type laminated varistor of a conventional example with a part cut away.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip-type laminated varistor 2 Ceramic layer 3, 4 Internal electrode layer 5, 6 Uppermost and lowermost ceramic layer 7 Sintered body 8, 9 External electrode 10 Uppermost internal electrode layer 11 Lowermost internal electrode layer 12 Firing The front of the sintered body 13 The back of the sintered body 14 One end of the sintered body 15 The other end of the sintered body

Claims (2)

[Claims] 1. A sintered body obtained by alternately laminating and sintering a ceramic layer containing SrTiO ₃ as a main component and an internal electrode layer containing NiO as a main component, wherein the NiO content in the sintered body is 8 wt%. T1 is the thickness from the uppermost layer to the lowermost layer of the internal electrode layers in the sintered body, and T2 is the thickness of the uppermost and lowermost ceramic layers in the sintered body. T1 / T2, and the width dimension away from the front or back surface of the sintered body to the internal electrode layer is W
1. The size of the internal electrode layer overlapping in the front or back direction of the laminate is W2, and W1 and W2 are each 0.4.
≧ W1 / W2, an internal electrode layer extending from one end or the other end of the sintered body toward the opposing surface and having a length dimension L1 apart from the opposing surface of the laminated body and overlapping via the ceramic layer Is L2, L1 and L2 are each set to 0.
A chip-type multilayer varistor having a range of 4 ≧ L1 / L2. 2. An N layer laminated per ceramic layer
The chip type varistor according to claim 1, wherein the ratio of the internal electrode layer made of iO is 10 wt% or less with respect to the sum of the weights of the ceramic layer and the internal electrode layer.