JP2001320604A - Display start position correction method and screen display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an image on a screen from being shaken and occurrence of flicker on the screen without changing a position of a display start position signal in an odd numbered field (or even numbered field) even when a relative phase relation of a vertical synchronizing signal input and a horizontal synchronizing signal input is inverted. SOLUTION: A phase discrimination means 120 discriminates whether a vertical synchronizing signal 101 is placed just before or just after a horizontal synchronizing signal 102, correction information outputted from a correction information selection circuit 106 is selected on the basis of its discrimination result, an adder circuit 108 adds the correction information and display start position setting information and comparing an output of a counter circuit 109 counting horizontal synchronizing signals after the input of the vertical synchronizing signal with an output of the adder circuit 108 generates the display start position signal. Thus, the display start position in the vertical direction of the image is corrected to keep the display start position of the image in the vertical direction constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display start position correcting method for correcting a vertical display start position of an image displayed on a screen based on an interlaced scanning video signal, and an interlaced scanning video signal. The present invention relates to a screen display control device that controls a display start position of an image displayed on a screen in a vertical direction based on the image display control device.

[0002]

2. Description of the Related Art A conventional screen display control device will be described below.

FIG. 6 is a schematic block diagram showing a circuit configuration of a conventional screen display control device. In FIG.
Is a display start position setting information storage circuit that stores display start position setting information, 702 is a counter circuit that counts the number of horizontal synchronization signals after inputting a vertical synchronization signal, and 703 is output from the display start position setting information storage circuit 701. A comparison determination circuit that compares the display start position setting information with the count value of the counter circuit 702 and determines that the output value of the counter circuit 702 matches or exceeds the display start position setting information. Is a display start position signal generating circuit that generates a display start position signal in response to the output of the display start signal.

The operation of the screen display control device configured as described above will be described below.

[0005] First, a vertical synchronizing signal and a horizontal synchronizing signal which are externally synchronized and separated are input to a counter circuit 702. Normally, a video signal of a television receiver or a video tape recorder enters through a vertical blanking period after a vertical synchronizing signal is input. Therefore, a predetermined video display start position in the vertical direction of the received image can be determined by counting the horizontal synchronization signal input based on the input of the vertical synchronization signal. The display start position is, for example, a position at which the display is started from the center of the screen or when the display is started by opening several tens of lines at the top.

This device is used, for example, in a display controller for navigation. In order to display a navigation image or a television image, the device is vertically cut, left and right cut, and the vertical position is finely adjusted according to peripheral circuits. It is for adjustment.

A display start position setting information circuit 701 preliminarily storing display start position setting information indicating a predetermined video start position.
And an output result of the counter circuit 702 and a comparison judgment circuit 703
To compare. When the output result of the counter circuit 702 reaches a predetermined count value, the display start position signal generation circuit 704 outputs a display start position signal, which is sent to the display unit via the display drive circuit. As a result, video display is started from the vertical position where the display start position signal is generated.

Generally, as shown in FIG. 7, an image in the interlaced scanning system forms one screen by two vertical scans, and one vertical scan is called a field. In FIG. 7, reference numeral 801 denotes vertical scanning in the first field;
Reference numeral 802 denotes vertical scanning in the second field. And
Reference numeral 803 denotes a state of one screen in which 801 and 802 are overlapped. Thereafter, by repeating this vertical scanning, the image can be viewed as a continuous image.

[0009] Of the two vertical scans, the odd-numbered vertical scan field is called an odd-numbered field, and the even-numbered vertical scan field is called an even-numbered field. Reference numeral 804 indicates that the same vertical scanning is performed in the same field in the odd field and the even field.
That is, odd fields scan on the same line, and even fields scan the same line.

FIG. 8 is a waveform diagram showing the relationship between a waveform and a continuous field over time. In FIG. 8, 90
Reference numeral 1 denotes a relative relationship between a vertical synchronizing signal input, a horizontal synchronizing signal input, and a screen display start position signal output in an odd field (or an even field) of a certain video N. As a delicate positional relationship with respect to the input of the synchronization signal, it is in a state slightly before (immediately before) the input of the horizontal synchronization signal.

Reference numeral 902 denotes a relative relationship between a vertical synchronizing signal input, a horizontal synchronizing signal input, and a screen display start position signal output in an even field (or odd field) of a certain video N. Since the field is different from that of the synchronization signal input, the phase is shifted by 水平 horizontal period, and the phase relationship between the vertical synchronization signal input and the horizontal synchronization signal input is not delicate.

Reference numeral 903 indicates the relative relationship between the input of the vertical synchronizing signal, the input of the horizontal synchronizing signal, and the output of the screen display start position signal in the odd field (or even field) of the next image (N + 1). Since the vertical synchronization signal input comes to a position shifted by 水平 horizontal period from 902, the synchronization signal input again has a delicate positional relationship.

At this time, if the input of the vertical synchronization signal includes jitter and is delayed, the input of the vertical synchronization signal relatively straddles the input of the horizontal synchronization signal, and the input of the vertical / vertical synchronization signal becomes relatively horizontal. It may be located immediately after the signal input (rising). The screen display start position signal output has the same type (odd or even) field relationship as compared with the odd field (or even field) in the video N because the input of the horizontal synchronization signal is counted after the input of the vertical synchronization signal. Despite this, the display start position is different.

Reference numeral 904 denotes a relative relationship between the input of the vertical synchronizing signal, the input of the horizontal synchronizing signal, and the output of the screen display start position signal in the even field (or the odd field) of the video (N + 1). Is further shifted by 水平 horizontal period from 903, and there is no delicate positional relationship, indicating that the screen display start position signal is output at the same position in the same type of field.

In the conventional display device, the vertical synchronizing signal externally desynchronized includes jitter, and the counter circuit 702 determines whether or not the vertical synchronizing signal input crosses the horizontal synchronizing signal output as a relative operation. Depends on whether the horizontal synchronization signal is counted or not, ie, whether the result of the comparison circuit 703 is delayed by one horizontal synchronization period or not, and the phenomenon of the display start position signal generation circuit 704 in the vertical direction occurs. The display start position signal also changes, and the image screen is lowered by one horizontal scan. When the relative phase relationship between the vertical synchronization signal and the horizontal synchronization signal is at a delicate position, the image screen shakes in the vertical direction. Or flickering occurs.

[0016]

In the above-mentioned conventional screen display control device, the vertical synchronizing signal externally synchronized and separated contains jitter, and the relative phase relationship between the input of the vertical synchronizing signal and the input of the horizontal synchronizing signal. In the state before and after, there is a problem that the position of the display start position signal changes in spite of being in the same odd-numbered field (or even-numbered field), which causes the screen to fluctuate vertically and flicker. Was.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, in which a vertical sync signal externally sync-separated contains jitter, and a relative relationship between a vertical sync signal input and a horizontal sync signal input is provided. Even when the phase relationship is
In the same odd field (or even field), a display start position correction method and a screen display control device capable of preventing the screen from swaying or flickering in the vertical direction without changing the position of the display start position signal. The purpose is to provide.

[0018]

According to a first aspect of the present invention, there is provided a display start position correcting method for correcting a vertical display start position of an image displayed on a screen based on an interlaced video signal. It is determined whether the vertical synchronization signal synchronously separated from the video signal is located immediately before or immediately after the horizontal synchronization signal synchronously separated from the video signal, and is located immediately before or immediately after the horizontal synchronization signal. Based on the determination result, the vertical display start position of the image is corrected so as to keep the vertical display start position of the image constant.

According to this method, the same odd number is used even when the vertical sync signal externally sync-separated contains jitter and the relative phase relationship between the vertical sync signal input and the horizontal sync signal input fluctuates. In a field (or an even field), it is possible to prevent the screen from fluctuating or flickering in the vertical direction without changing the position of the display start position signal.

According to a second aspect of the present invention, there is provided a screen display control apparatus for controlling a vertical display start position of an image displayed on a screen based on an interlaced scanning video signal. Phase determining means for determining whether the vertical synchronizing signal is located immediately before or immediately after the horizontal synchronizing signal separated from the video signal, and different display start position correction information according to the determination result by the phase determining means. A correction information selection circuit that selectively outputs, a display start position setting information storage circuit that stores normal display start position setting information,
An adding circuit for adding the normal display start position setting information and the display start position correction information; a counter circuit for counting the number of horizontal synchronization signals after the input of the vertical synchronization signal; an output value of the counter circuit and an output of the addition circuit A comparison determination circuit for comparing the output value of the counter circuit with the output value of the addition circuit or exceeding the output value of the addition circuit, and a display start position signal in response to the output of the comparison determination circuit. And a display start position signal generation circuit for generating And
The correction information selection circuit selects the correction information so as to keep the vertical display start position of the image constant.

According to this configuration, the correction information selection circuit selects the correction information so as to keep the vertical display start position of the image constant according to the determination result of the phase determination means. Even when the vertical sync signal contains jitter and the relative phase relationship between the vertical sync signal input and the horizontal sync signal input fluctuates, the position of the display start position signal is not changed in the same odd field (or even field). Without changing, it is possible to prevent the screen from swaying and flickering in the vertical direction.

According to a third aspect of the present invention, in the screen display control apparatus according to the second aspect, the phase determining means resets the count value in response to the input of a vertical synchronizing signal separated from the video signal. Counter circuit for counting clocks having a frequency higher than the horizontal frequency, stopping the clock count in response to the input of a horizontal synchronization signal that is synchronously separated from the video signal, and holding the count value A determination reference value storage circuit storing a phase difference determination reference value for determining a phase difference between the vertical synchronization signal and the horizontal synchronization signal; and a count held by the phase difference determination reference value and the phase difference extraction counter circuit. And a phase difference comparison determination circuit that determines whether the count value exceeds a phase difference determination reference value.

According to this configuration, the phase difference between the vertical synchronizing signal and the horizontal synchronizing signal is extracted as a clock count value by the phase difference extraction counter circuit, and the count value is compared with the phase difference determination reference value. Whether the vertical synchronization signal is located immediately before or immediately after the horizontal synchronization signal is determined depending on whether the value exceeds the phase difference determination reference value, so that the vertical synchronization signal is located immediately before or immediately after the horizontal synchronization signal. Can be easily determined.

According to a fourth aspect of the present invention, in the screen display control apparatus according to the third aspect, the phase difference determination reference value is a value corresponding to a period of three quarters of one horizontal cycle.

According to this configuration, the same operation as that of the third aspect is provided.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment) FIG. 1 is a schematic block diagram showing a circuit configuration of a screen display device according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a vertical synchronizing signal input that is synchronously separated from a video signal, and 102 denotes a horizontal synchronizing signal input that is synchronously separated from a video signal.

Reference numeral 103 denotes a counter whose value is reset in response to the input of the vertical synchronizing signal 101, starts counting a clock having a frequency higher than the horizontal frequency, and stops counting the clock in response to the input of the horizontal synchronizing signal 102. And a phase difference extraction counter circuit that holds a count value.

Reference numeral 104 denotes a determination reference storing a phase difference determination reference value (for example, a value corresponding to a period of three quarters of a horizontal cycle) for determining a phase difference between the vertical synchronization signal 101 and the horizontal synchronization signal 102. It is a value storage circuit.

A phase difference comparing and judging circuit 105 compares the phase difference judging reference value with the count value held by the phase difference extracting counter circuit 103, and judges whether or not the count value exceeds the phase difference judging reference value. It is.

The above-described phase difference extraction counter circuit 103, judgment reference value storage circuit 104, and phase difference comparison judgment circuit 105
Thus, the phase determination unit 120 that determines whether the vertical synchronization signal 101 is located immediately before or immediately after the horizontal synchronization signal 102 is configured.

Numeral 106 denotes a correction information selection circuit for selectively outputting different display start position correction information in accordance with the result of the determination by the phase determination means 120. The correction information selection circuit 106 controls the correction information so as to keep the vertical display start position of the image constant. Select

Reference numeral 107 denotes a display start position setting information storage circuit for storing normal display start position setting information.

Reference numeral 108 denotes an addition circuit for adding normal display start position setting information and display start position correction information.

A counter circuit 109 counts the horizontal synchronization signal 102 after the input of the vertical synchronization signal 101.

The reference numeral 110 compares the output value of the counter circuit 109 with the output value of the adder circuit 108, and
Is a comparison determination circuit for determining that the output value of the adder circuit 108 matches or exceeds the output value of the adder circuit 108.

Reference numeral 111 denotes a display start position signal generation circuit for generating a display start position signal in response to the output of the comparison and judgment circuit 110.

Reference numeral 112 denotes a display start position signal output transmitted to the display unit via the display driving circuit.

The operation of the above configuration will be described below. A vertical synchronization signal input 101 and a horizontal synchronization signal input 102 are input to a phase difference extraction counter circuit 103. The vertical synchronizing signal input 101 and the horizontal synchronizing signal input 102 are also input to a counter circuit 109 that counts the horizontal synchronizing signal after the input of the vertical synchronizing signal.

The output of the phase difference extraction counter circuit 103 and the output of the judgment reference value storage circuit 104 are input to a phase difference comparison judgment circuit 105, and the output of the phase difference comparison judgment circuit 105 is input to a correction information selection circuit 106. You. The output of the correction information selection circuit 106 and the output of the normal display start position setting information storage circuit 107 are input to the addition circuit 108 and added. The output of the adder circuit 108 and the output of the counter circuit 109 that counts the horizontal synchronization signal after the input of the vertical synchronization signal are input to the comparison determination circuit 110,
Both are compared. Further, the comparison result of the comparison determination circuit 110 is input to the display start position signal generation circuit 111, and the output of the display start position signal generation circuit 111 is transmitted to the display start position signal output 112 transmitted to the display unit via the display drive circuit. Is done.

A description will be given of the screen display device of the present embodiment configured as described above and a display start position correction method performed by the screen display device.

The vertical synchronizing signal input 101 and the horizontal synchronizing signal input 102 are input to a counter circuit 103 for phase difference extraction. The vertical synchronizing signal input 101 and the horizontal synchronizing signal input 102 are also input to a counter circuit 109 that counts the horizontal synchronizing signal after the input of the vertical synchronizing signal.

The output of the phase difference extraction counter circuit 103 and the output of the judgment reference value storage circuit 104 are compared by a phase difference comparison judgment circuit 105 to determine whether the vertical synchronization signal input 101 has crossed the horizontal synchronization signal input 102. That is, it is determined whether the vertical synchronization signal input 101 is located immediately before or immediately after the horizontal synchronization signal input 102, and a comparison result is output.

The correction information selection circuit 106 selects the stored value (information of "1" or "0") as to whether or not to perform the correction in accordance with the result of the determination by the phase difference comparison and determination circuit 105. ,Output. This value is used as an addition circuit 10 described later.
8 is added.

Then, the output value of the normal display start position setting information storage circuit 107 and the output value of the correction information selection circuit 106 are added by the addition circuit 108. The output result of the adding circuit 108 becomes a horizontal synchronization count value for outputting the corrected display start position signal.

Here, the above horizontal synchronization count value will be specifically described. Display start position setting information storage circuit 1
If the value at 07 is set to, for example, N, if no correction is made, a display start position signal is output from the display start position signal generation circuit 111 at N + 1, and if correction is applied, N + 0
Outputs a display start position signal. When the vertical synchronizing signal input 101 crosses the horizontal synchronizing signal input 102, a correction is applied, and a display start position signal is output at N. When there is no change, the display start position signal is output at N + 1 because no correction is applied.

On the other hand, the counter circuit 109 for counting the horizontal synchronization signal after the input of the vertical synchronization signal counts the horizontal synchronization signal. The count value is compared with the output value of the addition circuit 108 by the comparison / judgment circuit 110. , Adder circuit 10
6, the display start position signal output circuit 112 generates a display start position signal in the display start position signal generation circuit 111 and transmits the display start position signal output 112 to the display unit via the display drive circuit.
Output as

By the operation of the screen display control device as described above, the vertical synchronizing signal 101 synchronously separated from the video signal.
Is determined immediately before or immediately after the horizontal synchronization signal 102 synchronously separated from the video signal, and based on the determination result as to whether the image is located immediately before or immediately after the horizontal synchronization signal 102, The display start position correction method of correcting the vertical display start position of the image so as to keep the vertical display start position of the image constant.

Here, a method of determining the phase difference between the vertical synchronization signal input 101 and the horizontal synchronization signal input 102 will be described.

FIG. 2 is considered as a range where the vertical synchronizing signal in the same odd field (or even field) in the vertical synchronizing signal input and the horizontal synchronizing signal input exceeds or does not exceed (straddles or does not cross) the horizontal synchronizing signal. FIG. 4 is a waveform diagram showing a relative relationship between phases. In FIG.
1 is a vertical synchronization signal input, 202 is a horizontal synchronization signal input, 2
03 is one horizontal synchronization period of the horizontal synchronization signal input 202, 20
4 indicates that the vertical synchronization signal input 201 is the horizontal synchronization signal input 202
205 indicates a range after the vertical synchronization signal input 201 crosses the horizontal synchronization signal input 202.

The range 204 before the straddling and the range 205 after the straddling have a phase difference of ＨH between the odd field and the even field. It can be in the range of 1 / 4H. When the vertical sync signal input 201 is in the vicinity of, not exceeding, the horizontal sync signal input 202 in the odd field (or even field), the vertical sync signal input of the other even field (or odd field) and the horizontal sync signal Since the relative relationship of the input is always shifted by 水平 horizontal period as compared with the relationship between the odd field and the even field in the related art, the input does not come to a nearby position that does not straddle.

In the odd field (or even field), the vertical synchronizing signal input 201 is
Assuming that the vertical synchronization signal input 201 exceeds the horizontal synchronization signal input 202 and does not exceed the horizontal synchronization signal input 202, it is considered that the vertical synchronization signal input 201 exceeds the horizontal synchronization signal input 202 in the period before the range 204 and the range 205 after the range. Can be.

FIG. 3 is a schematic diagram showing the operation of the phase difference extraction counter circuit. In FIG. 3, reference numeral 301 denotes a vertical synchronization signal input. Reference numeral 302 denotes an output operation of the phase difference extraction counter circuit. Reference numeral 303 denotes a count period of one horizontal synchronization period of the output operation 302 of the phase difference extraction counter circuit, and reference numeral 304 denotes an output operation 30 of the phase difference extraction counter circuit.
2 indicates a 3/4 horizontal synchronization period, and 305 indicates the count-up operation in the output operation 302 of the phase difference extraction counter circuit as a gradient. Reference numeral 306 denotes a horizontal synchronization signal input.

In FIG. 3, when a vertical synchronization signal input 301 comes in, the output operation 3 of the phase difference extraction counter circuit is started.
02 is reset. Then, the vertical synchronization signal input 30
The counting operation is performed after 1 is input until the horizontal synchronization signal 306 is input, and when the horizontal synchronization signal 306 is input, the counting operation is stopped. Then, the vertical synchronization signal input 30
The count value is held until 1 is input.

In the output operation 302 of the phase difference extraction counter circuit, if the count value is within the range of 3/4 horizontal synchronization period or more and less than one horizontal synchronization period, it can be seen from the immediately preceding horizontal synchronization signal. , １ ／ horizontal synchronization period. In other words, it can be said that the vertical synchronization signal is located at the position of the range 205 after exceeding the horizontal synchronization signal.

Conversely, if the period is less than the 3/4 horizontal synchronization period, the vertical synchronization signal does not extend beyond the horizontal synchronization signal in that field, and the range before the vertical synchronization signal exceeds the horizontal synchronization signal in the other field. 204.

Therefore, the phase relationship is determined based on whether or not the number corresponding to the 3/4 horizontal synchronization period 304 has been counted.

Here, the reason why the number corresponding to the 3/4 horizontal synchronization period 304 is used as the criterion for determining the phase relationship will be described. The phase difference between the odd and even fields is
0.5H (on the principle of interlaced scanning). Now, suppose that the vertical synchronization signal is in a subtle position in the odd-numbered field as to whether or not it straddles the horizontal synchronization signal. A jitter exceeding 0.5H is impossible in the interlaced scanning method. Now, it is a problem whether the signal crosses the horizontal synchronizing signal. Therefore, the range in which the jitter occurs may be a range between the 0.25H period before the horizontal synchronization signal and the 0.25H period after the horizontal synchronization signal. In terms of the circuit, it is only necessary to correspond to the range (0.25H after the horizontal synchronizing signal is input) when the frequency is exceeded. Further, the circuit measures the length from the input of the vertical synchronization signal to the input of the horizontal synchronization signal.
75H (= (3/4) H) may be used as a reference.

Since the width of the jitter is not predetermined, it is necessary to assume a maximum jitter of 0.5H. Considering this, the set value is (3/4) H.

However, the set value can be set to a value other than the above (3/4) H, for example, 0 to (3/4) H.
The smaller the value, the more difficult it becomes to correct when a jitter having a large width enters.

FIG. 4 is a schematic diagram showing the phase relationship before the vertical synchronization signal input in the same odd field (or even field) exceeds the horizontal synchronization signal. 4, reference numeral 401 denotes a vertical synchronization signal input, 402 denotes a horizontal synchronization signal input, and 403 denotes one horizontal synchronization period. Reference numeral 404 denotes an output operation of the phase difference extraction counter circuit. Reference numeral 405 indicates the count-up operation in the output operation 404 of the phase difference extraction counter circuit as a gradient, and 406 indicates a 3/4 horizontal synchronization period of the output operation 404 of the phase difference extraction counter circuit. Reference numeral 407 denotes a counting operation period of the output operation 404 of the phase difference extracting counter circuit from the input of the vertical synchronizing signal input 401 to the input of the horizontal synchronizing signal input 402.

Output operation 40 of the phase difference extraction counter circuit
Since the count value at 4 does not exceed the 3/4 horizontal synchronizing period, it is determined that the vertical synchronizing signal input 401 does not cross the horizontal synchronizing signal input 402 from the range 204 before straddling and the range 205 after straddling in FIG. can do.

FIG. 5 is a schematic diagram showing the phase relationship after the vertical synchronizing signal input in the same odd field (or even field) straddles the horizontal synchronizing signal. In FIG. 5, reference numeral 501 denotes a vertical synchronization signal input, 502 denotes a horizontal synchronization signal input, and 503 denotes one horizontal synchronization period. Reference numeral 504 denotes an output operation of the phase difference extraction counter circuit. Reference numeral 505 denotes the count-up operation in the output operation 504 of the phase difference extraction counter circuit, which is indicated by a gradient. Reference numeral 506 denotes a 3/4 horizontal synchronization period of the output operation 504 of the phase difference extraction counter circuit. Reference numeral 507 denotes a count operation period of the output operation 504 of the phase difference extraction counter circuit from the input of the vertical synchronizing signal input 501 to the input of the horizontal synchronizing signal input 502.

Output operation 50 of the phase difference extraction counter circuit
Since the count value at 4 exceeds the 3/4 horizontal synchronization period, it is determined that the vertical synchronization signal input 501 has straddled the horizontal synchronization signal input 502 from the range 204 before straddling and the range 205 after straddling in FIG. be able to.

That is, after the input of the vertical synchronizing signal, the counter circuit for extracting the phase difference is reset, and thereafter, the counter is counted until the input of the horizontal synchronizing signal first comes, and the count value is counted for 3/4 horizontal synchronizing period. It is determined whether the vertical synchronizing signal input exceeds or does not exceed the horizontal synchronizing signal input.

The polarity of the waveforms of the vertical synchronizing signal and the horizontal synchronizing signal shown in FIGS. 2, 3, 4, and 5 may be reversed depending on how the synchronization is separated.

As described above, according to the display start position correcting method of the present embodiment, the vertical sync signal externally sync-separated includes jitter, and the relative position between the vertical sync signal input and the horizontal sync signal input is increased. The same odd field (or even field) even when the phase relations change
In, without changing the position of the display start position signal,
It is possible to prevent the screen from swaying or flickering in the vertical direction.

Further, according to the screen display control device of this embodiment, the correction information selecting circuit 106 controls the correction information so that the display start position in the vertical direction of the image is kept constant according to the determination result of the phase determination means 120. Is selected, the jitter is included in the externally separated vertical sync signal, and even when the relative phase relationship between the vertical sync signal input 101 and the horizontal sync signal input 102 fluctuates, the same odd field ( (Or even field), the screen can be prevented from swaying and flickering in the vertical direction without changing the position of the display start position signal.

Further, a vertical synchronization signal input 101 and a horizontal synchronization signal input 102 are provided by a phase difference extraction counter circuit 103.
The phase difference is extracted as a clock count value, and this count value is compared with the phase difference determination reference value. Depending on whether the count value exceeds the phase difference determination reference value, the vertical synchronization signal is immediately before the horizontal synchronization signal. Since it is determined whether the vertical synchronization signal is located immediately after the horizontal synchronization signal, it can be easily determined whether the vertical synchronization signal is located immediately before or immediately after the horizontal synchronization signal.

[0070]

According to the display start position correcting method of the present invention, the vertical sync signal externally separated by the sync includes jitter, and the relative phase relationship between the vertical sync signal input and the horizontal sync signal input is reduced. Even in the preceding and following states, it is possible to prevent the screen from swaying and flickering in the vertical direction without changing the position of the display start position signal in the same odd field (or even field).

Further, according to the screen display control device of the present invention, the correction information selecting circuit selects the correction information so as to keep the display start position in the vertical direction of the image constant according to the determination result of the phase determining means. The same odd field (or even field) is used even in a state where the vertical sync signal externally separated by synchronization contains jitter, and the relative phase relationship between the vertical sync signal input and the horizontal sync signal input fluctuates.
In, without changing the position of the display start position signal,
It is possible to prevent the screen from swaying or flickering in the vertical direction.

As described above, by adding the correction information based on whether or not the vertical synchronization signal input straddles the horizontal synchronization signal input, even if the vertical synchronization signal input includes jitter, the screen display position can be reduced. , A superior display start position correction method and a screen display control device capable of maintaining the constant can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a circuit configuration of a screen display control device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a relative phase relationship between a vertical synchronization signal input and a horizontal synchronization signal input.

FIG. 3 is a schematic diagram illustrating the operation of a phase difference extraction counter circuit.

FIG. 4 is a schematic diagram showing a phase relationship before a vertical synchronization signal input in the same odd field (or even field) straddles a horizontal synchronization signal.

FIG. 5 is a schematic diagram showing a phase relationship after a vertical synchronization signal input in the same odd field (or even field) straddles a horizontal synchronization signal.

FIG. 6 is a schematic block diagram showing a circuit configuration of a conventional screen display control device.

FIG. 7 is a schematic diagram showing the relationship between interlaced scanning and fields.

FIG. 8 is a waveform diagram showing a relationship between a waveform and a continuous field over time.

[Explanation of symbols]

 101 Vertical sync signal input after sync separation 102 Horizontal sync signal input after sync separation 103 Phase difference extraction counter circuit 104 Judgment reference value storage circuit 105 Phase difference comparison and judgment circuit 106 Correction information selection circuit 107 Display start position setting information storage circuit Reference Signs List 108 adder circuit 109 counter circuit 110 comparison / judgment circuit 111 display start position signal generation circuit 112 display start position signal output 120 phase difference judgment means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 3/227 H04N 3/227 5/66 5/66 B

Claims (4)

[Claims] 1. A display start position correction method for correcting a display start position in a vertical direction of an image displayed on a screen based on a video signal of an interlaced scanning method, wherein the vertical synchronization signal is synchronously separated from the video signal. Is determined immediately before or immediately after the horizontal synchronization signal synchronously separated from the video signal, based on the determination result of whether located immediately before or immediately after the horizontal synchronization signal, the image A display start position in the vertical direction of the image is corrected so that the display start position in the vertical direction is kept constant. 2. A screen display control device for controlling a vertical display start position of an image displayed on a screen based on an interlaced scanning video signal, comprising: a vertical synchronization signal separated from the video signal by synchronization. Phase determination means for determining whether the position is located immediately before or immediately after a horizontal synchronization signal synchronously separated from the video signal; and selectively displaying different display start position correction information according to the determination result by the phase determination means. A correction information selection circuit that outputs the information, a display start position setting information storage circuit that stores normal display start position setting information, and an addition circuit that adds the normal display start position setting information and the display start position correction information. A counter circuit for counting the number of the horizontal synchronization signals after the input of the vertical synchronization signal, and comparing an output value of the counter circuit with an output value of the addition circuit, A comparison and judgment circuit for judging that the output value of the counter circuit matches the output value of the addition circuit or exceeds the output value of the addition circuit; and generating a display start position signal in response to the output of the comparison and judgment circuit. A display start position signal generation circuit, wherein the correction information selection circuit selects the correction information so as to keep a vertical display start position of the image constant. 3. The phase determination means resets a count value in response to an input of a vertical synchronization signal synchronously separated from a video signal and starts counting a clock having a frequency higher than a horizontal frequency. A counter circuit for extracting a phase difference that stops counting the clock and retains the count value in response to the input of the horizontally separated horizontal synchronization signal; and determining a phase difference between the vertical synchronization signal and the horizontal synchronization signal. A reference value storage circuit storing a phase difference determination reference value for comparing the phase difference determination reference value with the count value held in the phase difference extraction counter circuit, and determining the count value as the phase difference determination value. 3. The screen display control device according to claim 2, further comprising a phase difference comparison determination circuit that determines whether or not the value exceeds a reference value. 4. The phase difference determination reference value is a value corresponding to a period of three quarters of one horizontal cycle.
Screen display control device according to the above.