JP2013070261A - Synchronous signal control circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time required for synchronization to improve screen quality.SOLUTION: A synchronous signal control circuit for outputting a display synchronization clock, a display horizontal synchronization signal and a display vertical synchronization signal used for display of an input video signal, to a display unit capable of display based on the input video signal when a display frequency for the input video signal is in a predetermined allowable range, includes: a phase-difference detection section for detecting a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal; a display synchronization clock control section for controlling a frequency of the display synchronization clock in the allowable range so that the phase difference is reduced, on the basis of the detection result by the phase-difference detection section; and a synchronization signal generation section for generating the display horizontal synchronization signal and the display vertical synchronization signal by using the display synchronization clock controlled in clock frequency by the display synchronization clock control section.

Description

  The present invention relates to a synchronization signal control circuit and a display device.

  Conventionally, flat panel displays (hereinafter referred to as FPD) such as liquid crystal panels and plasma display panels have been widely used as display devices. In the FPD, an image is displayed by supplying a video signal (pixel signal) corresponding to each pixel. That is, the video signal supplied to the FPD is once held in the display memory, and the FPD performs display by reading out a pixel signal corresponding to each pixel of the FPD from the display memory and driving each pixel.

  Accordingly, horizontal and vertical synchronization signals (hereinafter referred to as display horizontal and vertical synchronization signals) used for display in the FPD are horizontal and vertical synchronization signals (hereinafter referred to as input horizontal and vertical) of video signals (input video signals) supplied to the FPD. It is generated asynchronously.

  The frequency of the display vertical synchronization signal of the FPD (hereinafter referred to as the display vertical synchronization frequency) is related to the reciprocal of the period of the vertical synchronization signal period, is determined by the display clock, the horizontal synchronization period, and the vertical synchronization period, and is unique to each display device. Value. Further, the unique value for each display device has an allowable range of the vertical synchronization period, and by providing a range of the minimum vertical synchronization period and the maximum vertical synchronization period (hereinafter referred to as a compensation period), the FPD can always input video. Signal-based display can be performed.

  As described above, the display vertical synchronization frequency of the FPD is different for each device, and the frequency of the input vertical synchronization signal of the input video signal (hereinafter referred to as the input vertical synchronization frequency) is considered to be different for each video source. Both do not match. Therefore, the display memory may overflow or underflow, and the FPD may have to skip or repeat the video signal at predetermined intervals.

  Accordingly, when the start position of the vertical synchronization of the input video signal enters the compensation period allowed for the display device, the synchronization circuit that performs the process of synchronizing the display vertical synchronization signal with the input vertical synchronization signal thereafter is the FPD. May be employed. This prevents the skipping of the video signal and the occurrence of the repeat phenomenon from being repeated.

  Further, in the FPD, an image from a game machine may be displayed, and it is preferable to reduce the delay time between the input image and the display image as much as possible. For this reason, at the time of the first synchronization described above, a process is performed in which the video signal is skipped only once and the delay time between the input image and the display image is minimized.

  However, depending on the phase difference and frequency difference between the display vertical synchronization signal and the input vertical synchronization signal, a relatively long time is required for synchronization. The maximum time required for synchronization corresponds to the screen size. For example, in an FPD for high-definition video display such as 4K2K (4400 × 2250 pixels), the time required for synchronization becomes extremely long. For this reason, for example, when a channel is switched or when the input vertical synchronization frequency is switched, a skip may occur at an unexpected timing several seconds after the switching, and the viewer may feel uncomfortable.

JP-A-11-331638

  It is an object of the present invention to provide a synchronization signal control circuit and a display device that can reduce the time required for synchronization and improve the screen quality.

  The synchronization signal control circuit of one embodiment of the present invention can display the input video signal with respect to a display portion that can display based on the input video signal when a display frequency for the input video signal is within a predetermined allowable range. Phase difference detection unit for detecting a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal in a synchronization signal control circuit for outputting a display synchronization clock, a display horizontal synchronization signal, and a display vertical synchronization signal to be used And a display synchronization clock control unit that controls the frequency of the display synchronization clock within the allowable range so that the phase difference is reduced based on the detection result of the phase difference detection unit, and the display synchronization clock control unit. A synchronization signal generator for generating the display horizontal synchronization signal and the display vertical synchronization signal using the display synchronization clock whose clock frequency is controlled; To Bei.

  According to the present invention, it is possible to improve the screen quality by reducing the time required for synchronization.

1 is a block diagram showing a synchronization signal control circuit according to a first embodiment of the present invention. 1 is a block diagram showing a display device in which a synchronization signal control circuit according to a first embodiment is incorporated. Explanatory drawing for demonstrating the synchronization method of patent document 1. FIG. Explanatory drawing for demonstrating the synchronization method of patent document 1. FIG. Explanatory drawing for demonstrating the synchronization method in 1st Embodiment. The block diagram which shows 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a synchronization signal control circuit according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a display device in which the synchronization signal control circuit according to the first embodiment is incorporated.

  First, the synchronization method in the present embodiment will be described with reference to FIGS. 3 and 4 are explanatory diagrams for explaining the synchronization method of Patent Document 1, and FIG. 5 is an explanatory diagram for explaining the synchronization method in the present embodiment.

  As shown in FIG. 2, the input video signal input to the input terminal 1 is supplied to the buffer 2. The buffer 2 is controlled to be written and read by the control unit 3, holds the input video signal for several frames, and outputs it to the display unit 4. The input video signal is also supplied to the control unit 3. The control unit 3 separates the input horizontal synchronization signal and the input vertical synchronization signal included in the input video signal and supplies them to the synchronization signal control circuit 10 and controls writing and reading of the buffer 2. In addition, the control unit 3 supplies display cycle size setting information described later to the synchronization signal control circuit 10.

  The synchronization signal control circuit 10 generates a display horizontal synchronization signal, a display vertical synchronization signal, and a display synchronization clock (hereinafter referred to as various synchronization signals) on the basis of a signal supplied from the control unit 3 and supplies the display unit 4 with the display horizontal synchronization signal. Supply. The display unit 4 performs display based on the video signal from the buffer 2 using various synchronization signals. That is, the display unit 4 displays each pixel in synchronization with the display synchronization clock, displays each line in synchronization with the display horizontal synchronization signal, and displays each screen in synchronization with the display vertical synchronization signal.

  The cycle of the display synchronization clock corresponds to the period required for display per pixel, and {screen switching frequency (display frequency) × total number of pixels in one screen} is the display synchronization clock frequency. Accordingly, the display frequency is expressed as display synchronization clock frequency / total number of pixels.

  In this embodiment, when the input vertical synchronization signal and the display vertical synchronization signal are asynchronous, such as when the power is turned on, when the channel is switched, and when the input vertical synchronization frequency is switched, the input vertical of the input video signal is input. By forcibly setting the display frequency higher or lower than the synchronization frequency, the start timing of the vertical synchronization of the input video signal is matched with the start timing of the display vertical synchronization. Thereby, the display vertical synchronizing signal is synchronized with the input vertical synchronizing signal thereafter.

  In the invention of Patent Document 1, the display frequency is changed by changing the vertical synchronization period (display vertical synchronization period) in the display device, thereby enabling synchronization. In this case, in the invention of Patent Document 1, the display vertical synchronization period is set within the compensation period that can be displayed on the display device in order to display the input video even during the period until the synchronization.

  In FIG. 3, the vertical synchronization period includes a period corresponding to the effective display area and the blanking area (shaded area). The vertical synchronization period is set to the period of the display vertical synchronization signal. In general, a display device has a permissible range in a displayable vertical synchronization period. That is, in the display device, the vertical synchronization period of the input video signal (hereinafter referred to as the input vertical synchronization period) is defined by the minimum vertical synchronization period Vs and the maximum vertical synchronization period Vl set before and after the standard vertical synchronization period. Within the compensation period, display based on the input video signal can be performed.

  The display vertical synchronization signal in the initial state of the display device is a standard vertical synchronization signal (Vbase). The vertical synchronization period based on the standard vertical synchronization signal is also denoted as a standard vertical synchronization period Vbase. In this case, as shown in FIG. 3, Vl> Vbase> Vs.

  In the invention of Patent Document 1, the synchronization method of FIG. 4 is adopted. FIG. 4 shows the start point of the vertical synchronization, that is, the vertical synchronization signal by the vertical line indicating the frame delimiter with the time axis in the horizontal direction. In FIG. 4, the upper part shows the writing of each frame of the input video signal to the buffer 2, and the lower part shows the display of the video signal read from the buffer 2.

  The numbers in parentheses indicate the buffer area number of the buffer 2 that holds each frame of the input video signal. In the example of FIG. 4, the video signal of each frame is temporarily held in the buffer area of 4 frames of the buffer 2. It is shown that. Each successive frame of the input video signal is cyclically written in each buffer area having the buffer 2 number 1 to 4.

  The upper vertical line in FIG. 4 indicates the input vertical synchronization signal, and the lower vertical line indicates the display vertical synchronization signal that is the vertical synchronization signal of the display device. In the example of FIG. 4, the video signal stored in the buffer area with the number 1 is displayed during the writing of the input video signal to the buffer area with the number 2 after the synchronization request, that is, one frame delay. Shows the display.

  In the device of Patent Document 1, in order to prevent the image from being broken due to synchronization, the display device first displays asynchronously with the input video signal. In this case, the display device performs display using a standard vertical synchronization signal (Vbase).

  That is, the apparatus of Patent Document 1 monitors the input vertical synchronization signal and detects whether or not the input vertical synchronization start point has entered the compensation period. If the input vertical synchronization start point is not detected within the compensation period, a display vertical synchronization signal is generated and used for display. That is, in the apparatus of Patent Document 1, it is unclear whether or not the input vertical synchronization start point falls within the compensation period until the input vertical synchronization start point is detected. Therefore, the display vertical synchronization signal is generated in the maximum vertical synchronization period Vl until the input vertical synchronization start point enters the compensation period. Thus, in order to detect whether or not the input vertical synchronization start point falls within the compensation period, it is necessary to delay the display vertical synchronization start point until the compensation period is full. FIG. 4 shows this state, in which the generation timing of the display vertical synchronization signal (display vertical synchronization start point) is gradually delayed with respect to the input vertical synchronization signal, and finally the input vertical synchronization start point is within the compensation period. Will occur.

  As described above, in the proposal of Patent Document 1, it is necessary to generate the display vertical synchronization signal in the maximum vertical synchronization period Vl until the input vertical synchronization start point enters the compensation period, and it takes a long time to synchronize. There is.

For example, in a general FPD, a compensation period of about ± 10 lines can be considered. In the technique of Patent Document 1, the compensation period is set to ± 5 lines, for example, and the maximum value of the time required for synchronization in the display device of the 4K2K (4400 × 2250 pixels) panel (pull-in time) is obtained. Since the shift is shortened by 5 lines per input vertical synchronization period, when the shift between the input vertical synchronization start point and the display vertical synchronization start point is the maximum (2250 lines), the maximum pull-in time is
Maximum pull-in time = 2250/5 (V) = 450 V = about 7.5 seconds.

  On the other hand, in the present embodiment, the display frequency is changed by changing the display synchronization clock, and synchronization is possible in a relatively short time.

  In this embodiment, the synchronization method shown in FIG. 5 is adopted.

  The vertical line in FIG. 5A indicates the input vertical synchronization signal input to the synchronization signal control circuit 10, the vertical line in FIG. 5B indicates the display vertical synchronization signal output from the synchronization signal control circuit 10, FIG. 5C shows a display synchronization clock. When the display synchronization clock is adapted to high-definition broadcasting, for example, 1125 clocks are generated in one display vertical synchronization period. FIG. 5C shows a small number of clocks for simplification of the drawing. . In addition, it is assumed that the time transitions from the left to the right. In the present embodiment, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal (hereinafter also simply referred to as phase difference) is detected, and the frequency of the display synchronization clock is changed so as to reduce the detected phase difference. It is like that. The display synchronization clock frequency corresponding to the frame rate of the input video signal and the total number of pixels in one screen is referred to as the reference display synchronization clock frequency.

  In the display device, an allowable range is provided for the frequency of the display synchronization clock. That is, in the display device, video display based on the input video signal is possible even when the display synchronization clock frequency is slightly changed for the same input video signal. For example, the allowable range of the display synchronization clock frequency is generally about ± (several% to about 10%).

  If the display sync clock frequency is set lower than the reference display sync clock frequency within the allowable range of the display sync clock frequency for the same input video signal, the frame rate of the display video will be lower than the frame rate of the input video signal. On the contrary, if it is set higher, the frame rate of the display video is higher than the frame rate of the input video signal. That is, if the display synchronization clock frequency is set lower than the reference display synchronization clock frequency, the phase changes so that the display vertical synchronization signal is delayed with respect to the input vertical synchronization signal. The phase changes so that the display vertical synchronizing signal advances. Thus, even when the input vertical synchronization start timing and the display vertical synchronization start timing are different at the time of channel switching or the like, the input vertical synchronization start timing and the display vertical synchronization can be changed by changing the display synchronization clock frequency. In other words, the phase difference can be made zero.

  In this embodiment, in order to reduce the phase difference in a short time, the frequency of the display synchronization clock is changed so that the phase of the display vertical synchronization signal matches the phase of the input vertical synchronization signal close in time. Determine the direction.

  FIG. 5 shows an example (δi <(1125/2)) in which the phase of the display vertical synchronization signal is close to the phase of the input vertical synchronization signal later in time among the two input vertical synchronization signals preceding and following in time. Show. In this case, the frequency of the display synchronization clock is set lower than the reference display synchronization clock frequency within an allowable range. In the example of FIG. 5, the reference display synchronization clock frequency is Xi to Xi + 3 MHz, and when the synchronization process is started, the display synchronization clock frequency is set to frequencies Xi + 1, Xi + 2 MHz lower than Xi MHz. To do.

  As a result, the phase difference δi between the input vertical synchronization signal and the display vertical synchronization signal decreases to the phase difference δi + 1 (δi> δi + 1) at the next input vertical synchronization start timing. Further, in the next display vertical synchronization period, the display synchronization clock frequency is set to a frequency Xi + 2 MHz lower than Xi + 1 MHz, and in the next display vertical synchronization period, the display synchronization clock frequency is set to Xi + 3 MHz. To do. The frequencies Xi + 1 and Xi + 2 may be the same frequency.

  Thus, in the example of FIG. 5, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal is reduced to the phase difference δi + 2 (δi> δi + 1> δi + 2). And the start timing of display vertical synchronization coincide with each other.

  In the present embodiment, the phase difference between the display vertical synchronization signal and the input vertical synchronization signal is sequentially detected, and the frequency of the display synchronization clock is determined so that this phase difference becomes small. As a result, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal can be made sufficiently small, and the start timing of the input vertical synchronization and the start timing of the display vertical synchronization should be made substantially coincident after a predetermined period. Can do.

  In the example of FIG. 5, the example in which the frequency of the display synchronization clock is changed for each display vertical synchronization period is shown, but the frequency of the display synchronization clock may be changed for every arbitrary period. There is an advantage that other control becomes easy by changing the frequency of the clock for each display vertical synchronization period. Further, in order to improve the reliability of display, it may be driven at the standard display synchronization clock frequency during the effective display area, and the display synchronization clock frequency may be changed in the blanking area.

  In FIG. 1, display cycle size setting information is input to the input terminal 11, and an input vertical synchronization signal is input to the input terminal 12. The display cycle size setting information is information that gives the frame rate of the input video signal and the number of horizontal and vertical pixels of one screen. The display cycle size setting information is provided to the display synchronization clock control unit 13, and the input vertical synchronization signal is provided to the phase difference detection unit 15.

  The display synchronization clock control unit 13 calculates the standard display synchronization clock frequency by obtaining the frame rate and the number of horizontal and vertical pixels of the input video signal based on the display cycle size setting information. The display synchronization clock control unit 13 controls the display synchronization clock generation unit 14 based on the standard display synchronization clock frequency or the display synchronization clock frequency obtained by calculation described later.

  The display synchronization clock generation unit 14 is controlled in frequency by the display synchronization clock control unit 13 and generates a display synchronization clock used for display of each pixel in the display unit 4. The display synchronization clock is output to the display unit 4 via the terminal 18 and is also supplied as a clock to the display synchronization clock control unit 13, the phase difference detection unit 15, the display synchronization vertical counter 16, and the display synchronization signal generation unit 17. Supplied.

  As the display synchronous clock generation unit 14, a spread spectrum clock generator having high noise resistance performance by changing the generated frequency can be adopted.

  The display horizontal synchronization signal and the display vertical synchronization signal (hereinafter referred to as display synchronization signal) supplied to the display unit 4 are generated by the display synchronization signal generation unit 17. The display synchronization signal generation unit 17 outputs the generated display vertical synchronization signal to the display unit 4 via the terminal 19 and also outputs it to the display synchronization vertical counter 16 and the display synchronization clock control unit 13.

  The display synchronization vertical counter 16 receives the display vertical synchronization signal as a reset signal Reset, and counts up the display synchronization clock while being reset by the display vertical synchronization signal. That is, the output of the display synchronization vertical counter 16 indicates the number of display synchronization clocks from the display vertical synchronization start position. The count value from the display synchronization vertical counter 16 is output to the phase difference detector 15.

  The phase difference detector 15 obtains the count value of the display synchronization vertical counter 16 at the timing of the input vertical synchronization signal. That is, the phase difference detection unit 15 calculates and outputs the number of display synchronization clocks from the display vertical synchronization start position to the input vertical synchronization start position, that is, the phase difference between the display vertical synchronization signal and the input vertical synchronization signal. This phase difference is supplied to the display synchronization clock controller 13.

  Based on the display cycle size setting information, the display synchronization clock control unit 13 determines how many clocks of the display synchronization clock the input horizontal synchronization period and the input vertical synchronization period correspond to, and calculates these values horizontally and vertically. The count set value is output to the display synchronization signal generator 17. The display synchronization signal generator 17 is supplied with the output of the display synchronization vertical counter 16 and generates a display horizontal synchronization signal when the horizontal count set value is reached, and when it reaches the vertical count set value, the display vertical synchronization is generated. Generate a signal. As described above, these display synchronization signals from the display synchronization signal generation unit 17 are supplied to the display unit 4 via the terminal 19.

  The display synchronization clock control unit 13 is also provided with the phase difference and the output of the display synchronization vertical counter 16. The display synchronization clock control unit 13 obtains the number of display synchronization clocks corresponding to the input vertical synchronization period based on the display cycle size setting information, and from the phase difference detected by the phase difference detection unit 15, the phase of the current display vertical synchronization signal is It is determined whether or not the phase of any one of the two input vertical synchronization signals moving back and forth in time is close to the phase. The display synchronization clock control unit 13 sets the display synchronization clock frequency higher than the reference display synchronization clock frequency when the phase of the current display vertical synchronization signal is close in time to the phase of the previous input vertical synchronization signal. When the phase of the input vertical synchronization signal is later in time, the display synchronization clock frequency is set lower than the reference display synchronization clock frequency. The display synchronization clock control unit 13 changes the setting of the display synchronization clock frequency at the start timing of display vertical synchronization.

  Next, the operation of the embodiment configured as described above will be described.

  Assume that a synchronization request is generated by channel switching or the like. An input vertical synchronization signal is input to the synchronization signal control circuit 10 via the input terminal 12. This input vertical synchronization signal is given to the phase difference detector 15. The phase difference detection unit 15 is supplied with the number of display synchronization clocks reset by the display vertical synchronization signal from the display synchronization vertical counter 16, and the phase difference detection unit 15 calculates the difference between the display vertical synchronization signal and the input vertical synchronization signal. The phase difference is obtained and output to the display synchronous clock control unit 13.

  The display synchronization clock control unit 13 determines, based on the output of the phase difference detection unit 15, whether the current display vertical synchronization start timing is close to the input vertical synchronization start timing that changes in time, and obtains the determination result. Based on this, the frequency of the display synchronization clock is controlled.

  Now, at the time of channel switching, for example, as shown in FIG. 5, it is assumed that the phase difference between the display vertical synchronization signal and the input vertical synchronization signal based on the display vertical synchronization signal is δi, and δi <input vertical synchronization period / 2 Suppose that In this case, the display synchronization clock control unit 13 sets the display synchronization clock frequency of the display synchronization clock generation unit 14 to be lower than the reference display synchronization clock frequency.

  The display synchronization clock generation unit 14 is controlled by the display synchronization clock control unit 13 to switch the display synchronization clock frequency at the display vertical synchronization start timing. As a result, a display synchronization clock having a frequency lower than the reference display synchronization clock frequency is generated and output to the output terminal 18 and to the display synchronization vertical counter 16. The display synchronization vertical counter 16 counts the display synchronization clock, and the display synchronization signal generation unit 17 determines that the display horizontal synchronization signal and the display synchronization signal and the vertical synchronization count counter 16 have reached the horizontal and vertical count set values. Generate display vertical sync signal.

  In this way, the display synchronization clock having a frequency lower than the reference display synchronization clock frequency and the display horizontal synchronization signal and the display vertical synchronization signal generated based on the display synchronization clock are supplied to the display unit 4. The display unit 4 performs display using a display synchronization clock, a display horizontal synchronization signal, and a display vertical synchronization signal. Since the display synchronization clock frequency is lower than the reference display synchronization clock frequency corresponding to the input video signal, the display frequency is lower than the display frequency corresponding to the input video signal, and the phase difference is reduced as shown in FIG. .

  The phase difference detection unit 15 detects the phase difference for each display vertical synchronization period, and the display synchronization clock control unit 13 sets the display synchronization clock frequency so as to reduce the phase difference based on the detection result of the phase difference. As shown in FIG. 5, the phase difference gradually decreases and becomes zero. Thus, synchronization between the input vertical synchronization signal and the display vertical synchronization signal is achieved.

Now, when the allowable range of the display synchronization clock frequency is ± 5%, the maximum value of the time required for synchronization in the display device of the 4K2K (4400 × 2250 pixels) panel (pull-in time) is obtained. Since the shift is shortened by 2250 × 0.05 lines per input vertical synchronization period, the maximum pull-in time when the shift between the input vertical synchronization start point and the display vertical synchronization start point is maximum (2250 lines). Is
Maximum pull-in time = 2250 / (2250 × 0.05) (V) = 20 V = about 0.34 seconds. Thus, in the present embodiment, the maximum pull-in time can be significantly shortened compared to the maximum pull-in time (about 7.5 seconds) proposed in Patent Document 1 described above.

  As described above, in the present embodiment, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal is detected, and the display synchronization clock frequency is changed so that the phase difference is reduced based on the detection result. Synchronization can be achieved in a very short time.

  In the above embodiment, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal is always detected, and the display synchronization clock frequency is changed so as to reduce the phase difference based on the detection result. Explained. However, if the start timing of input vertical synchronization enters the compensation period as a result of controlling the display synchronization clock frequency, the display synchronization clock frequency is set to the standard synchronization clock frequency and the display vertical synchronization signal is input vertically. You may control to synchronize with a synchronizing signal compulsorily.

(Second Embodiment)
FIG. 6 is a block diagram showing the second embodiment. In FIG. 6, the same components as those in FIG.

  In the first embodiment, synchronization processing is performed by controlling the display synchronization clock frequency. In contrast, in the present embodiment, in the synchronization process, not only the display synchronization clock frequency is controlled, but also the display vertical synchronization period is controlled to reduce the phase difference.

  The present embodiment is different from the first embodiment in that a display synchronous clock control unit 23 is employed instead of the display synchronous clock control unit 13. The display synchronization clock control unit 13 generates a horizontal count setting value and a vertical count setting value based on the display cycle size setting information and supplies them to the display synchronization signal generation unit 17. On the other hand, for the vertical count setting value, the display synchronization clock control unit 23 generates a vertical count correction value that is increased / decreased based on the phase difference within the compensation period, and sends it to the display synchronization signal generation unit 17. It comes to supply.

  The display synchronization clock control unit 23 generates a count value between the maximum vertical synchronization period Vl and the minimum vertical synchronization period Vs so that the phase difference is small as the vertical count correction value. For example, in the example of FIG. 5, the display synchronization clock control unit 23 generates a count value corresponding to the maximum vertical synchronization period Vl so that the phase difference is small. As a result, the phase of the display vertical synchronization signal from the display synchronization signal generation unit 17 can be gradually delayed with respect to the input vertical synchronization signal, and the phase difference can be made zero. Conversely, when the phase of the display vertical synchronization signal is advanced with respect to the input vertical synchronization signal, the display synchronization clock control unit 23 may generate a count value corresponding to the minimum vertical synchronization period Vs.

  In this case as well, the pull-in period is shortened by changing the period of the display vertical synchronizing signal in a direction in which the phase difference decreases quickly. In addition, by appropriately setting the set count value, it is possible to moderate the change in the display vertical synchronization period, and it is possible to prevent the image from deteriorating due to a sudden change in the vertical period.

  As described above, in this embodiment, the phase difference between the input vertical synchronization signal and the display vertical synchronization signal is detected, and not only the display synchronization clock is controlled so that the phase difference becomes small, but also the display is performed within the compensation period. The period of the vertical synchronization signal is changed. As a result, even when a video signal asynchronous with display synchronization is input, synchronization can be achieved in a short time.

  Note that the present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention.

    DESCRIPTION OF SYMBOLS 13 ... Display synchronous clock control part, 14 ... Display synchronous clock generation part, 15 ... Phase difference detection part, 16 ... Display synchronization vertical counter, 17 ... Display synchronous signal generation part

Claims (5)

When a display frequency for the input video signal is within a predetermined allowable range, a display synchronization clock, a display horizontal synchronization signal, and a display vertical used to display the input video signal for a display unit capable of displaying based on the input video signal In the synchronization signal control circuit that outputs the synchronization signal,
A phase difference detector for detecting a phase difference between the input vertical synchronization signal based on the input video signal and the display vertical synchronization signal;
Based on the detection result of the phase difference detection unit, a display synchronization clock control unit that controls the frequency of the display synchronization clock within the allowable range so as to reduce the phase difference;
A synchronization signal control circuit comprising a synchronization signal generation unit that generates the display horizontal synchronization signal and the display vertical synchronization signal using the display synchronization clock whose clock frequency is controlled by the display synchronization clock control unit. . The display unit is capable of display based on the input video signal when a vertical synchronization period of the input video signal is within a compensation period between a minimum vertical synchronization period and a maximum vertical synchronization period.
The synchronization signal generation unit changes the period of the display vertical synchronization signal within the range of the compensation period based on the detection result of the phase difference detection unit so that the phase difference becomes small. The synchronizing signal control circuit according to claim 1. The phase difference detection unit obtains a count value by counting the display synchronization clock while being reset by the display vertical synchronization signal, and obtains the phase difference by a count value at a timing of an input vertical synchronization signal. Item 3. The synchronization signal control circuit according to Item 1 or 2. When a display frequency for the input video signal is within a predetermined allowable range, a display synchronization clock, a display horizontal synchronization signal, and a display vertical used to display the input video signal for a display unit capable of displaying based on the input video signal In a synchronization signal control circuit that outputs a synchronization signal, a phase difference detection unit that detects a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal, and a detection result of the phase difference detection unit A display synchronization clock control unit that controls the frequency of the display synchronization clock within the allowable range so that the phase difference is small, and the display synchronization clock whose clock frequency is controlled by the display synchronization clock control unit. A synchronization signal control circuit comprising a synchronization signal generator for generating the display horizontal synchronization signal and the display vertical synchronization signal;
And a control unit that controls the synchronization signal control circuit and reads the video signal stored in the buffer and supplies the video signal as the input video signal to the display unit. The display unit is capable of display based on the input video signal when a vertical synchronization period of the input video signal is within a compensation period between a minimum vertical synchronization period and a maximum vertical synchronization period.
The synchronization signal generation unit changes the period of the display vertical synchronization signal within the range of the compensation period based on the detection result of the phase difference detection unit so that the phase difference becomes small. The display device according to claim 4.

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