JP2001319975A - Clock phase adjusting system and clock tree designing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that, in a method for designing a clock tree of ASIC (all containing IC, LSI, and VLSI), as a clock tree composing tool itself has a limit in performance even if a circuit scale increases, for example, in one system clock, an absolute time at a terminal is great, or a skew is great. SOLUTION: In a method for designing a clock tree of ASIC (all containing IC, LSI, and VLSI) which operates at a common cyclic clock and is constituted by a plurality of functional blocks in a layout, the clock tree is divided into the number of functional block or the number less than that, to restrict an absolute delay time and relative delay time (skew) by the number of steps of the clock tree.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an ASIC in general (I
The present invention relates to a clock phase adjustment system and a clock tree design method applied to C, LSI, and VLSI. In particular, when designing a large-scale ASIC, clock tree synthesis is performed, but this relates to improvement in timing such as delay (absolute delay time) and skew (variation in relative delay time).

[0002]

2. Description of the Related Art A conventional clock tree designing method for synchronously designing a semiconductor integrated circuit will be described.

FIG. 7 is a block diagram showing a case where a clock tree is generated in the prior art. Input clock buffer
The delay time from 11 to the end blocks 12, 13, 14 is kept to a minimum, and the delay time is obtained from the temporary wiring capacity. Then, the clock driver cells 15 are inserted corresponding to each of the end blocks 12, 13, and 14, thereby forming a clock tree. Here, since the clock tree is constructed from the root of one clock tree (the output of the input buffer 11 in FIG. 6), the number of clock tree stages (the number of clock buffer series stages) is three.

Since the absolute delay of the entire clock tree is the sum of the cell delay for three clock buffers and the wiring delay, the cell delay per clock buffer is simply calculated as Tck
Assuming that buf, the wiring delay per line is Twire, Tdelay = 3 * Tckbuf + 3 * Twire (Equation 1).

[0005]

However, in the above-mentioned prior art, the performance of the clock tree synthesis tool itself is limited. Therefore, even if a single system clock is used, if the circuit scale becomes large, the end of the clock tree synthesis tool may be reduced. The absolute time of the skew was increased and the skew was increased.

[0006] When phase locking is performed using an internal PLL, improving the skew to the end requires a plurality of internal PLLs.
Although it is not impossible if L is used, there are problems that the circuit scale of the internal PLL itself becomes large and the number of terminals increases because a dedicated power supply is required.

In recent years, a configuration has been frequently used in which a clock tree is divided into a plurality of pieces so that clocks can be stopped so that power management can be performed in order to reduce power consumption. However, since the clock trees are different, there is a problem that clock skew occurs when signals between the clock trees move back and forth, and a layout correction time for adjusting the skew is required.

The present invention has been made to solve the above problems.

[0009]

According to a first aspect of the present invention, there is provided an ASIC clock phase adjusting system which operates with a clock having a common cycle and includes a plurality of functional blocks on a layout. A clock phase adjustment system characterized in that the clock phase adjustment system is configured to be divided into a plurality of pieces or less pieces.

According to a second aspect of the present invention, in a signal connection portion between the plurality of divided blocks, a phase adjusting means including switching of polarity of a clock is provided on the input side. 3. The clock phase adjustment system according to claim 1.

According to a third aspect of the present invention, in a signal connection portion between the plurality of divided blocks, a phase adjusting means including switching of polarity of a clock is provided on the output side. 2. The clock phase adjustment system according to item 1.

A fourth aspect of the present invention is the clock phase adjusting system according to the second or third aspect, wherein the polarity switching is supplied from a microcomputer.

According to a fifth aspect of the present invention, there is provided a clock tree designing method for an ASIC (including all ICs, LSIs, and VLSIs) which operates with a clock having a common cycle and is composed of a plurality of functional blocks on a layout. A clock tree design method is characterized in that the number of functional blocks is divided into a plurality of functional blocks or less, and the number of clock tree stages is reduced.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a clock tree is generated for each functional block divided into functional blocks.

FIG. 2 is a phase adjustment circuit diagram in which the clock polarity of the input FF can be switched.

FIG. 3 is a time chart for explaining the operation of FIG.

FIG. 4 is a phase adjustment circuit diagram in which the clock polarity of the output FF can be switched.

FIG. 5 is a system configuration diagram in which the clock polarity can be switched by parameter adjustment by the microcomputer, and is an application example of the present invention.

FIG. 6 is a configuration diagram of a clock tree incorporating power management.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram of the conventional example shown in FIG. 7 in which a clock tree is divided according to the number of blocks according to the present invention. That is, the clock tree is divided into a plurality by the number of the functional blocks or less,
Here, the division into each functional block makes the clock driver cell 15 inserted between the input clock buffer 11 and the end blocks 12, 13, 14 two stages, and the absolute delay time and the relative delay according to the number of clock tree stages. Time (skew) is reduced.

In general, the input and output of a plurality of flip-flops (FF) are connected in a complicated manner (although there is a difference between the presence and absence of a logic gate) in a functional block. In this case, naturally, the clock tree synthesis is performed so as to satisfy the Setup and Hold time of each FF. Conversely, in order for the functional block to operate correctly in clock synchronization, at least the clock supplied to the FF in the functional block needs to have a relative delay variation (skew) suppressed.

The problem is when data flows between functional blocks (inter-block wiring). That is, in a design having no inter-block wiring, if there is no skew in the clock supplied to the inside of the block, the block operates correctly in clock synchronization. However, if there is wiring between blocks, it is sufficient to simply drive with the same clock tree, but usually the number of FFs is different for each block, so if the clock tree is synthesized corresponding to them, delay is slow Therefore, the total number of clock tree stages increases, and the relative delay variation (skew) tends to deteriorate as the absolute delay increases.

By dividing the clock tree for each functional block, the above problem can be avoided, and the clock tree can be synthesized so as to minimize the absolute delay and skew.

When the absolute delay Tdelay of the entire clock tree in the above embodiment is obtained by a calculation method similar to the prior art, Tdelay = 2 * Tckbuf + 2 * Twire (Equation 2). Here, Tckbuf is the cell delay time per clock buffer, and Twire is the wiring delay per clock buffer.

The relative delay (clock skew) Tske
Since w generally tends to be proportional to the number of terminal clock buffers and the absolute delay of the entire clock tree, Tskew = Kd * Tdelay + Kbuf * Nbuf (Equation 3). Here, Kd is a proportional coefficient with respect to Tdelay, and Kbuf is a proportional coefficient with respect to the terminal clock buffer number Nbuf.

Accordingly, as can be seen from Equations 1 and 2, the absolute delay and the relative delay can be reduced by dividing the clock tree so as to reduce the number of stages per clock tree.

In FIG. 1, for the sake of simplicity, the description has been made on the assumption that there is no difference in absolute time between clock trees. However, in practice, the number of flip-flop (FF) circuits in each block is different, so that the difference in the number of clock tree stages or the number of terminal clock buffers may cause a difference in the absolute delay between the clock trees. .

FIGS. 2 and 3 illustrate an adjusting circuit for accommodating a variation in absolute delay between clock trees when there is a wiring between blocks in FIG.

FIG. 2 shows a configuration in which the clock polarity of the input FF can be switched.

In FIG. 2, for example, a flip-flop
FF01 is the last stage of BLOCK1 in FIG. 1, and the data from FF01 is B
In the case of wiring between blocks input to LOCK2, FF02 with polarity selection of clock 2 is arranged at the first stage of BLOCK2, and FF01
Is input to FF02.

In this case, the polarity selection of the clock 1 supplied from the clock tree 1 and the clock 2 supplied from the clock tree 2 depend on which absolute delay is shorter. Is determined, the polarity that operates correctly is determined. This allows
Timing adjustment before layout can be simplified.

The absolute delay between clock 1 and clock 2 (Tdela
y1, Tdelay2) is close to half a cycle, and Tdelay1> T
In the case of delay2, clock 2 only needs to be received at the rising edge (see FIG. 3A). Similarly, Tdelay1 <Tdelay2
In this case, the clock 2 only needs to be received at the falling edge (see FIG. 3B). When the difference between Tdelay1 and Tdelay2 is small and Tdelay1> Tdelay2 or Tdelay1 <Tdelay2 is not clear, the clock 2 may be received at the falling edge (see FIG. 3C).

In addition, the clock phase to be received can be selected even when inputting from the outside, and optimization can be performed. For example, after an external signal and an internal signal are selected by a selector and passed through a clock phase adjusting circuit, phase adjustment suitable for either of them can be performed.

The same applies to the case where the phase is changed by the output as shown in FIG.

In FIG. 4, for example, FF03 is the BLOC of FIG.
In the last stage of K1, in the case of inter-block wiring in which data from FF03 is input to BLOCK2, the output from FF03 is clock 1
FF04 driven by the inversion clock of 配置 配置 デ ー タ 配置 配置 デ ー タ デ ー タ 、 極性 、 、 極性 極性 極性 極性 極性 極性 極性 極性 極性 極性 極性 極性 極性 極性 デ ー タ 極性 極性
It is input to FF05 of the first stage of 2. Here, BLOCK2
FF05 is the rising drive of clock 2.

The absolute delay of clock 1 and clock 2 (Tdel
ay1, Tdelay2) is close to half a cycle, and Tdela
If y1> Tdelay2, BROCK1 should be output at the rising edge of clock 1. Similarly, if Tdelay1 <Tdelay2, BROCK1 only needs to be output at the falling edge of clock 1. Also, the difference between Tdelay1 and Tdelay2 is small, and Td
If elay1> Tdelay2 or Tdelay1 <Tdelay2 is not clear, it is sufficient to output at the falling edge of BLOCK1 clock 1. In addition, when outputting to the outside, the clock phase can be selected and optimization is possible.

FIG. 5 shows a system block in which the clock phase can be adjusted by a parameter instruction from the microcomputer. In FIG. 5, the phase adjustment circuit 5 is written separately from BLOCK1 or BLOCK2, but in practice, as shown in FIG. 2 or FIG.
It is configured to be absorbed by OCK1 or BLOCK2.

The microcomputer 1 inputs a parameter control signal including an 8-bit address data bus, a parameter clock, an address / data mode control, a read / write control, a chip selector and the like to the microcomputer interface 2. The microcomputer interface 2 extracts an address and data from an address data bus according to each control signal. The address decoder 3 is a microcomputer interface 2
The data obtained by the microcomputer interface 2 is held by the data latch circuit 4 only when the address obtained in step (1) is decoded, and only when the address matches a prescribed address.

The data is supplied to the phase adjustment circuit 5 as a polarity signal, and the phase can be switched.

When performing power management,
FIG. 6 (showing a clock tree configuration diagram incorporating power management) is combined with FIG. 2 or FIG. 4 is used for the phase adjustment circuit 5 in that case.

Although FIGS. 2 and 4 illustrate the phase adjustment circuit when performing clock transfer of data between blocks in the ASIC, the present invention is not limited to this.
Needless to say, it can be used for an interface with an external digital IC. For example, in the case of FIG. 2, the FF operating at clock 1 corresponds to an external digital IC, and in the case of FIG.
Corresponds to an external digital IC.

[0043]

According to the present invention, it is possible to improve the result of clock tree synthesis by reducing the number of clock tree stages, to reduce the absolute delay time and to suppress the occurrence of skew.

Although the clock tree is divided, the clock polarity of the input or output FF can be controlled by connecting the blocks, so that the optimum state can be set.

Furthermore, since it can be set by adjusting parameters from a microcomputer or the like, and the polarity can be set according to the result of wiring delay after layout, the development time until the completion of timing simulation can be greatly reduced, and the cost can be reduced. The benefits are huge.

[Brief description of the drawings]

FIG. 1 is a configuration diagram in a case where a clock tree is generated for each block separately for each functional block.

FIG. 2 is a phase adjustment circuit diagram in which the clock polarity of an input-side FF can be switched.

FIG. 3 is a time chart for explaining the operation of FIG. 2;

FIG. 4 is a phase adjustment circuit diagram in which the clock polarity of an output FF can be switched.

FIG. 5 is a system configuration diagram in which a clock polarity can be switched by parameter adjustment by a microcomputer.

FIG. 6 is a clock tree configuration diagram incorporating power management.

FIG. 7 is a configuration diagram showing a conventional one-clock tree structure.

[Explanation of symbols]

 01 ～ 05 Flip-flop 1 Microcomputer 2 Microcomputer interface 3 Address decoder 4 Data latch circuit 5 Phase adjustment circuit

Claims (5)

[Claims] 1. An ASIC clock phase adjustment system which operates with a clock having a common cycle and is composed of a plurality of functional blocks on a layout, wherein a clock tree is divided into a plurality by the number of functional blocks or less. A clock phase adjustment system comprising: 2. The clock phase according to claim 1, wherein a phase adjustment unit including a clock polarity switch is provided on the input side in a signal connection portion between the plurality of divided blocks. Adjustment system. 3. The clock phase according to claim 1, wherein a phase adjusting unit including a clock polarity switch is provided on the output side in a signal connection portion between the plurality of divided blocks. Adjustment system. 4. The clock phase adjusting system according to claim 2, wherein the polarity switching is supplied from a microcomputer. 5. An ASIC (I / O) that operates with a clock having a common cycle and includes a plurality of functional blocks on a layout.
C, LSI, and VLSI), wherein the clock tree is divided into a plurality of blocks with the number of functional blocks or less, and the number of stages of the clock tree is reduced. .