JP2001307939A - Laminated ceramic capacitor and its manufacturing method - Google Patents

Laminated ceramic capacitor and its manufacturing method

Info

Publication number
JP2001307939A
JP2001307939A JP2000125289A JP2000125289A JP2001307939A JP 2001307939 A JP2001307939 A JP 2001307939A JP 2000125289 A JP2000125289 A JP 2000125289A JP 2000125289 A JP2000125289 A JP 2000125289A JP 2001307939 A JP2001307939 A JP 2001307939A
Authority
JP
Japan
Prior art keywords
grain boundary
ceramic capacitor
multilayer ceramic
ceramic
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000125289A
Other languages
Japanese (ja)
Inventor
Koichi Chazono
広一 茶園
Hisamitsu Shizuno
寿光 静野
Hiroshi Kishi
弘志 岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2000125289A priority Critical patent/JP2001307939A/en
Priority to TW090105118A priority patent/TW508600B/en
Priority to KR1020010015083A priority patent/KR100568398B1/en
Priority to CN011120762A priority patent/CN1216388C/en
Priority to US09/823,157 priority patent/US6673461B2/en
Priority to MYPI20011528A priority patent/MY130797A/en
Publication of JP2001307939A publication Critical patent/JP2001307939A/en
Priority to US10/702,931 priority patent/US7020941B2/en
Withdrawn legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem in which an electric field is increased in intensity per layer when dielectric layers are each lessened in thickness and increased in number of layers so as to enable a laminated ceramic capacitor to be enhanced in capacitance and lessened in size at the same time, and therefore a dielectric breakdown is liable to occur between inner electrodes, so that the laminated ceramic capacitor is shortened in service life and deteriorated in reliability of electrical properties. SOLUTION: Dielectric layers and inner electrode layers are laminated into a laminated ceramic capacitor of integral structure, where the dielectric layer is formed of dielectric porcelain composition composed of ceramic particles and glassy grain boundaries linking and covering the ceramic particles. The grain boundaries contain one or more elements selected out of Mn, V, Cr, Mo, Cu, Ni, Fe and Co. At this point, it is preferable that the grain boundaries are formed of glass. It is preferable that the inner electrode layers come into contact with the ceramic particles through the intermediary of the grain boundary.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、寿命特性を向上
させ、薄層化・多層化による更なる小型大容量化を可能
にした積層セラミックコンデンサとその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor having improved life characteristics and capable of achieving further miniaturization and large capacity by thinning and multilayering, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】図3は積層セラミックコンデンサの説明
図である。同図に示すように、積層セラミックコンデン
サはチップ状の素体10と、素体10の両端部に形成さ
れた一対の外部電極12,12とからなる。素体10は
一般に誘電体層14と内部電極16とが交互に多数層積
層された積層体からなる。内部電極16のうち、隣り合
う内部電極16,16は誘電体層14を介して対向し、
別々の外部電極12,12と電気的に接続されている。
2. Description of the Related Art FIG. 3 is an explanatory view of a multilayer ceramic capacitor. As shown in FIG. 1, the multilayer ceramic capacitor includes a chip-shaped element body 10 and a pair of external electrodes 12 formed on both ends of the element body 10. The element body 10 is generally formed of a laminate in which a large number of dielectric layers 14 and internal electrodes 16 are alternately laminated. Among the internal electrodes 16, the adjacent internal electrodes 16 and 16 face each other via the dielectric layer 14,
It is electrically connected to separate external electrodes 12 and 12.

【0003】ここで、誘電体層14の材料としては、例
えばチタン酸バリウムを主成分とし、これに希土類元素
の酸化物を添加した、耐還元性誘電体磁器組成物が使用
されている。この誘電体磁器組成物は、図4に示すよう
に、セラミック粒子18と粒界部20とからなる。ま
た、内部電極16の材料としては、例えばNi金属粉末
を主成分とする導電性ペーストを焼結させたものが使用
されている。
Here, as a material for the dielectric layer 14, for example, a reduction-resistant dielectric ceramic composition containing barium titanate as a main component and an oxide of a rare earth element added thereto is used. This dielectric ceramic composition is composed of ceramic particles 18 and grain boundaries 20, as shown in FIG. Further, as a material of the internal electrode 16, for example, a material obtained by sintering a conductive paste containing Ni metal powder as a main component is used.

【0004】素体10は、セラミックグリーンシートと
内部電極パターンとを交互に一体的に積層させたチップ
状の積層体を脱バインダした後、非酸化性雰囲気中にお
いて1200〜1300℃程度の高温で焼成し、その
後、酸化性雰囲気中で再酸化させることにより製造され
ている。
[0004] The element body 10 is obtained by removing a chip-like laminate in which ceramic green sheets and internal electrode patterns are alternately and integrally laminated, and then subjecting the chip body to a high temperature of about 1200 to 1300 ° C in a non-oxidizing atmosphere. It is manufactured by firing and then reoxidizing in an oxidizing atmosphere.

【0005】[0005]

【発明が解決しようとする課題】ところで、近年におけ
る電子回路の小型化、高密度化の流れに伴い、積層セラ
ミックコンデンサについても小型大容量化が求められ、
小型大容量化のために誘電体層の積層数の更なる増加
と、1層当たりの誘電体層の更なる薄層化が進んでい
る。
With the recent trend of miniaturization and high density of electronic circuits, multilayer ceramic capacitors are also required to have a small size and a large capacity.
To increase the size and the capacity, the number of stacked dielectric layers is further increased, and the thickness of each dielectric layer is further reduced.

【0006】しかし、誘電体層を薄層化させると、1層
当たりの電界強度が大きくなり、積層セラミックコンデ
ンサの寿命が短くなり、所望の寿命の積層セラミックコ
ンデンサが得られなくなるという問題があった。
However, when the thickness of the dielectric layer is reduced, the electric field strength per one layer increases, and the life of the multilayer ceramic capacitor is shortened, so that a multilayer ceramic capacitor having a desired life cannot be obtained. .

【0007】この発明は、誘電体層を多層化・薄層化し
ても所望の寿命を有し、小型大容量化が可能な積層セラ
ミックコンデンサとその製造方法を提供することを目的
とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer ceramic capacitor which has a desired life even when the dielectric layers are multilayered and thinned, and which can be reduced in size and capacity, and a method of manufacturing the same.

【0008】[0008]

【課題を解決するための手段】この発明に係る積層セラ
ミックコンデンサは、複数の誘電体層と複数の内部電極
とを一体的に積層してなり、該誘電体層は誘電体磁器組
成物からなり、該誘電体磁器組成物はセラミック粒子と
該セラミック粒子を連結・被覆するガラス質の粒界部
(隣り合うセラミック粒子間の部分)とからなり、該粒
界部はMn,V,Cr,Mo,Cu,Ni,Fe及びC
oから選択された1種又は2種以上の元素を含んでいる
ものである。
A multilayer ceramic capacitor according to the present invention is formed by integrally laminating a plurality of dielectric layers and a plurality of internal electrodes, and the dielectric layers are made of a dielectric ceramic composition. The dielectric porcelain composition comprises ceramic particles and a vitreous grain boundary portion (a portion between adjacent ceramic particles) connecting and covering the ceramic particles, and the grain boundary portion is Mn, V, Cr, Mo. , Cu, Ni, Fe and C
It contains one or more elements selected from o.

【0009】ここで、前記内部電極は前記粒界部を介し
て前記セラミック粒子と接していてもよい。また、前記
粒界部はMn,V,Cr,Mo,Cu,Ni,Fe及び
Coから選択された1種又は2種以上の元素を含むガラ
スであってもよい。
Here, the internal electrode may be in contact with the ceramic particles via the grain boundary portion. Further, the grain boundary portion may be a glass containing one or more elements selected from Mn, V, Cr, Mo, Cu, Ni, Fe and Co.

【0010】また、前記粒界部は前記誘電体磁器組成物
の0.2〜3wt%を占めているのが好ましい。前記粒
界部が前記誘電体磁器組成物の0.2wt%未満では所
望の寿命が得られず、3wt%を超えると誘電体層の誘
電率が低下し過ぎてしまうからである。
It is preferable that the grain boundary part occupies 0.2 to 3 wt% of the dielectric ceramic composition. If the grain boundary portion is less than 0.2 wt% of the dielectric ceramic composition, a desired life cannot be obtained, and if it exceeds 3 wt%, the dielectric constant of the dielectric layer is excessively lowered.

【0011】また、Mn,V,Cr,Mo,Cu,N
i,Fe及びCoから選択された1種又は2種以上の元
素の化合物は前記粒界部中に0.05〜20wt%の割
合で含まれているのが好ましい。これらの元素の化合物
が0.05wt%未満では所望の寿命が得られず、20
wt%を超えると誘電体層の誘電率が低下し過ぎてしま
うからである。
Further, Mn, V, Cr, Mo, Cu, N
It is preferable that a compound of one or more elements selected from i, Fe and Co is contained in the grain boundary at a ratio of 0.05 to 20 wt%. If the compound of these elements is less than 0.05 wt%, the desired life cannot be obtained,
This is because if it exceeds wt%, the dielectric constant of the dielectric layer will be too low.

【0012】また、前記粒界部中には結晶質の二次相が
含まれていてもよい。結晶質の二次相が含まれている
と、誘電体層の誘電率の低下が少なくなる。また、前記
粒界部は耐還元性を有する組成物からなるのが好まし
い。
The grain boundary may include a crystalline secondary phase. When a crystalline secondary phase is contained, the decrease in the dielectric constant of the dielectric layer is reduced. Further, the grain boundary part is preferably made of a composition having reduction resistance.

【0013】また、この発明に係る積層セラミックコン
デンサの製造方法は、セラミック原料を準備する原料工
程と、該セラミック原料を用いてセラミックグリーンシ
ートを形成するシート形成工程と、該セラミックグリー
ンシートに導電ペーストで内部電極パターンを印刷する
印刷工程と、該印刷工程を経たセラミックグリーンシー
トを積層して積層体を形成する積層工程と、該積層体を
内部電極パターン毎に裁断してチップ状の積層体を得る
裁断工程と、該裁断工程で得られたチップ状の積層体を
焼成する焼成工程とを備え、前記セラミック原料が粒界
形成成分を含んでおり、該粒界形成成分はMn,V,C
r,Mo,Cu,Ni,Fe及びCoから選択された1
種又は2種以上の元素の化合物を含んでいるものであ
る。
[0013] Further, a method of manufacturing a multilayer ceramic capacitor according to the present invention includes a raw material step of preparing a ceramic raw material, a sheet forming step of forming a ceramic green sheet using the ceramic raw material, and a conductive paste on the ceramic green sheet. A printing step of printing an internal electrode pattern at, a laminating step of laminating the ceramic green sheets after the printing step to form a laminated body, and cutting the laminated body for each internal electrode pattern to form a chip-shaped laminated body. And a firing step of firing the chip-like laminate obtained in the cutting step, wherein the ceramic raw material contains a grain boundary forming component, and the grain boundary forming component is Mn, V, C
1 selected from r, Mo, Cu, Ni, Fe and Co
It contains a species or a compound of two or more elements.

【0014】ここで、粒界形成成分とは、焼成したとき
に溶融してガラス質の溶融体を形成する化合物からなる
混合物をいい、例えばLiO−SiO−MO(Mは
Ba,Ca,Sr,Mg,Zn)やB−SiO
−MOで示されるものを挙げることができるが、これら
に限定されるものではなく、これら以外のガラス形成成
分であってもよい。。
The term "grain boundary forming component" as used herein refers to a mixture of compounds which melt when fired to form a vitreous melt. For example, Li 2 O--SiO 2 --MO (M is Ba, Ca , Sr, Mg, Zn) and B 2 O 3 —SiO 2
Although what is shown by -MO can be mentioned, it is not limited to these and glass-forming components other than these may be sufficient. .

【0015】また、前記粒界形成成分は前記セラミック
原料の0.2〜3wt%を占めているのが好ましい。前
記粒界形成成分が0.2wt%未満では所望の寿命の積
層セラミックコンデンサが得られず、3wt%を超える
と積層セラミックコンデンサの誘電体層の誘電率が低下
し過ぎてしまうからである。
Preferably, the grain boundary forming component accounts for 0.2 to 3% by weight of the ceramic raw material. If the content of the grain boundary forming component is less than 0.2 wt%, a multilayer ceramic capacitor having a desired life cannot be obtained, and if it exceeds 3 wt%, the dielectric constant of the dielectric layer of the multilayer ceramic capacitor is excessively lowered.

【0016】また、Mn,V,Cr,Mo,Cu,N
i,Fe及びCoから選択された1種又は2種以上の元
素の化合物が前記粒界形成成分中に0.05〜20wt
%の割合で含まれているのが好ましい。これらの元素の
化合物が0.05wt%未満では所望の寿命の積層セラ
ミックコンデンサが得られず、20wt%を超えると積
層セラミックコンデンサの誘電体層の誘電率が低下し過
ぎてしまうからである。
Also, Mn, V, Cr, Mo, Cu, N
i, a compound of one or more elements selected from Fe and Co is contained in the grain boundary forming component in an amount of 0.05 to 20 wt.
% Is preferred. If the compound of these elements is less than 0.05 wt%, a laminated ceramic capacitor having a desired life cannot be obtained, and if it exceeds 20 wt%, the dielectric constant of the dielectric layer of the laminated ceramic capacitor is excessively lowered.

【0017】また、前記導電ペーストが前記粒界形成成
分を含んでいてもよい。この場合、前記導電ペーストは
1〜20vol%の前記粒界形成成分を含んでいるのが
好ましい。1vol%未満では積層セラミックコンデン
サの寿命延長の効果が認められず、20vol%を超え
ると積層セラミックコンデンサの内部電極の電気抵抗が
大きくなり過ぎるからである。
Further, the conductive paste may include the grain boundary forming component. In this case, the conductive paste preferably contains 1 to 20 vol% of the component for forming the grain boundary. If the content is less than 1 vol%, the effect of extending the life of the multilayer ceramic capacitor is not recognized, and if it exceeds 20 vol%, the electrical resistance of the internal electrodes of the multilayer ceramic capacitor becomes too large.

【0018】[0018]

【実施例】まず、BaCOを0.96モル部、MgO
を0.05モル部、SrOを0.01モル部、TiO
を0.99モル部及びYbを0.005モル部、
各々秤量し、これらの化合物をポットミルに、アルミナ
ボール及び水2.5リットルとともに入れ、15時間撹
拌混合して、原料混合物を得た。
EXAMPLE First, 0.96 mol part of BaCO 3 and MgO were used.
0.05 mol part, SrO 0.01 mol part, TiO 2
0.99 mol part and Yb 2 O 3 0.005 mol part,
Each was weighed, and these compounds were put into a pot mill together with alumina balls and 2.5 liters of water and stirred and mixed for 15 hours to obtain a raw material mixture.

【0019】次に、この原料混合物をステンレスポット
に入れ、熱風式乾燥器を用い、150℃で乾燥し、この
乾燥した原料混合物を粗粉砕し、この粗粉砕した原料混
合物をトンネル炉を用い、大気中において約1200℃
で2時間仮焼し、第1基本成分の粉末を得た。
Next, the raw material mixture is placed in a stainless steel pot, dried at 150 ° C. using a hot air drier, and the dried raw material mixture is coarsely pulverized. About 1200 ° C in air
For 2 hours to obtain a powder of the first basic component.

【0020】また、BaCO とZrO とが等モル
となるように、それぞれ秤量し、これ等を混合し、乾燥
し、粉砕した後、大気中において約1250℃で2時間
仮焼して、第2基本成分の粉末を得た。そして、98モ
ル部(976.28g)の第1基本成分の粉末と、2モ
ル部(23.85g)の第2基本成分の粉末とを混合し
て1000gの基本成分を得た。
Further, BaCO 3 and ZrO 2 were weighed so as to be equimolar, mixed, dried and pulverized, and calcined in the atmosphere at about 1250 ° C. for 2 hours. A powder of the second basic component was obtained. Then, 98 mol parts (976.28 g) of the powder of the first basic component and 2 mol parts (23.85 g) of the powder of the second basic component were mixed to obtain 1000 g of the basic component.

【0021】また、LiOを1モル部、SiOを8
0モル部、BaCOを3.8モル部、CaCO
9.5モル部及びMgOを4.7モル部、TiO
1.0モル部、各々秤量し、これら100重量部に対し
てMnOを8重量部、更に加え、これらを混合し、こ
の混合物にアルコールを300ミリリットル加え、ポリ
エチレンポット中において、アルミナボールを用いて1
0時間撹拌し、その後、大気中において1000℃で2
時間仮焼した。
Also, 1 mol part of Li 2 O and 8 mol of SiO 2
0 mol parts, 3.8 mol parts of BaCO 3 , 9.5 mol parts of CaCO 3 , 4.7 mol parts of MgO, and 1.0 mol part of TiO 2 were weighed, and with respect to 100 parts by weight, 8 parts by weight of MnO 2 was further added and mixed, and 300 ml of alcohol was added to this mixture, and 1 part of the mixture was placed in a polyethylene pot using alumina balls.
Stir for 0 hours, then in air at 1000 ° C for 2 hours.
It was calcined for hours.

【0022】次に、上記仮焼によって得られたものを3
00ミリリットルの水とともにアルミナポットに入れ、
アルミナボールで15時間粉砕し、その後、150℃で
4時間乾燥させて、第1添加成分の粉末を得た。
Next, what was obtained by the above calcination was
Put in an alumina pot with 00 ml of water,
The powder was pulverized with an alumina ball for 15 hours and then dried at 150 ° C. for 4 hours to obtain a powder of the first additive component.

【0023】次に、100重量部(1000g)の前記
基本成分に、2重量部(20g)の前記第1添加成分を
添加し、また、平均粒径が0.5μmで良く粒の揃った
純度99.0%以上のCrとAlとを第2
添加成分として各々0.1重量部(1g)添加し、アク
リル酸エステルポリマー、グリセリン、縮合リン酸塩の
水溶液からなる有機バインダーを、15重量%添加し、
更に、50重量%の水を加え、これらをボールミルに入
れて、粉砕及び混合して磁器原料のスラリーを調製し
た。
Next, 2 parts by weight (20 g) of the first additive component is added to 100 parts by weight (1000 g) of the basic component, and the average particle size is 0.5 μm and the purity is good. 99.0% or more of Cr 2 O 3 and Al 2 O 3
0.1 parts by weight (1 g) were added as additive components, and 15% by weight of an organic binder composed of an aqueous solution of an acrylate polymer, glycerin, and condensed phosphate was added.
Further, 50% by weight of water was added, and these were put into a ball mill, pulverized and mixed to prepare a slurry of a porcelain raw material.

【0024】次に、上記セラミックスラリーを真空脱泡
機に入れて脱泡し、このセラミックスラリーをリバース
ロールコータに入れ、ここから得られる薄膜成形物を長
尺なポリエステルフィルム上に連続して受け取らせると
共に、同フィルム上でこれを100℃に加熱して乾燥さ
せ、厚さ約5μmで10cm角の正方形のセラミックグ
リーンシートを得た。
Next, the ceramic slurry is placed in a vacuum defoaming machine to remove bubbles, and the ceramic slurry is placed in a reverse roll coater, and a thin film formed therefrom is continuously received on a long polyester film. At the same time, the film was heated to 100 ° C. and dried on the same film to obtain a square ceramic green sheet having a thickness of about 5 μm and a square of 10 cm.

【0025】一方、平均粒径1.5μmのニッケル粉末
10gと、エチルセルロース0.9gをブチルカルビト
ール9.1gに溶解させたものとを撹拌機に入れ、10
時間撹拌することにより内部電極用の導電性ペーストを
得た。そして、この導電性ペーストを用い、長さ14m
m、幅7mmのパターンを50個有するスクリーンを介
して上記セラミックグリーンシートの片側に内部電極パ
ターンを印刷し、これを乾燥させた。
On the other hand, 10 g of nickel powder having an average particle size of 1.5 μm and 0.9 g of ethyl cellulose dissolved in 9.1 g of butyl carbitol were placed in a stirrer and placed in a stirrer.
By stirring for a time, a conductive paste for an internal electrode was obtained. Then, using this conductive paste, a length of 14 m
An internal electrode pattern was printed on one side of the ceramic green sheet through a screen having 50 m and 7 mm wide patterns, and this was dried.

【0026】次に、内部電極パターンを印刷したセラミ
ックグリーンシートを内部電極パターンを上にした状態
で11枚積層した。この際、隣接する上下のセラミック
グリーンシートにおいて、その印刷面が内部電極パター
ンの長手方向に約半分程ずれるように配置した。更に、
この積層物の上下両面に内部電極パターンを印刷してな
い保護層用のセラミックグリーンシートを200μmの
厚さで積層した。
Next, eleven ceramic green sheets on which the internal electrode patterns were printed were laminated with the internal electrode patterns facing upward. At this time, the printed surfaces of the adjacent upper and lower ceramic green sheets were arranged so as to be shifted by about half in the longitudinal direction of the internal electrode pattern. Furthermore,
On the upper and lower surfaces of the laminate, ceramic green sheets for a protective layer on which no internal electrode pattern was printed were laminated with a thickness of 200 μm.

【0027】次に、この積層物を約50℃の温度で厚さ
方向に約40トンの荷重を加えて圧着させ、しかる後、
この積層物を内部電極パターン毎に格子状に裁断して、
3.2×1.6mmのチップ状の積層体を50個得た。
Next, the laminate is pressed at a temperature of about 50 ° C. by applying a load of about 40 tons in a thickness direction, and thereafter,
This laminate is cut into a lattice shape for each internal electrode pattern,
Fifty 3.2 × 1.6 mm chip-shaped laminates were obtained.

【0028】次に、このチップ状の積層体を雰囲気焼成
が可能な炉に入れ、大気雰囲気中において100℃/h
の速度で600℃まで昇温させ、有機バインダを燃焼除
去させた。
Next, this chip-shaped laminate is placed in a furnace capable of firing in an atmosphere, and is heated at 100 ° C./h in an air atmosphere.
The temperature was raised to 600 ° C. at a rate of to burn off the organic binder.

【0029】その後、炉の雰囲気を大気雰囲気からH2
(2体積%)+N2 (98体積%)の還元性雰囲気に
変えた。そして、炉をこの還元性雰囲気とした状態を保
って、積層体チップの加熱温度を600℃から焼結温度
の1130℃まで、100℃/hの速度で昇温して11
30℃(最高温度)を3時間保持した。
After that, the atmosphere of the furnace was changed from the air atmosphere to H2.
The atmosphere was changed to a reducing atmosphere of (2% by volume) + N2 (98% by volume). Then, while keeping the furnace in the reducing atmosphere, the heating temperature of the laminated chip was raised from 600 ° C. to the sintering temperature of 1130 ° C. at a rate of 100 ° C./h, and 11
30 ° C. (maximum temperature) was maintained for 3 hours.

【0030】そして、100℃/hの速度で600℃ま
で降温し、雰囲気を大気雰囲気(酸化性雰囲気)におき
かえて、600℃を30分間保持して酸化処理を行い、
その後、室温まで冷却して積層セラミックコンデンサの
素体を得た。
Then, the temperature was lowered to 600 ° C. at a rate of 100 ° C./h, the atmosphere was changed to the air atmosphere (oxidizing atmosphere), and the oxidation treatment was carried out at 600 ° C. for 30 minutes.
Thereafter, the resultant was cooled to room temperature to obtain a body of a multilayer ceramic capacitor.

【0031】次に、内部電極の端部が露出する素体の側
面に亜鉛とガラスフリット(glassfrit)とビヒクル(v
ehicle)とからなる導電性ペーストを塗布して乾燥し、
これを大気中で550℃の温度で15分間焼付け、亜鉛
電極層を形成し、更にこの上に無電解メッキ法で銅層を
形成し、更にこの上に電気メッキ法でPb−Sn半田層
を設けて、一対の外部電極を形成した。
Next, zinc, glass frit and vehicle (v) are applied to the side surfaces of the element where the ends of the internal electrodes are exposed.
ehicle) and dried.
This is baked in the air at a temperature of 550 ° C. for 15 minutes to form a zinc electrode layer, a copper layer is further formed thereon by an electroless plating method, and a Pb—Sn solder layer is further formed thereon by an electroplating method. To form a pair of external electrodes.

【0032】そして、この積層セラミックコンデンサの
誘電体層の断面を顕微鏡で観察したところ、図1にモデ
ルで極端に示すように、セラミック粒子18がガラス質
の粒界部20に被覆されていた。そして、粒界部20の
成分をTEM(透過型電子顕微鏡)による点分析で分析
したところ、Mnを0.05〜5wt%の範囲で含んで
いることがわかった。
When the cross section of the dielectric layer of the multilayer ceramic capacitor was observed with a microscope, it was found that the ceramic particles 18 were coated on the vitreous grain boundary 20 as shown extremely in the model in FIG. Then, when the components of the grain boundary portion 20 were analyzed by point analysis using a TEM (transmission electron microscope), it was found that Mn was contained in the range of 0.05 to 5 wt%.

【0033】また、このようにして作成した積層セラミ
ックコンデンサの寿命(Life)と、誘電体層の誘電率(ε)
を調べたところ、表1に示す通りであった。
The life of the multilayer ceramic capacitor thus produced and the dielectric constant (ε) of the dielectric layer
Was as shown in Table 1.

【0034】ここで、寿命(Life)は、170℃の恒温槽
内で、積層セラミックコンデンサに70Vの電圧を負荷
し、ブレークダウンした時間を測定して求めた。なお、
表1中の寿命の数値は試料No.1の値を1とした場合
の倍率で表わしている。
Here, the life was determined by applying a voltage of 70 V to the multilayer ceramic capacitor in a constant temperature bath at 170 ° C. and measuring the breakdown time. In addition,
The values of the life in Table 1 are shown in Sample No. It is represented by the magnification when the value of 1 is set to 1.

【0035】また、誘電率(ε)は、温度20℃、周波
数1kHz、電圧1.0Vの条件で積層セラミックコン
デンサの静電容量を測定し、この測定値と、一対の内部
電極の対向面積と誘電体層の厚みから計算で求めた。
The dielectric constant (ε) is obtained by measuring the capacitance of a multilayer ceramic capacitor under the conditions of a temperature of 20 ° C., a frequency of 1 kHz and a voltage of 1.0 V. It was calculated from the thickness of the dielectric layer.

【0036】[0036]

【表1】 [Table 1]

【0037】以上の結果から、粒界形成成分を0.2w
t%以上添加したものは積層セラミックコンデンサの寿
命(Life)のアップが認められた。但し、粒界形成成分が
3wt%を超えると、誘電体層の誘電率が低下し過ぎて
しまうこともわかった。粒界形成成分をB−Si
−MO−TiOとしても同様の結果が得られた。
MOのM成分としてSrやZnを使用した場合も同様の
結果が得られた。
From the above results, the grain boundary forming component was 0.2 w
With the addition of t% or more, an increase in the life of the multilayer ceramic capacitor was observed. However, it has also been found that when the grain boundary forming component exceeds 3 wt%, the dielectric constant of the dielectric layer is excessively reduced. The grain boundary forming component is B 2 O 3 —Si
O 2 -MO-TiO 2 Similar results as were obtained.
Similar results were obtained when Sr or Zn was used as the M component of MO.

【0038】また、添加元素を0.05wt%以上添加
したものは積層セラミックコンデンサの寿命(Life)のア
ップが認められた。但し、添加元素が5wt%を超える
と、誘電体層の誘電率が低下し過ぎてしまうこともわか
った。添加元素をV,Cr,Mo,Co,Cu,Ni,
Feとしても同様の結果が得られた。
Further, when the additive element was added in an amount of 0.05 wt% or more, the life of the multilayer ceramic capacitor was increased. However, it has also been found that when the additive element exceeds 5 wt%, the dielectric constant of the dielectric layer is excessively reduced. The additional elements are V, Cr, Mo, Co, Cu, Ni,
Similar results were obtained for Fe.

【0039】また、内部電極形成用の導電ペースト中に
上記粒界形成成分を1〜20vol%の範囲で添加した
場合も、寿命の向上が見られた。
Also, when the above-mentioned grain boundary forming component was added to the conductive paste for forming the internal electrode in the range of 1 to 20 vol%, the life was improved.

【0040】なお、上記寿命のアップは次のような理由
によるものと思われる。すなわち、図2に示すように、
セラミック粒子18中の酸素欠陥(V)は、内部電極
16,16間にDCが印加されると、(V)→(V
++)+2eとなり、プラスにチャージし、陰極側に
移動してたまる。そして、陰極側に一定量以上の(V
++)がたまるともはや結晶構造の維持ができなくな
り、結晶が破壊され、寿命が尽き、絶縁破壊となる。
The above-mentioned increase in life is due to the following reasons.
It seems to be due to. That is, as shown in FIG.
Oxygen vacancies (Vo) Is the internal electrode
When DC is applied between 16 and 16, (Vo) → (Vo
++) + 2eAnd charge positively, and on the cathode side
Move and accumulate. Then, a certain amount or more (V o
++) Can no longer maintain the crystal structure
As a result, the crystal is destroyed, the life is exhausted, and dielectric breakdown occurs.

【0041】しかし、図2に示すように、セラミック粒
子18が粒界部20によって被覆されていると、この
(V ++)の移動がまず粒界部分で阻止され、陰極側
にたまらない。内部電極16とセラミック粒子18との
間でも同様の現象が生じていると考えられる。このた
め、酸素欠陥の局部的な集中につながらず、破壊が防止
され、寿命がアップすると考えられる。
However, as shown in FIG. 2, when the ceramic particles 18 are covered with the grain boundary portions 20, the movement of (V o ++ ) is first blocked at the grain boundary portions, and the (V o ++ ) is not accumulated on the cathode side. It is considered that a similar phenomenon occurs between the internal electrode 16 and the ceramic particles 18. For this reason, it is considered that the destruction is prevented without leading to local concentration of oxygen vacancies, and the life is extended.

【0042】[0042]

【発明の効果】この発明は、誘電体層を形成している誘
電体磁器組成物中のセラミック粒子をガラス質の粒界部
で被覆したので、セラミック粒子中の酸素欠陥(V
の移動が阻止され、積層セラミックコンデンサの寿命特
性、特に誘電体層を薄層化させた時の寿命特性が向上
し、薄層化・多層化が可能になり、積層セラミックコン
デンサの小型大容量化が可能になるという効果がある。
According to the present invention, since the ceramic particles in the dielectric ceramic composition forming the dielectric layer are covered with the vitreous grain boundaries, oxygen defects (V o ) in the ceramic particles are obtained.
Of the multilayer ceramic capacitor, especially when the dielectric layer is made thinner, improves the life characteristics of the multilayer ceramic capacitor. There is an effect that it becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明に係る積層セラミックコンデンサの誘
電体層を形成している磁器組成物の微細構造の説明図で
ある。
FIG. 1 is an explanatory diagram of a fine structure of a porcelain composition forming a dielectric layer of a multilayer ceramic capacitor according to the present invention.

【図2】図1のA部拡大図である。FIG. 2 is an enlarged view of a portion A in FIG.

【図3】積層セラミックコンデンサの説明図である。FIG. 3 is an explanatory diagram of a multilayer ceramic capacitor.

【図4】従来の積層セラミックコンデンサの誘電体層を
形成している磁器組成物の微細構造の説明図である。
FIG. 4 is an explanatory diagram of a fine structure of a porcelain composition forming a dielectric layer of a conventional multilayer ceramic capacitor.

【符号の説明】[Explanation of symbols]

10 素体 12 外部電極 14 誘電体層 16 内部電極 18 セラミック粒子 20 粒界部 DESCRIPTION OF SYMBOLS 10 Element body 12 External electrode 14 Dielectric layer 16 Internal electrode 18 Ceramic particle 20 Grain boundary part

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01G 4/30 311 H01G 4/30 311D (72)発明者 岸 弘志 東京都台東区上野6丁目16番20号 太陽誘 電株式会社内 Fターム(参考) 5E001 AB03 AC09 AD00 AE05 AH01 AH06 AH09 AJ01 AJ02 5E082 AA01 AB03 BC39 EE04 EE22 EE35 FG06 FG25 FG26 FG54 LL01 LL02 LL03 MM24 PP03──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme court ゛ (Reference) H01G 4/30 311 H01G 4/30 311D (72) Inventor Hiroshi Kishi 6-16-20 Ueno, Taito-ku, Tokyo No. Taiyo Denki Co., Ltd. F-term (reference) 5E001 AB03 AC09 AD00 AE05 AH01 AH06 AH09 AJ01 AJ02 5E082 AA01 AB03 BC39 EE04 EE22 EE35 FG06 FG25 FG26 FG54 LL01 LL02 LL03 MM24 PP03

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 複数の誘電体層と複数の内部電極とを一
体的に積層してなり、該誘電体層は誘電体磁器組成物か
らなり、該誘電体磁器組成物はセラミック粒子と該セラ
ミック粒子を連結・被覆するガラス質の粒界部とからな
り、該粒界部はMn,V,Cr,Mo,Cu,Ni,F
e及びCoから選択された1種又は2種以上の元素を含
んでいることを特徴とする積層セラミックコンデンサ。
1. A plurality of dielectric layers and a plurality of internal electrodes are integrally laminated, wherein the dielectric layers are composed of a dielectric ceramic composition, and the dielectric ceramic composition comprises ceramic particles and the ceramic. And a vitreous grain boundary that connects and covers the particles, and the grain boundary is Mn, V, Cr, Mo, Cu, Ni, F
A multilayer ceramic capacitor comprising one or more elements selected from e and Co.
【請求項2】 前記内部電極が前記粒界部を介して前記
セラミック粒子と接していることを特徴とする請求項1
に記載の積層セラミックコンデンサ。
2. The method according to claim 1, wherein the internal electrode is in contact with the ceramic particles via the grain boundary.
3. The multilayer ceramic capacitor according to item 1.
【請求項3】 前記粒界部がMn,V,Cr,Mo,C
u,Ni,Fe及びCoから選択された1種又は2種以
上の元素を含むガラスからなることを特徴とする請求項
1又は2に記載の積層セラミックコンデンサ。
3. The method according to claim 1, wherein the grain boundary part is Mn, V, Cr, Mo, C.
3. The multilayer ceramic capacitor according to claim 1, comprising a glass containing one or more elements selected from u, Ni, Fe and Co. 4.
【請求項4】 前記粒界部が前記誘電体磁器組成物の
0.2〜3wt%を占めていることを特徴とする請求項
1〜3のいずれかに記載の積層セラミックコンデンサ。
4. The multilayer ceramic capacitor according to claim 1, wherein said grain boundary portion occupies 0.2 to 3% by weight of said dielectric ceramic composition.
【請求項5】 前記粒界部中にMn,V,Cr,Mo,
Cu,Ni,Fe及びCoから選択された1種又は2種
以上の元素の化合物が0.05〜20wt%の割合で含
まれていることを特徴とする請求項1〜4のいずれかに
記載の積層セラミックコンデンサ。
5. The method according to claim 1, wherein Mn, V, Cr, Mo,
The compound of one or more elements selected from Cu, Ni, Fe and Co is contained at a ratio of 0.05 to 20% by weight. Multilayer ceramic capacitors.
【請求項6】 前記粒界部中に結晶質の二次相が含まれ
ていることを特徴とする請求項1〜5のいずれかに記載
の積層セラミックコンデンサ。
6. The multilayer ceramic capacitor according to claim 1, wherein a crystalline secondary phase is contained in the grain boundary part.
【請求項7】 前記粒界部が耐還元性を有する組成物か
らなることを特徴とする請求項1〜6のいずれかに記載
の積層セラミックコンデンサ。
7. The multilayer ceramic capacitor according to claim 1, wherein the grain boundary part is made of a composition having reduction resistance.
【請求項8】 セラミック原料を準備する原料工程と、
該セラミック原料を用いてセラミックグリーンシートを
形成するシート形成工程と、該セラミックグリーンシー
トに導電ペーストで内部電極パターンを印刷する印刷工
程と、該印刷工程を経たセラミックグリーンシートを積
層して積層体を形成する積層工程と、該積層体を内部電
極パターン毎に裁断してチップ状の積層体を得る裁断工
程と、該裁断工程で得られたチップ状の積層体を焼成す
る焼成工程とを備え、前記セラミック原料が粒界形成成
分を含んでおり、該粒界形成成分はMn,V,Cr,M
o,Cu,Ni,Fe及びCoから選択された1種又は
2種以上の元素の化合物を含んでいることを特徴とする
積層セラミックコンデンサの製造方法。
8. A raw material step for preparing a ceramic raw material,
A sheet forming step of forming a ceramic green sheet using the ceramic raw material, a printing step of printing an internal electrode pattern on the ceramic green sheet with a conductive paste, and laminating the ceramic green sheets after the printing step to form a laminate A laminating step of forming, a cutting step of cutting the laminated body for each internal electrode pattern to obtain a chip-shaped laminated body, and a firing step of firing the chip-shaped laminated body obtained in the cutting step, The ceramic raw material contains a grain boundary forming component, and the grain boundary forming component is Mn, V, Cr, M
A method for manufacturing a multilayer ceramic capacitor, comprising a compound of one or more elements selected from o, Cu, Ni, Fe and Co.
【請求項9】 前記粒界形成成分がMn,V,Cr,M
o,Cu,Ni,Fe及びCoから選択された1種又は
2種以上の元素を含むガラス形成成分からなることを特
徴とする請求項8に記載の積層セラミックコンデンサの
製造方法。
9. The method according to claim 8, wherein the grain boundary forming component is Mn, V, Cr, M.
The method for manufacturing a multilayer ceramic capacitor according to claim 8, comprising a glass-forming component containing one or more elements selected from o, Cu, Ni, Fe, and Co.
【請求項10】 前記粒界形成成分が前記セラミック原
料の0.2〜3wt%を占めていることを特徴とする請
求項8又は9に記載の積層セラミックコンデンサの製造
方法。
10. The method for manufacturing a multilayer ceramic capacitor according to claim 8, wherein the grain boundary forming component accounts for 0.2 to 3 wt% of the ceramic raw material.
【請求項11】 前記粒界形成成分中にMn,V,C
r,Mo,Cu,Ni,Fe及びCoから選択された1
種又は2種以上の元素の化合物が0.05〜20wt%
の割合で含まれていることを特徴とする請求項8〜10
のいずれかに記載の積層セラミックコンデンサの製造方
法。
11. Mn, V, C in the grain boundary forming component
1 selected from r, Mo, Cu, Ni, Fe and Co
0.05 to 20 wt% of a compound of a species or two or more elements
11. The composition according to claim 8, wherein
The method for manufacturing a multilayer ceramic capacitor according to any one of the above.
【請求項12】 前記導電ペーストが前記粒界形成成分
を含んでいることを特徴とする請求項8に記載の積層セ
ラミックコンデンサの製造方法。
12. The method according to claim 8, wherein the conductive paste contains the grain boundary forming component.
【請求項13】 前記導電ペーストが1〜20vol%
の前記粒界形成成分を含んでいることを特徴とする請求
項12に記載の積層セラミックコンデンサの製造方法。
13. The method according to claim 1, wherein the conductive paste is 1 to 20 vol%.
13. The method for manufacturing a multilayer ceramic capacitor according to claim 12, comprising the grain boundary forming component.
JP2000125289A 2000-03-30 2000-04-26 Laminated ceramic capacitor and its manufacturing method Withdrawn JP2001307939A (en)

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TW090105118A TW508600B (en) 2000-03-30 2001-03-06 Laminated ceramic capacitor and its manufacturing method
KR1020010015083A KR100568398B1 (en) 2000-03-30 2001-03-23 Multilayer ceramic capacitor and method for manufacturing same
CN011120762A CN1216388C (en) 2000-03-30 2001-03-27 Stacked ceramic capacitor and its mfg. method
US09/823,157 US6673461B2 (en) 2000-03-30 2001-03-30 Multilayer ceramic capacitor and method for manufacturing same
MYPI20011528A MY130797A (en) 2000-03-30 2001-03-30 Multilayer ceramic capacitor and method for manufacturing same
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