JP2001298360A - Counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a counter capable of improving accuracy and also suppressing consumption current without increasing the clock frequency. SOLUTION: Two counters 1 and 2 are used to measure the Hi times of input signals A, B and C, the counter 1 counts the Hi times of the input signals with a CLK1, and the counter 2 counts the Hi times of the input signals with a CLK2 obtained by inverting the CLK1. Count values showing the Hi times are outputted by adding the outputs of the respective counters. In the case of the input signal A, the count value of the counter 1 becomes 3, the count value of the counter 2 becomes 4, and the final count value output count 7 is obtained by adding 3 to 4. Similarly, in the case of the input signal B, count 6 is obtained, and in the case of the input signal C, count 5 is obtained so that count accuracy being the same as count accuracy obtained by doubling a clock frequency can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a counter device for measuring a predetermined level period of an input signal using a clock.

[0002]

2. Description of the Related Art An arbitrary input signal is Hi (high level).
Time to change from low to low, or L
When the time from ow to Hi is measured by a counter circuit using a clock, a clock that changes in a sufficiently short time with respect to the time when the input signal changes, that is, a clock used for counting from the highest frequency of the input signal. The higher the frequency is set, the higher the counting accuracy can be.

FIG. 9 shows a first conventional example of a conventional counter device, and FIG. 10 shows the operation thereof. In FIG. 9, in the counter unit 100, an arbitrary signal, that is, a signal asynchronous with respect to the clock CLK is input to the enable unit EN.
The Hi time of the input signal is counted by CLK, and the count value is output to measure the time when the input signal changes.

In FIG. 10, Hi is used as the input signal.
The case where signals A, B, and C having different times are input will be described. Counter unit 10 when signal A is input
The count value output of 0 is 3 counts, and when the signal B and the signal C are input, the count value output is the same 3 counts.

The signal A and the signal C have a Hi time difference of C
Although the width of LK is slightly less than two clocks, the difference cannot be represented as a difference in the count value of the counter unit 100 and is treated as a measurement error. From the above, it is considered that increasing the clock frequency is a means for reducing the measurement error.

Therefore, as shown in the second conventional example of FIG. 11, in order to increase the counting accuracy, the doubling circuit 101 is used.
In the case where 2CLK whose frequency of CLK is twice as high as that of FIGS. 9 and 10 is used, as shown in FIG. 12, the count value output of the counter unit 100 when the signal A is input is as shown in FIG. 7 counts, 6 counts for signal B, 5 counts for signal C, and signals A, B,
For each C, the difference in the Hi time of the signal can be identified as the difference in the count value.

[0007]

However, FIG.
1. In the method of FIG. 12, a clock 2CL having a double frequency
A doubling circuit 101 for generating K is required, and the current consumption of the doubling circuit 101 increases.
In addition, the operation of the counter unit 100 at a high clock frequency is disadvantageous in terms of an operation margin, and the doubler circuit can be realized by an analog LSI process.
When the doubler circuit is realized by the digital LSI process, there is a problem that it is necessary to add a new LSI manufacturing process step for the doubler circuit.

The present invention has been made to solve the above-described problem, and can increase the counting accuracy without increasing the clock frequency, and can suppress a large increase in the current consumption of the counter section. It is intended to obtain a counter device.

[0009]

In order to achieve the above object, in a counter device according to the present invention, a plurality of counter means for receiving a signal in common and counting a predetermined level period of the signal using a clock are provided. A clock supply means for supplying clocks having different timings to each counter means, and an addition means for adding the count value of each counter means.

The clock supply means may be constituted by one or more inverters and / or one or more delay elements, and supply clocks of the same frequency to each counter means.

Also, two counter means are provided, and the clock supply means supplies the first clock to the first counter means and shifts the phase of the first clock by a half cycle by an inverter or a delay element. The second clock may be generated and the second clock may be supplied to the second counter means.

Also, four counter means are provided, and the clock supply means supplies a first clock to the first counter means, and supplies the first clock to one or more inverters and / or one or more The second, third, and fourth clocks whose phases are shifted by ４ cycle by the delay element are generated, and the second, third, and fourth clocks are supplied to the second, third, and fourth counter means. You may make it supply.

Further, two counter means are provided, and
The counter means outputs a predetermined signal when the count value is within a predetermined range, and the clock supply means supplies the first clock to the first counter means and outputs the first clock during the predetermined signal period. The second clock in which the first clock is shifted in phase by a half cycle using an inverter or a delay element.
May be generated, and this second clock may be supplied to the second counter means.

Further, setting means for setting a predetermined range may be provided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a counter device according to a first embodiment of the present invention, and FIG. 2 is a timing chart showing the operation thereof. 1, the counter device according to the present embodiment includes a counter unit 1, a counter unit 2, an inverter 5, and an adder 6. Each counter unit 1, 2
Counts the number of clocks CLK1 and CLK2 input while the enable unit EN is in the Hi state, and the respective counter outputs are added by the adder 6 to obtain a count value output as an added value. CLK2 is C
LK1 is inverted by an inverter 5.

Next, the operation will be described. In FIG. 1, an input signal that is asynchronous with respect to a clock is input to an enable unit EN of each of the counter units 1 and 2 to measure the Hi time. The counter unit 1 counts the input signal Hi time based on CLK1, and the counter unit 2 counts the input signal Hi based on CLK2 obtained by inverting CLK1 by an inverter 5.
Count the time. Then, the counter outputs of the respective counter units 1 and 2 are added by an adder 6 and output as a count value.

In FIG. 2, for example, when a signal A is input as an input signal to the enable units EN of the counter units 1 and 2, the count value of the counter unit 1 becomes 3 and the count value of the counter unit 2 becomes 4. . By adding these counter outputs by the adder 6, the final count value output becomes 3 + 4 = 7 counts. Similarly, in the case of the signal B, 6 (= 3 + 3) counts, and in the case of the signal C, 5 (= 3 + 3)
2) Counting is performed, and the same counting accuracy as doubling the clock frequency can be obtained.

FIG. 3 shows a counter device according to a second embodiment of the present invention. This embodiment uses the delay element (delay) 7 instead of the inverter 5 of FIG.
K2 is obtained. In this case, CLK2 of FIG. 2 is obtained by delaying CLK1 by a half cycle by the delay element 7. The configuration and operation of the other parts are the same as in FIG.

FIG. 4 shows a counter device according to a third embodiment of the present invention, and FIG. 5 is a timing chart showing the operation thereof. In the present embodiment, as shown in FIG.
In order to further improve the counting accuracy, four counter units 1, 2, 3, and 4 are provided.
1, CLK2, CLK3, and CLK4 are supplied. Further, the count outputs of the counter units 1 to 4 are added by the adder 11.

Further, as shown in FIG. 5, four types of clocks CLK1 to CLK4 having the same frequency and shifted in phase by 1/4 are generated by using the inverter 8 and the delay elements 9 and 10. According to the present embodiment, it is possible to obtain a counter accuracy equivalent to quadrupling the clock frequency.

FIG. 6 shows a counter device according to a fourth embodiment of the present invention. This embodiment uses the delay element 12 in place of the inverter 8 in FIG.
K1 to K4 are obtained. The configuration and operation of the other parts are the same as in the third embodiment.

FIG. 7 shows a counter device according to a fifth embodiment of the present invention, and FIG. 8 is a timing chart showing the operation thereof. In the present embodiment, the range of the count value output from the adder 6 is determined.
In FIG. 7, an input signal is input to the enable units EN of the two counter units 1 and 2, and the counter unit 1
LK1 is supplied, and CLK2 is supplied to the counter unit 2. CLK2 is obtained by ANDing the CLK1 and a CONT signal described later output from the counter unit 1 with the AND circuit 13.

Next, the operation will be described. Assuming that the range of the output count value is between the 103rd clock and the 109th clock with respect to the clock CLK1 of the counter unit 1, the counter unit 1 outputs
A CONT signal which becomes Hi during nine clocks is generated.
The CONT signal and CLK1 are applied to the AND circuit 13.

By making the AND output CLK2, as shown in FIG. 8, the count value of the adder output until the input signal asynchronous with respect to CLK1 changes from Hi to Low is, for example, 108 in FIG. It becomes a count.

According to the present embodiment, the supply of the clock CLK 2 to the counter section 2 may be performed only during the CONT signal period, which is the gate period of the AND circuit 13. That is, the adder 6
It is only necessary to supply six pulses of CLK2 during the count output value of 104 to 115 counts. Therefore, the current consumption of the counter section 2 can be reduced without deteriorating the counting accuracy.

Incidentally, a delay element may be used in place of the inverter 5 in FIG.
There may be provided setting means for arbitrarily setting the range of the count output value from which the NT signal is output.

[0027]

As described above, according to the present invention, a plurality of counter means are provided, clocks having different timings are supplied to the respective counter sections, and the count output values of the respective counter sections are added. Thus, the counting accuracy can be increased without increasing the clock frequency, and the current consumption can be suppressed.

Further, by configuring the clock supply means with an inverter and / or a delay element, it is possible to easily obtain clocks of the same frequency with shifted timing.

Further, the first clock is supplied to the first counter means, and the CONT signal is obtained in the predetermined count range, and the second clock is shifted by shifting the timing of the first clock in the CONT signal period. Is generated and supplied to the second counter means, the second counter means does not need to be constantly operating, and the current consumption can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a counter device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the counter device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a counter device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a counter device according to a third embodiment of the present invention.

FIG. 5 is a timing chart showing an operation of the counter device according to the third embodiment of the present invention.

FIG. 6 is a block diagram showing a counter device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a counter device according to a fifth embodiment of the present invention.

FIG. 8 is a timing chart showing an operation of the counter device according to the fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a counter device according to a first conventional example.

FIG. 10 is a timing chart showing the operation of the counter device according to the first conventional example.

FIG. 11 is a block diagram showing a counter device according to a second conventional example.

FIG. 12 is a timing chart showing the operation of the counter device according to the second conventional example.

[Explanation of symbols]

 1, 2, 3, 4 Counter section 5, 8 Inverter 6, 11 Adder 7, 9, 10, 12 Delay element 13 AND circuit A, B, C Input signal CLK1, CLK2 Clock CONT CONT signal

Claims (6)

[Claims] A plurality of counter means for receiving a signal in common and counting a predetermined level period of the signal using a clock; a clock supply means for supplying a clock having a timing shifted to each counter means; A counter device provided with an adding means for adding the count value of the counter means. 2. The clock supply means according to claim 1, wherein said clock supply means comprises one or more inverters and / or one or more delay elements, and supplies a clock of the same frequency to each of said counter means. Counter device. 3. The counter means is provided in two units, and the clock supply means supplies a first clock to the first counter means and divides the first clock into a half cycle by an inverter or a delay element. 2. The counter device according to claim 1, wherein a second clock having a phase shifted is generated, and the second clock is supplied to second counter means. 4. The counter means is provided with four clock means, and the clock supply means supplies a first clock to the first counter means and supplies the first clock to one or more inverters and / or one or more inverters. 1 /
The second, third, and fourth clocks whose phases are shifted by four periods are generated, and the second, third, and fourth clocks are supplied to second, third, and fourth counter means. The counter device according to claim 1, wherein 5. The apparatus according to claim 1, wherein two counters are provided, and the first counter outputs a predetermined signal when the count value is within a predetermined range. Is supplied to the first counter means, and a second clock in which the phase of the first clock in the predetermined signal period is shifted by a half cycle with an inverter or a delay element is generated. 2. The counter device according to claim 1, wherein said clock is supplied to said second counter means. 6. The counter device according to claim 1, further comprising setting means for setting the predetermined range.