JP2001298088A - Method for verifying layout data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for verifying layout data, by which a mask layout pattern and a circuit diagram can be compared and collated in a short time without preparing a circuit diagram for verification irrespective of the number of emitter holes in a lateral PNP transistor. SOLUTION: This layout data verifying method uses a computer to verify whether an integrated circuit mask layout pattern prepared based on a circuit diagram is equivalent to the circuit diagram. Element connection information is extracted based on a base layer in the integrated circuit mask layout pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for verifying layout data.

[0002]

2. Description of the Related Art When designing an integrated circuit, a circuit diagram is first created, and an integrated circuit mask layout pattern (hereinafter simply referred to as a mask layout pattern) is designed based on the circuit diagram.

However, as the degree of integration of integrated circuits increases,
The mask layout pattern becomes very complicated, and it is necessary to verify whether a circuit embodied by the designed mask layout pattern is equivalent to a circuit on the original circuit diagram. It is very difficult to perform such verification manually.

For this reason, a computer has been conventionally used for such verification. That is, the designed mask layout pattern is digitized and taken into a computer as digital data, which is subjected to a graphic operation and a phase operation to check the connection relationship between elements, and is extracted as circuit connection information. To fetch circuit connection information, compare and collate the two, and check for match / mismatch.

FIG. 4 is a flowchart showing a manufacturing process of the integrated circuit device.

When manufacturing an integrated circuit device, a basic circuit diagram is created (step 401), and a mask layout pattern is designed based on the created circuit diagram (step 402). Next, an integrated circuit device is manufactured using this mask layout pattern (step 403).

Here, the mask layout pattern is verified before manufacturing the integrated circuit device using the mask layout pattern, that is, at the stage of designing the mask layout pattern.

In this verification, circuit connection information extracted from the mask layout pattern designed in step 402 (information indicating how each element is connected).
And the circuit connection information extracted from the circuit diagram created in step 401. If the two coincide, it can be confirmed that the mask layout pattern designed in step 402 correctly corresponds to the circuit diagram created in step 401.

FIG. 5 is a flowchart showing a process of verifying a mask layout pattern using a computer disclosed in, for example, Japanese Patent Application Laid-Open No. H6-110973.

Circuit connection information is extracted from a mask layout pattern in the following procedure.

First, in step 501, digitization is performed, and a mask layout pattern is fetched into a computer as digital data (graphic data).

In step 502, a hierarchical structure is developed for the acquired mask layout pattern data. Generally, a current integrated circuit is designed with a hierarchical structure, and the mask layout pattern designed in step 402 is not a state in which all the graphic patterns are developed on one plane. In the mask layout pattern of the upper hierarchy, instead of expressing a specific graphic pattern of the lower hierarchy, it is expressed as one cell. Then, a specific graphic pattern in this cell is prepared as a mask layout pattern of a lower hierarchy. The hierarchical structure development process in step 502 is a process of developing the mask layout pattern represented by such a hierarchical structure into a state where all the graphic patterns are represented on one plane.

Next, in step 503, circuit connection information is extracted from the developed mask layout pattern. Specifically, first, an operation for recognizing each circuit element is performed. For example, for a bipolar transistor, a figure pattern obtained by performing an AND operation between the figure pattern of the base diffusion layer and the figure pattern of the polysilicon layer can be recognized as the emitter layer. Recognition of each circuit element is performed by such graphic operation, and subsequently, equipotential recognition is performed for each node to obtain connection information between the circuit elements. The recognition of the equipotential is performed by calculating the phase between the layers of the mask layout pattern. For example, if a contact hole graphic pattern exists in an overlapping region of two wiring layers provided as two different graphic patterns, the two wiring layers are recognized as having the same potential. Thus, through step 503, circuit connection information extracted from the mask layout pattern is obtained. Here, this information will be referred to as circuit connection information on the layout side.

On the other hand, circuit connection information is extracted from the circuit diagram created in step 401 in the following procedure.

First, in step 504, circuit connection information in a hierarchical representation is extracted from a circuit diagram. Usually, a circuit diagram is also created in a representation having a hierarchical structure, and it is common to create a circuit diagram using a computer. Therefore, the process of step 504 is a process of extracting circuit connection information with a hierarchical expression based on data corresponding to a circuit diagram prepared in the computer. Since such processing is a known technique, a detailed description is omitted here.

Subsequently, in step 505, the hierarchical structure of the extracted circuit connection information is expanded to obtain circuit connection information on the circuit diagram side.

As described above, circuit connection information on the layout side is extracted from the mask layout pattern designed in step 402, and circuit connection information on the circuit diagram side is extracted from the circuit diagram created in step 401. At 506, the two are compared. If the circuit embodied in the mask layout pattern is equivalent to the circuit on the circuit diagram, they should match. Therefore, if a match occurs, it can be determined that an error in the mask layout pattern exists at that location.

[0018]

Here, the lateral PN
FIG. 6 shows how the P transistor is extracted in step 503 of FIG.

In FIG. 6, reference numeral 1 denotes a mask layout pattern of a lateral PNP transistor having one emitter hole EH, and reference numeral 2 denotes a lateral PNP transistor having two emitter holes EH.
The mask layout pattern 3 of the NP transistor is a mask layout pattern of a lateral PNP transistor having three emitter holes EH.

A lateral PN having one emitter hole EH
The circuit symbol 7 is extracted from the mask layout pattern 1 of the P transistor as element connection information. From the mask layout pattern 2 of the lateral PNP transistor having two emitter holes EH, a circuit symbol 8 is extracted as element connection information. From the mask layout pattern 3 of the lateral PNP transistor having three emitter holes EH, the circuit symbol 9 is used as element connection information.
Is extracted. In the mask layout pattern of FIG. 6, B is a base layer and E is an emitter layer.

Therefore, in step 506, when the circuit connection information on the layout side is compared with the circuit connection information on the circuit diagram side, a mismatch occurs at the lateral PNP transistor.

That is, on the circuit diagram side, regardless of the number of emitter holes EH in the mask layout pattern, the lateral PNP transistor is represented by one circuit symbol 10 as shown in FIG. However, the circuit symbols obtained from the layout side differ depending on the number of the emitter holes EH, as shown in FIGS.

For this reason, conventionally, the lateral PN
When a P transistor is used, a circuit symbol of a lateral PNP transistor having two emitter holes is shown as a circuit symbol 8 in FIG. 6B, and a circuit symbol of a lateral PNP transistor having three emitter holes is shown in FIG. It is necessary to prepare a circuit diagram for comparison and comparison (a circuit diagram for verification) in which the circuit symbols 9 shown in FIG.

In the "Reconstruction circuit connection shaping method in layout verification of CMOS / LSI" disclosed in Japanese Patent Application Laid-Open No. 4-340172, it is proposed to perform equivalent transistor degeneration processing. Although there is no need to prepare a circuit diagram, there is a problem that the degeneration processing takes time.

The present invention has been made in view of the above points, and is capable of reducing a mask layout pattern in a short time without preparing a circuit diagram for verification regardless of the number of emitter holes of a lateral PNP transistor. It is an object of the present invention to provide a layout data verification method capable of comparing and collating with a circuit diagram.

[0026]

A first invention (an invention according to claim 1) uses a computer to verify whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram. In the layout data verification method, the connection information of the elements is extracted based on the base layer in the integrated circuit mask layout pattern. According to the present invention, device connection information is extracted based on the base layer in the integrated circuit mask layout pattern.

A second invention (an invention according to claim 2) is a layout data verification method for verifying, using a computer, whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to a circuit diagram. In this method, a circuit symbol of a lateral PNP transistor is extracted based on a base layer in an integrated circuit mask layout pattern. According to the present invention, a circuit symbol of a lateral PNP transistor is extracted based on a base layer in an integrated circuit mask layout pattern.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining an embodiment of a layout data verification method according to the present invention.

6, the same reference numerals as those in FIG. 6 denote the same or equivalent components.

In this embodiment, when extracting the connection information of the lateral PNP transistor from the mask layout pattern, the extraction is performed based on the base layer.

That is, a circuit symbol 4 is extracted from the mask layout pattern 1 of one lateral PNP transistor having the emitter hole EH shown in FIG. 1 (b)
The circuit symbol 5 is extracted from the mask layout pattern 2 of the lateral PNP transistor having two emitter holes EH as shown in FIG. 1 as element connection information based on the base layer B, and the emitter hole EH shown in FIG. Extracts the circuit symbol 6 from the mask layout pattern 3 of the three lateral PNP transistors based on the base layer B as the connection information of the elements.

The circuit symbols 4, 5, and 6 match the circuit symbol 10 shown on the circuit diagram side and shown in FIG. That is, in this embodiment, the lateral PNP
Since the circuit symbols are extracted based on the base layer B from the mask layout pattern of the transistors, the number of extracted circuit symbols is not related to the number of the emitter holes EH, but matches the circuit symbols expressed on the circuit diagram side. become.

Therefore, according to this embodiment, there is no need to prepare a circuit diagram for verification. Further, compared with the method of performing the equivalent transistor degeneration processing, the comparison and comparison between the mask layout pattern and the circuit diagram can be performed in a shorter time.

FIG. 2 shows a procedure for extracting a circuit symbol 4 from a mask layout pattern of a lateral PNP transistor having one emitter hole EH.

As shown in FIG. 2A, the mask layout pattern of a lateral PNP transistor having one emitter hole EH includes a buried layer U and a base diffusion layer B.
S, Locos layer LO and text LP-1.

First, the portion in the area of the base diffusion layer BS having a hole is designated as the "EmitP" layer (FIG. 2).
(B)). Next, a place where the hole in the area of the base diffusion layer BS is filled is designated as a “PbpdiffC” layer (FIG. 2C),
The region of the buried layer U is designated as the “PNParea” layer (FIG. 2D), and the region of the locos layer LO is designated as “locos”.
The layer is designated (FIG. 2E). A layer in which text is assigned to LP-1 in the “PNParea” layer is referred to as an “lp1” layer. Then, the “lp1” layer is used as a device recognition layer,
“EmitP” layer as emitter layer, “PbpdiffC”
The layer is designated as a collector layer and the “locos” layer is designated as a base layer, and the circuit symbol 4 is extracted based on the designated base layer.

FIG. 3 shows a procedure for extracting a circuit symbol 5 from a mask layout pattern of a lateral PNP transistor having two emitter holes EH.

As shown in FIG. 3A, the mask layout pattern of a lateral PNP transistor having two emitter holes EH includes a buried layer U and a base diffusion layer B.
S, Locos layer LO and text LP-2.

First, a portion in the area of the base diffusion layer BS where a hole is formed is designated as an "EmitP" layer (FIG. 3).
(B)). Next, the place where the hole in the area of the base diffusion layer BS is filled is designated as the “PbpdiffC” layer (FIG. 3C),
The area of the buried layer U is designated as the “PNParea” layer (FIG. 3D), and the area of the locos layer LO is “locos”.
The layer is designated (FIG. 3E). A layer in which text is assigned to LP-2 in the “PNParea” layer is referred to as an “lp2” layer. Then, the “lp2” layer is used as a device recognition layer,
“EmitP” layer as emitter layer, “PbpdiffC”
The layer is designated as the collector layer and the “locos” layer is designated as the base layer, and the circuit symbol 5 is extracted based on the designated base layer.

[0041]

As is apparent from the above description, according to the present invention, the connection information of the elements is extracted based on the base layer in the integrated circuit mask layout pattern. Is no longer related to the number of emitter holes, and the mask layout pattern can be compared with the circuit diagram in a short time without preparing a circuit diagram for verification.

[Brief description of the drawings]

FIGS. 1A to 1C are diagrams illustrating an embodiment of a layout data verification method according to the present invention.

FIGS. 2A to 2E are diagrams showing a procedure for extracting a circuit symbol from a mask layout pattern of a lateral PNP transistor having one emitter hole EH.

FIGS. 3A to 3E are diagrams illustrating a procedure for extracting a circuit symbol from a mask layout pattern of a lateral PNP transistor having two emitter holes EH.

FIG. 4 is a flowchart showing a manufacturing process of the integrated circuit device.

FIG. 5 is a flowchart showing a mask layout pattern verification process using a computer disclosed in, for example, Japanese Patent Application Laid-Open No. 6-110973.

6 (a) to 6 (c) are diagrams showing how a lateral PNP transistor is extracted in step 503 of FIG.

FIG. 7 is a diagram showing a circuit symbol representing a lateral PNP transistor on the circuit diagram side.

[Explanation of symbols]

 1, 2, 3 Mask layout pattern 4, 5, 6, 7, 8, 9, 10 Circuit symbol

Claims (6)

[Claims] 1. A layout data verification method for verifying, using a computer, whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, comprising: a base in the integrated circuit mask layout pattern; A layout data verification method, wherein element connection information is extracted based on layers. 2. A layout data verification method for verifying, using a computer, whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, comprising the steps of: A method of verifying layout data, wherein a circuit symbol of a lateral PNP transistor is extracted based on a layer. 3. A layout data verification apparatus for verifying whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, comprising: a base layer in the integrated circuit mask layout pattern; An apparatus for verifying layout data, wherein connection information of elements is extracted. 4. A layout data verifying apparatus for verifying whether an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, comprising: a base layer in the integrated circuit mask layout pattern; A layout data verification apparatus, wherein a circuit symbol of a lateral PNP transistor is extracted. 5. A recording medium storing a computer program for verifying whether or not an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, wherein a base layer in the integrated circuit mask layout pattern is A recording medium on which a computer program is recorded, based on which connection information of an element is extracted. 6. A recording medium recording a computer program for verifying whether an integrated circuit mask layout pattern created based on a circuit diagram is equivalent to the circuit diagram, wherein a base layer in the integrated circuit mask layout pattern is A recording medium storing a computer program, wherein a circuit symbol of a lateral PNP transistor is extracted based on the extracted computer symbol.