JP2000268077A - Element recognizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an element recognizing method capable of recognizing an element without depending on the number of elements desired to distinguish the number of recognizing layers. SOLUTION: In order to recognize the elements of transistors N1, N2 and N3 in the same layout structure at the time of verification, layout data are prepared by arranging recognition patterns 11-13 having the different number of contact sides in different two layers corresponding to minimum gate lengths G1-G3 of MOS transistors. The elements can be recognized by extracting the recognition patterns 11-13 from the layout data. The recognition patterns 11-13 are graphic data when the number of contact sides between a white rectangular graphic arranged in a certain layer and a black rectangular graphic arranged in the other layer is 2, 3 or 4 and at the time of verification, the element is recognized from the number of contact sides of these graphic data. Regardless of the number of kinds of elements, the graphic data are arranged in two recognizing layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for recognizing elements, and more particularly to a method for recognizing elements from layout data in a large-scale semiconductor integrated circuit (LSI) layout verification tool.

[0002]

2. Description of the Related Art In a layout verification tool, when recognizing elements of layout data, the layout structure is the same, but the elements may be treated as different elements. For example, transistors having the same layout structure but different minimum gate length dimensions may be treated as separate elements. Conventionally, when recognizing an indistinguishable element in the layout structure as described above, two methods are known: a method using a different recognition layer for each element type and a method using text (TEXT). (Japanese Patent No. 2788804,
3-36553).

In the former element recognition method using a different recognition layer for each element type, for example, a transistor 1 having a gate length g1 shown in FIG. 6A and a transistor having a gate length g2 shown in FIG. The gate lengths of the transistor 2 and the transistor 4 having the gate length g3 shown in FIG.
<G3, the transistor 2 has recognition layer data indicating the recognition layer 3 and the transistor 4
Is inserted into the recognition layer data indicating the recognition layer 5 that is different from the recognition layer 3 so that three types of transistors 1 and
2 and 4 are distinguished, and a logical operation is performed on each data of the element formation layer and the recognition layer to distinguish the layout structure.

In the latter conventional element recognition method using the text (TEXT), for example, a transistor 1 having a gate length g1 shown in FIG. 7A, a transistor 2 having a gate length g2 shown in FIG. Gate length g shown in FIG.
G1 <g2 <g
3, the transistor 2 has B
The text “Tr” is placed, and the transistor 4
By arranging different texts, distinction is made in terms of layout structure depending on the text characters.

[0005]

However, in the conventional element recognition method described with reference to FIG. 6, recognition layers are required for the number of types of elements to be distinguished. However, there is an upper limit to the number of layout layers that can be used in a general layout drawing tool and LSI verification tool. Moreover, in recent years, in LSI design, there is a tendency to miniaturize processes and form various devices on the same chip, and the number of layers used for configuring the manufacturing process is increasing, so that many LSIs can be used as recognition layers. However, there is a problem that the number of types of elements to be distinguished is limited.

On the other hand, the conventional element recognition method described with reference to FIG. 7 has a problem in that the recognition text must always be arranged at the highest level that can be recognized by the verification tool at the verification level. That is, text is treated as terminal information in a general verification tool. Also, in the hierarchical layout, text as terminal information is arranged in each hierarchical level in order to perform verification at each hierarchical level utilizing the characteristics. Therefore, when recognizing texts of all hierarchies, there is a problem in that an error is detected as a plurality of texts as a plurality of terminals on the same node.

In order to avoid this problem, in a general verification, it is necessary to validate only the recognition of the text arranged at the highest level. Therefore, the text for area recognition shown in the conventional element recognition method described with reference to FIG. 7 also needs to be always arranged at the highest hierarchy at the time of verification.
However, since the highest hierarchy at the time of verification is not always the same hierarchy depending on the element, text for element recognition which should originally be arranged in a specific area must be arranged in each of the highest hierarchy for each element. In addition, there is a problem that the number of steps is increased.

[0008] The present invention has been made in view of the above points,
It is an object of the present invention to provide an element recognition method in which the number of recognition layers can perform element recognition without depending on the number of elements to be distinguished.

Another object of the present invention is to provide an element recognition method that allows easy data input in hierarchical verification.

[0010]

According to the present invention, there is provided a method for recognizing a layout pattern of a semiconductor integrated circuit, the method comprising the steps of: As at least one side of each of the figures of an arbitrary shape arranged on each of the different arbitrary two layers is in contact with each other through the two layers,
In addition, layout data is created by arranging graphic patterns with different numbers of tangent sides according to the same element type, creating layout data, and extracting the graphic pattern from the layout data based on the number of tangent sides during verification to perform element recognition. It is characterized by.

According to the present invention, in order to achieve the above object, a figure pattern having a different layout according to the type of the same element is arranged in an arbitrary hierarchy as a recognition pattern for element recognition. Then, layout data is created, and at the time of verification, a figure pattern is extracted from the layout data based on the shape to perform element recognition. Here, the graphic pattern is a graphic having a different number of vertices or a graphic having a different area according to the type of element.

According to the present invention, in order to achieve the above object, as a recognition pattern for element recognition, a figure having the same shape and a layout pattern having a different number according to the type of the same element are arbitrarily set. It is characterized in that layout data is created by arranging in one hierarchy, and a graphic pattern is extracted from layout data based on the number of graphics during verification to perform element recognition.

In the present invention, layout data is created by arranging graphic patterns having different numbers of tangent sides, shapes, or numbers in two or less recognition layers according to the type of the same element, and creating layout data. Since the graphic pattern is extracted from the layout data, an arbitrary number of elements can be recognized in two or less recognition layers.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows various pattern diagrams according to an embodiment of the element recognition method according to the present invention. FIG.
(A) is a recognition pattern diagram of the transistor N1, and FIG.
(B) is a recognition pattern diagram of the transistor N2, and FIG.
(C) shows a recognition pattern diagram of the transistor N3. M
The OS transistors N1, N2, and N3 have the same layout structure, but have minimum gate lengths of G1, G2, and G3, respectively, and have a different relationship of G1 <G2 <G3.

In this embodiment, the transistors N1, N2, and N3 having the same layout structure are recognized as separate elements from layout data at the time of comparison with a later circuit diagram. At this stage, the designer arranges the recognition pattern 11 shown in FIG. 1A, the recognition pattern 12 shown in FIG. 1B and the recognition pattern 13 shown in FIG. 1C according to the minimum gate length of the MOS transistor. Generated layout data. The above recognition patterns 11, 12, and 13 are patterned using two recognition layers of an LSI verification tool. That is, the recognition layer A shown in FIG.
A recognition layer B different from the recognition layer A, which is indicated by a white square in (D), is used.

As shown in FIG. 2B, the first recognition pattern 11 is a pattern having one recognition layer B and one recognition layer B in contact with one recognition layer. As shown in FIG. 2C, the second recognition pattern 12 is a pattern in which the number of tangent sides where two recognition layers B are in contact with one recognition layer A on each of the left and right sides thereof is two. Further, the third recognition pattern is shown in FIG.
As shown in (D), the recognition layer B is a pattern having three contact sides where one recognition layer B is in contact with one recognition layer A on the left, right, and underneath.

At the LSI logic circuit design stage, the designer
When the minimum gate length of the MOS transistor is G1, the recognition pattern 11 shown in FIG.
As shown in the figure, by arranging it in the region of the transistor N1 on the screen, data indicating that the number of tangent sides between the two recognition layers A and B is 1 is input. Similarly, MO
When the minimum gate length of the S transistor is G2, the recognition pattern 12 shown in FIG. 2C is arranged in the region of the transistor N2 on the screen as shown in FIG. The number of tangent sides between two recognition layers A and B is 2
Is input, and when the minimum gate length of the MOS transistor is G3, the recognition pattern 13 shown in FIG. 2C is changed to the area of the transistor N3 on the screen as shown in FIG. , The data that the number of tangent sides between the two recognition layers A and B is 3 is input, and layout data is generated.

At the LSI logic circuit design stage, AREA_1 to AREA_3, GA
Characters TE_1 to GATE_3 are not displayed, and a rectangular area and the above recognition patterns 11 to 13 are displayed.
As described above, at the stage of designing a logic circuit of an LSI, the recognition patterns 11 to 13 indicating the types of transistors are arranged according to the minimum gate length of the MOS transistor. It is easier to distinguish visually than. Moreover, in this embodiment,
Only two recognition layers, the recognition layer A and the recognition layer B, can perform three types of element recognition, and the arrangement positions of the recognition layers can be made independent of the hierarchy.

Next, after the completion of the LSI logic circuit design, a recognition pattern is extracted from the layout data by using the function of recognizing the characteristic of the figure shape in the LSI verification tool at the time of comparison with the circuit including the transistor. The operation in the case of performing transistor recognition will be described. The process of calculating the number of tangent sides of the recognition layer is a process provided in a general verification tool.

A specific description will be given with reference to the flowchart of FIG. 3 and the graphic of FIG. 2 using a rule file for executing the verification tool. In this embodiment, first, a recognition pattern is extracted from layout data according to the number of sides where different layers are in contact with each other (step 21 in FIG. 3). The SELECT command used for extracting the recognition pattern is:
It is expressed in a format of “SELECT A CONDITION BC”, and performs a process of copying only the data that matches the condition described in the CONDITION to the data layer C among the data layer A among the data layer A to the data layer C. is there.

Hereinafter, the rectangle formed by the recognition layer A is referred to as PAT.
TERN_A, and the rectangle formed by the recognition layer B is PA
It shall be represented by TTERN_B. Accordingly, the SELECT command used for the recognition pattern in step 21 is represented by SELECT PATTERN_A TOUCH [1] PATTERN_BFIG_1 (1-1) when the first recognition pattern 11 is extracted. Note that TOUCH [1] indicates that the number of tangent sides of the recognition layers A and B is one. (1-1) is PATTERN_
PAT with only one side (TOUCH [1]) in contact with B
This indicates that TERN_A is set to FIG_1.

Similarly, when extracting the second recognition pattern 12,
When the third recognition pattern 13 is extracted, the number of tangent sides of the recognition layers A and B is two or three, respectively. SELECT PATTERN_A TOUCH [2] PATTERN_B FIG_2 (1-2) SELECT PATTERN_A TOUCH [3] PATTERN_B FIG_3 (1) -3) where each of the recognition patterns 12 and 13 is
_2, FIG_3.

Subsequently, using the extracted recognition pattern,
Element regions are distinguished (Step 22 in FIG. 3). The distinction between the element regions includes the first recognition pattern FIG_1 (EN
CLOSE) The element region (AREA) is set to AREA_1 and includes the second recognition pattern FIG_2 (ENCLO).
SE) The element region (AREA) is AREA_2, and the third
(ENCLOSE) element region (AREA) including the recognition pattern FIG_3 is set to AREA_3.
This is expressed as the SELECT command as follows.

SELECT AREA ENCLOSE FIG_1 AREA_1 (2-1) SELECT AREA ENCLOSE FIG_2 AREA_2 (2-2) SELECT AREA ENCLOSE FIG_3 AREA_3 (2-3) These AREA_1, AREA_2 and AREA_3
Indicates a region illustrated in FIGS. 1A, 1B, and 1C.

Subsequently, the element components included in the element regions identified in step 22 are extracted (step 23 in FIG. 3). In the case of the recognition of a transistor, a portion where a diffusion layer and polysilicon overlap is defined as a gate by the following equation GATE = DIFFUSION AND POLY (3-1), and element regions AREA_1 and AREA_2 are defined by the following equations.
And GATE included in AREA_3
Extract as E_1, GATE_2 and GATE_3.

GATE_1 = AREA_1 AND GATE (3-2) GATE_2 = AREA_2 AND GATE (3-3) GATE_3 = AREA_3 AND GATE (3-4) Finally, recognition of the transistor composed of the element components extracted in step 23 (Step 24 in FIG. 3).
An element (ELEMENT) command for element recognition is “ELEMENT NAME abcd”
And the element "NAME" is b,
It is defined that it is composed of elements c and d. a
The device element is described, and it is necessary to be unique to NAME in order to distinguish various elements by this part.

In the case of a MOS transistor, the above ELE
In the MENT command, it is necessary to define a for a gate, b for polysilicon (material of a gate portion), c for a diffusion layer (material for a source / drain), and d for a well (material for a bulk portion). Therefore, in the case of FIG.
The transistors N1, N2, and N3 are recognized by the NT command.

ELEMENT MOS [N1] GATE_1 POLY DIFFUSION BULK (4-1) ELEMENT MOS [N2] GATE_2 POLY DIFFUSION BULK (4-2) ELEMENT MOS [N3] GATE_3 POLY DIFFUSION BULK (4-3) (4-1) As shown in FIG. 1A, the gate portion has a GA
This means that the transistor that is TE_1 is recognized as the transistor N1. Similarly, (4-2) corresponds to FIG.
Recognizing a transistor whose gate portion is GATE_2 as a transistor N2 as shown in FIG.
3), as shown in FIG. 1C, the gate portion is GATE_
Recognizing the transistor 3 as the transistor N3 means respectively.

Next, a second embodiment of the present invention will be described. The second embodiment is an element recognizing method for recognizing a recognition pattern based on a difference in the number of vertices of a recognition layer using a recognition pattern as shown in FIG. This embodiment is characterized in that only the step 21 in FIG. 3 extracts the element recognition pattern using the recognition pattern shown in FIG. 4, and steps 22 to 24 in FIG. Same as the form.

FIGS. 4A, 4B, 4C and 4D
Is a triangle with 3, 4, 5, and 6 vertices, respectively.
Squares, pentagons and hexagons are shown, which are shown in FIG.
Is used instead of the recognition pattern shown in FIG. Therefore,
For example, as a recognition pattern of the transistors N1, N2, and N3, a recognition pattern having a shape shown in FIGS. 4B, 4C, and 4D is used by a designer.

The element recognition of the LSI verification tool after the completion of the design is performed according to the flowchart shown in FIG.
In this embodiment, the SELECT command used for extracting the recognition pattern in step 21 of FIG.
At the time of extracting the recognition pattern of the square in (B), it is represented by SELECT PATTERN_A VERTEX [4] FIG_4 (5-1). This means that PATTERN_A having four vertices is set to FIG_4. Note that VE
RTEX [4] indicates that the number of vertices is 4. Similarly, when the pentagonal recognition pattern in FIG.
When extracting the recognition pattern of the hexagon in (D), since the number of vertices is 5 and 6, respectively, SELECT PATTERN_A VERTEX [5] FIG_5 (5-2) SELECT PATTERN_A VERTEX [6] FIG_6 (5-3) , PATTERN_A with 5 vertices
IG_5, PATTERN_A with 6 vertices
IG_6.

Next, a third embodiment of the present invention will be described. The third embodiment is an element recognizing method in which a recognition pattern is distinguished based on a difference in the area of a recognition layer using a recognition pattern as shown in FIG. This embodiment is characterized in that only step 21 in FIG. 3 extracts the element recognition pattern using the recognition pattern shown in FIG. 5, and steps 22 to 24 in FIG. Same as the form.

FIGS. 5A, 5B and 5C show rectangular recognition patterns having areas of 1, 2 and 3, respectively, which are used instead of the recognition patterns shown in FIG. 2 or FIG. Used for Therefore, for example, the transistor N
FIG. 5 (A) shows the recognition patterns of 1, N2 and N3.
The recognition patterns of the shapes shown in (B) and (C) are used by the designer.

The element recognition of the LSI verification tool after the design is completed is performed according to the flowchart shown in FIG.
In this embodiment, the SELECT command used for the recognition pattern in step 21 of FIG. 3 is such that SELECT PATTERN_A AREA [1.00] FIG_7 (6-1) It is represented by This means that the area of PATTERN_A is 1
(AREA [1.00]) means FIG_7. Similarly, when extracting the recognition pattern of the rectangle having the area 2 in FIG. 5B and extracting the recognition pattern of the rectangle having the area 3 in FIG. 5C, the areas are 2 and 3, respectively. SELECT PATTERN_A ARAE [2.00 ] FIG_8 (6-2) SELECT PATTERN_A AREA [3.00] FIG_9 (6-3)
________________________________________________________________________________________
9 is assumed.

The present invention is not limited to the above embodiment. For example, in the above embodiment, three types of element recognition have been described.
Alternatively, by increasing the number of tangent sides, the number of vertices, or the area by only one recognition layer A, four or more types of element recognition can be performed. Even if the two recognition layers A and B have overlapping sides, Further, it is also possible to form a recognition pattern in which two or more types of elements are recognized by different shapes or different numbers of the same shape. Furthermore,
It goes without saying that elements other than MOS transistors can be similarly recognized as elements to be recognized.

[0036]

As described above, according to the present invention,
For the layout structure, figure data with different numbers of tangent sides, shapes or numbers according to the same element type are arranged in two or less recognition layers to create layout data, and this figure pattern is extracted from the layout data during verification. By doing so, an arbitrary number of elements can be recognized by two or less recognition layers, so that it is suitable for an LSI verification tool having an upper limit on the layout layers that can be used, so that many The type of element can be recognized.

Further, according to the present invention, since the figure pattern is used as the recognition pattern, the arrangement position of the recognition pattern does not depend on the hierarchy, and may be arranged at an arbitrary hierarchy. Compared with the conventional method for recognizing the pattern, the number of steps for arranging the recognition pattern can be reduced and the verification in the hierarchical layout can be easily performed.

Further, according to the present invention, since the recognition pattern representing the type of the element by the characteristic of the figure shape is used, the recognition at the time of creating the layout data is different from the conventional method of inserting a recognition layer. The layout of the patterns can be visually easily performed, and the efficiency of layout creation can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of elements and recognition patterns recognized by an embodiment of the method of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of a recognition pattern used in the method of the present invention.

FIG. 3 is a flowchart of an embodiment of the method of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of a recognition pattern used in the method of the present invention.

FIG. 5 is an explanatory diagram of a third embodiment of a recognition pattern used in the method of the present invention.

FIG. 6 is an explanatory diagram of an example of a conventional method.

FIG. 7 is an explanatory diagram of another example of the conventional method.

[Explanation of symbols]

 11, 12, 13 Recognition pattern 21 to 24 Processing step A, B Recognition layer G1, G2, G3 Gate length

Claims (6)

[Claims] In a method for recognizing layout data required for verification by a tool for verifying the layout of a semiconductor integrated circuit, an arbitrary two different patterns are used as recognition patterns for recognizing elements.
At least one side of each of the figures of an arbitrary shape arranged in each of the layers is in contact with each other through the two layers, and the layout structure is configured by arranging a figure pattern having a different number of tangent sides according to the same element type. An element recognition method, wherein layout data is created, and at the time of the verification, the graphic pattern is extracted from the layout data based on the number of tangent sides to perform element recognition. 2. The element recognizing method according to claim 1, wherein the graphic patterns are arranged on the two different layers in the same graphic shape. 3. A method of recognizing layout data required for verification by a tool for verifying the layout of a semiconductor integrated circuit, wherein the layout structure has different shapes according to the type of the same device as a recognition pattern for recognizing the device. An element recognizing method, wherein the layout data is created by arranging the graphic patterns described above in an arbitrary hierarchy, and the graphic patterns are extracted from the layout data based on the shape during the verification to perform element recognition. 4. The graphic pattern according to claim 3, wherein the graphic pattern is a graphic having a different number of vertices according to the type of element, and recognizes that the element is different depending on the number of vertices during the verification. Element recognition method. 5. The apparatus according to claim 3, wherein the figure pattern is a figure having a different area according to the type of the element, and recognizes that the element differs depending on the size of the area during the verification. Element recognition method. 6. A device for recognizing layout data required for verification by a tool for verifying the layout of a semiconductor integrated circuit, wherein a pattern having the same shape is used as a recognition pattern for recognizing the device and the layout structure is the same type of device. The layout data is created by arranging graphic patterns of different numbers according to the number of layers in an arbitrary hierarchy, and performing the element recognition by extracting the graphic patterns from the layout data based on the number of the graphics during the verification. Characteristic element recognition method.