JP3540191B2 - Device recognition method for layout data of layout verification tool for semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a device recognition method, and more particularly to a device recognition method from layout data in a large-scale semiconductor integrated circuit (LSI) layout verification tool.
[0002]
[Prior art]
In the layout verification tool, in the element recognition of the layout data, the layout structure is the same, but it may be treated as another element. For example, transistors having the same layout structure but different gate length minimum dimensions may be treated as separate elements. Conventionally, when recognizing an indistinguishable element in the layout structure as described above, two methods are known: a method using a different recognition layer for each element type and a method using text (TEXT). (Japanese Patent No. 2788804, JP-A-63-36553).
[0003]
In the former element recognition method using a different recognition layer for each element type, for example, a transistor 1 having a gate length g1 shown in FIG. 6A, a transistor 2 having a gate length g2 shown in FIG. Assuming that each gate length of the transistor 4 having a gate length g3 shown in FIG. 3C has a relationship of g1 <g2 <g3, the transistor 2 receives recognition layer data indicating the recognition layer 3 and the transistor 2 For 4, by inserting recognition layer data indicating a recognition layer 5 different from the recognition layer 3, three types of transistors 1, 2 and 4 are distinguished, and a logical operation of each data of the element formation layer and the recognition layer is performed. Is performed to make a distinction in the layout structure.
[0004]
In the latter conventional element recognition method using the text (TEXT), for example, a transistor 1 having a gate length g1 shown in FIG. 7A, a transistor 2 having a gate length g2 shown in FIG. Assuming that each gate length of the transistor 4 having the gate length g3 shown in) has a relationship of g1 <g2 <g3, a text of BTr is arranged in the transistor 2 and a text of CTr is arranged in the transistor 4. By doing so, a distinction is made in the layout structure depending on the characters of the text.
[0005]
[Problems to be solved by the invention]
However, in the conventional device recognition method described with reference to FIG. 6, recognition layers are required for the number of types of devices to be distinguished. However, there is an upper limit to the number of layout layers that can be used in a general layout drawing tool and LSI verification tool. Moreover, in recent years, in LSI design, there is a tendency to miniaturize processes and form various devices on the same chip, and the number of layers used for forming a manufacturing process is increasing, so that many LSIs can be used as recognition layers. However, there is a problem that the number of types of elements to be distinguished is limited.
[0006]
On the other hand, the conventional element recognition method described with reference to FIG. 7 has a problem that the recognition text must always be arranged at the highest hierarchy that can be recognized by the verification tool at the verification level. That is, text is treated as terminal information in a general verification tool. Also, in the hierarchical layout, text as terminal information is arranged in each hierarchical level in order to perform verification at each hierarchical level utilizing the characteristics. Therefore, when recognizing texts in all hierarchies, there is a problem that an error is detected as a plurality of texts as a plurality of terminals on the same node.
[0007]
In order to avoid this problem, in general verification, it is necessary to enable recognition of only the text arranged at the highest level. Therefore, the text for area recognition shown by the conventional element recognition method described with reference to FIG. 7 also needs to be always arranged at the highest hierarchy at the time of verification. However, since the highest hierarchy at the time of verification is not always the same hierarchy depending on the element, text for element recognition which should originally be arranged in a specific area must be arranged in each of the highest hierarchy for each element. In addition, there is a problem that the number of steps is increased.
[0008]
The present invention has been made in view of the above points, and has as its object to provide an element recognition method capable of performing element recognition without depending on the number of elements for which the number of recognition layers is desired to be distinguished.
[0009]
It is another object of the present invention to provide an element recognition method that facilitates data input in hierarchical verification.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method for recognizing an element from input layout data in a layout verification tool for a semiconductor integrated circuit, wherein the layout data has a first element recognition layer and a second element recognition layer. A first step of extracting a recognition pattern based on the number of sides where the graphic of the first element recognition layer and the graphic of the second element recognition layer are in contact with each other, and a second step of distinguishing element regions using the extracted recognition pattern. The method includes the following two steps: a third step of extracting element components included in the element region; and a fourth step of recognizing a transistor including the extracted element components.
Further, the present invention is to achieve the above object, a layout structure but identical, arranged in different shapes shapes depending graphic element recognition layer of elements to be handled as a separate element of the type of the element, the element A first step of extracting a recognition pattern based on the figure shape of the recognition layer, a second step of distinguishing an element region using the extracted recognition pattern, and a third step of extracting an element component included in the element region And a fourth step of recognizing a transistor including the extracted element component. Although the layout structure is the same, a different number of figures having the same shape may be arranged in the element recognition layer of an element to be treated as another element according to the type of the element.
[0012]
Further, in order to achieve the above object, the present invention provides a layout data having an element recognition layer, a first step of extracting a recognition pattern based on the number or area of vertices of a figure in the element recognition layer, A second step of distinguishing an element region by using the following, a third step of extracting an element component included in the element region, and a fourth step of recognizing a transistor including the extracted element component. It is characterized by having.
[0013]
In the present invention, layout data is created by arranging graphic patterns having different numbers of tangent sides, shapes, or numbers according to the type of the same element in two or less recognition layers to generate layout data. Since the data is extracted from the layout data, an arbitrary number of elements can be recognized in two or less recognition layers.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows various pattern diagrams according to an embodiment of the element recognition method according to the present invention. 1A shows a recognition pattern diagram of the transistor N1, FIG. 1B shows a recognition pattern diagram of the transistor N2, and FIG. 1C shows a recognition pattern diagram of the transistor N3. The MOS transistors N1, N2, and N3 have the same layout structure, but have minimum gate lengths of G1, G2, and G3, respectively, and have a different relationship of G1 <G2 <G3.
[0015]
In this embodiment, the transistors N1, N2, and N3 having the same layout structure are recognized as separate elements from the layout data at the time of comparison with a later circuit diagram. Layout data in which a designer arranges a recognition pattern 11 shown in FIG. 1A, a recognition pattern 12 shown in FIG. 1B, and a recognition pattern 13 shown in FIG. 1C according to the minimum gate length of the MOS transistor. Generate The above recognition patterns 11, 12, and 13 are patterned using two recognition layers of an LSI verification tool. That is, a recognition layer A shown in FIG. 2A and a recognition layer B different from the recognition layer A shown by white squares in FIGS. 2B to 2D are used.
[0016]
As shown in FIG. 2B, the first recognition pattern 11 is a pattern in which one recognition layer B is in contact with one recognition layer B and the number of tangent sides is one. As shown in FIG. 2C, the second recognition pattern 12 is a pattern in which the number of tangent sides is two in which one recognition layer B is in contact with each of the left and right sides of one recognition layer A. Furthermore, as shown in FIG. 2D, the third recognition pattern is a pattern in which the number of tangent sides where one recognition layer B is in contact with one recognition layer B on the left, right, and underneath is one.
[0017]
At the LSI logic circuit design stage, when the minimum gate length of the MOS transistor is G1, the designer converts the recognition pattern 11 shown in FIG. 2B on the screen as shown in FIG. By arranging in the region of the transistor N1, data indicating that the number of tangent sides between the two recognition layers A and B is one is input. Similarly, when the minimum gate length of the MOS transistor is G2, the recognition pattern 12 shown in FIG. 2C is arranged in the region of the transistor N2 on the screen as shown in FIG. When data indicating that the number of tangent sides between the two recognition layers A and B is two and the minimum gate length of the MOS transistor is G3, the recognition shown in FIG. By arranging the pattern 13 in the region of the transistor N3 on the screen as shown in FIG. 1C, data indicating that the number of tangent sides between the two recognition layers A and B is three is obtained. The layout data is generated by input.
[0018]
In the logic circuit design stage of the LSI, the characters AREA_1 to AREA_3 and GATE_1 to GATE_3 in FIGS. 1A to 1C are not displayed, and a rectangular area and the above recognition patterns 11 to 13 are displayed. As described above, at the stage of designing the logic circuit of the LSI, the recognition patterns 11 to 13 indicating the types of the transistors are arranged according to the minimum gate length of the MOS transistor. It is easier to distinguish visually than. Moreover, in this embodiment, three types of element recognition can be performed only by the two recognition layers of the recognition layer A and the recognition layer B, and the arrangement position of the recognition layers can be made independent of the hierarchy.
[0019]
Next, after the completion of the LSI logic circuit design, at the time of comparison with a circuit including a transistor, a recognition pattern is extracted from the layout data by using a function of recognizing a feature of a figure shape in an LSI verification tool, and a transistor The operation for performing recognition will be described. The process of calculating the number of tangent sides of the recognition layer is a process provided in a general verification tool.
[0020]
This will be specifically described with reference to the flowchart of FIG. 3 and the graphic of FIG. 2 using a rule file for executing the verification tool. In this embodiment, first, a recognition pattern is extracted from layout data based on the number of sides where different layers are in contact with each other (step 21 in FIG. 3). The SELECT command used for extracting the recognition pattern is expressed in a format of “SELECT A CONDITION BC”. Only the data that matches the condition described in the CONDITION for the data layer B among the data layer A is described. Is performed on the data layer.
[0021]
Hereinafter, a rectangle formed by the recognition layer A is represented by PATTERN_A, and a rectangle formed by the recognition layer B is represented by PATTERN_B. Accordingly, the SELECT command used for the recognition pattern in step 21 is
SELECT PATTERN_A TOUCH [1] PATTERN_B FIG_1 (1-1)
It is represented by TOUCH [1] indicates that the number of tangent sides of the recognition layers A and B is one. (1-1) indicates that PATTERN_A having only one side (TOUCH [1]) in contact with PATTERN_B is set to FIG_1.
[0022]
Similarly, when the second recognition pattern 12 is extracted and the third recognition pattern 13 is extracted, the number of tangent sides of the recognition layers A and B is two or three, respectively.
SELECT PATTERN_A TOUCH [2] PATTERN_B FIG_2 (1-2)
SELECT PATTERN_A TOUCH [3] PATTERN_B FIG_3 (1-3)
, And the respective recognition patterns 12 and 13 are represented as FIG_2 and FIG_3.
[0023]
Subsequently, the element regions are distinguished by using the extracted recognition patterns (Step 22 in FIG. 3). The element regions are distinguished from each other in that the (ENCLOSE) element region (AREA) including the first recognition pattern FIG_1 is AREA_1, the (ENCLOSE) element region (AREA) including the second recognition pattern FIG_2 is AREA_2, and the third recognition is performed. This is performed by setting the element region (AREA) including the pattern FIG_3 (ENCLOSE) to AREA_3. This is represented by the SELECT command as follows.
[0024]
SELECT AREA ENCLOSE FIG_1 AREA_1 (2-1)
SELECT AREA ENCLOSE FIG_2 AREA_2 (2-2)
SELECT AREA ENCLOSE FIG_3 AREA_3 (2-3)
AREA_1, AREA_2, and AREA_3 indicate the areas illustrated in FIGS. 1A, 1B, and 1C.
[0025]
Subsequently, the element components included in the element regions distinguished in step 22 are extracted (step 23 in FIG. 3). In the case of transistor recognition, the following equation
GATE = DIFFUSION AND POLY (3-1)
Is defined as a gate, and the gates included in the element regions AREA_1, AREA_2, and AREA_3 are extracted as GATE_1, GATE_2, and GATE_3, respectively, by the following equation.
[0026]
GATE_1 = AREA_1 AND GATE (3-2)
GATE_2 = AREA_2 AND GATE (3-3)
GATE_3 = AREA_3 AND GATE (3-4)
Lastly, the transistor composed of the element components extracted in step 23 is recognized (step 24 in FIG. 3). An element (ELEMENT) command for element recognition is shown in a format of “ELEMENT NAME abcd”, and defines that an element “NAME” is composed of elements b, c, and d. . “a” describes a device element and needs to be unique to NAME in order to distinguish various elements by this part.
[0027]
In the case of a MOS transistor, a in the above ELEMENT command defines a gate, b defines polysilicon (material of a gate portion), c defines a diffusion layer (material of a source / drain), and d defines a well (material of a bulk portion). There is a need. Therefore, in the case of FIG. 1, the transistors N1, N2, and N3 are recognized by the following ELEMENT command.
[0028]
ELEMENT MOS [N1] GATE_1 POLY DIFFUSION BULK (4-1)
ELEMENT MOS [N2] GATE_2 POLY DIFFUSION BULK (4-2)
ELEMENT MOS [N3] GATE_3 POLY DIFFUSION BULK (4-3)
(4-1) means that the transistor whose gate portion is GATE_1 is recognized as the transistor N1, as shown in FIG. Similarly, (4-2) recognizes that the transistor whose gate portion is GATE_2 is recognized as the transistor N2 as shown in FIG. 1B, and (4-2) shows that the transistor is a transistor N2 as shown in FIG. , And that the transistor whose gate portion is GATE_3 is recognized as the transistor N3.
[0029]
Next, a second embodiment of the present invention will be described. The second embodiment is an element recognition method for distinguishing recognition patterns based on a difference in the number of vertices of a recognition layer using a recognition pattern as shown in FIG. This embodiment is characterized in that only the step 21 in FIG. 3 extracts the element recognition pattern using the recognition pattern shown in FIG. 4, and steps 22 to 24 in FIG. Same as the form.
[0030]
FIGS. 4 (A), (B), (C) and (D) show triangles, squares, pentagons and hexagons with 3, 4, 5 and 6 vertices, respectively, which are shown in FIG. It is used in place of the indicated recognition pattern. Therefore, for example, as a recognition pattern of the transistors N1, N2, and N3, a recognition pattern having a shape shown in FIGS. 4B, 4C, and 4D is used by a designer.
[0031]
The element recognition of the LSI verification tool after the completion of the design is performed according to the flowchart shown in FIG. 3. In this embodiment, the SELECT command used for extracting the recognition pattern in step 21 of FIG. ) When extracting the square recognition pattern
SELECT PATTERN_A VERTEX [4] FIG_4 (5-1)
It is represented by This means that PATTERN_A having four vertices is set to FIG_4. VERTEX [4] indicates that the number of vertices is 4. Similarly, when the pentagonal recognition pattern is extracted in FIG. 4C and the hexagonal recognition pattern is extracted in FIG.
SELECT PATTERN_A VERTEX [5] FIG_5 (5-2)
SELECT PATTERN_A VERTEX [6] FIG_6 (5-3)
And PATTERN_A having five vertices is represented by FIG_5, and PATTERN_A having six vertices is represented by FIG_6.
[0032]
Next, a third embodiment of the present invention will be described. The third embodiment is an element recognizing method that uses a recognition pattern as shown in FIG. 5 to distinguish a recognition pattern based on a difference in the area of a recognition layer. This embodiment is characterized in that only step 21 in FIG. 3 extracts the element recognition pattern using the recognition pattern shown in FIG. 5, and steps 22 to 24 in FIG. Same as the form.
[0033]
FIGS. 5A, 5B and 5C show rectangular recognition patterns having areas 1, 2 and 3, respectively, which are used instead of the recognition patterns shown in FIG. 2 or FIG. . Therefore, for example, as a recognition pattern of the transistors N1, N2, and N3, a recognition pattern having a shape shown in FIGS. 5A, 5B, and 5C is used by a designer.
[0034]
The element recognition of the LSI verification tool after the design is completed is performed according to the flowchart shown in FIG. 3. In this embodiment, the SELECT command used for the recognition pattern in step 21 in FIG. When extracting a recognition pattern of a rectangle with an area of 1,
SELECT PATTERN_A AREA [1.00] FIG_7 (6-1)
It is represented by This means that FIG. 7 has an area of PATTERN_A of 1 (AREA [1.00]). Similarly, when the recognition pattern of the rectangle having the area 2 in FIG. 5B is extracted, and when the recognition pattern of the rectangle having the area 3 in FIG.
SELECT PATTERN_A ARAE [2.00] FIG_8 (6-2)
SELECT PATTERN_A AREA [3.00] FIG_9 (6-3)
Where PATTERN_A has an area of 2 and FIG. 8, and PATTERN_A has an area of 3 as FIG_9.
[0035]
The present invention is not limited to the above embodiment. For example, in the above embodiment, three types of element recognition have been described, but only two recognition layers A and B or one recognition layer A are used. By increasing the number of tangent sides, the number of vertices, or the area, it is possible to recognize four or more types of elements, and the two recognition layers A and B may have overlapping sides and have different shapes. Alternatively, a recognition pattern for performing two or more types of element recognition by changing the number in the same shape can be used. Further, it goes without saying that elements other than MOS transistors can be similarly recognized as elements.
[0036]
【The invention's effect】
As described above, according to the present invention, layout data is created by arranging graphic patterns having different numbers of tangent sides, shapes or numbers according to the type of the same element in two or less recognition layers. By extracting this graphic pattern from the layout data at the time of verification, an arbitrary number of elements can be recognized by two or less recognition layers, which is suitable for an LSI verification tool having an upper limit on the layout layers that can be used. In addition, many types of elements can be recognized without depending on the number of recognition layers.
[0037]
Further, according to the present invention, since the figure pattern is used as the recognition pattern, the arrangement position of the recognition pattern does not depend on the hierarchy, and may be arranged at an arbitrary hierarchy. Compared with the conventional method, the number of steps for arranging the recognition pattern can be reduced, and verification in the hierarchical layout can be easily performed.
[0038]
Further, according to the present invention, since the recognition pattern representing the type of the element by the characteristic of the graphic shape is used, the arrangement of the recognition pattern at the time of creating the layout data is smaller than the conventional method of inserting the recognition layer. Can be visually easily performed, and the efficiency of layout creation can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an element and a recognition pattern recognized by an embodiment of the method of the present invention.
FIG. 2 is an explanatory diagram of a first embodiment of a recognition pattern used in the method of the present invention.
FIG. 3 is a flowchart of an embodiment of the method of the present invention.
FIG. 4 is an explanatory diagram of a second embodiment of a recognition pattern used in the method of the present invention.
FIG. 5 is an explanatory diagram of a third embodiment of a recognition pattern used in the method of the present invention.
FIG. 6 is an explanatory diagram of an example of a conventional method.
FIG. 7 is an explanatory diagram of another example of the conventional method.
[Explanation of symbols]
11, 12, 13 Recognition patterns 21 to 24 Processing steps A, B Recognition layers G1, G2, G3 Gate length

Claims (5)

In a method for recognizing elements from input layout data in a layout verification tool of a semiconductor integrated circuit,
The layout data has a first element recognition layer and a second element recognition layer,
A first step of extracting a recognition pattern based on the number of sides where the figure of the first element recognition layer and the figure of the second element recognition layer are in contact;
A second step of distinguishing an element region using the extracted recognition pattern;
A third step of extracting element components included in the element region;
And a fourth step of recognizing the extracted transistor composed of the element component. 4. A method of recognizing an element from layout data stored in a layout verification tool for a semiconductor integrated circuit. Graphic shapes and the second element recognition layer of said first element recognition layer in the layout verification tool of a semiconductor integrated circuit according to claim 1, wherein each of the same shape, from the input layout data element recognition method. In a method for recognizing elements from input layout data in a layout verification tool of a semiconductor integrated circuit,
The layout structure but identical, arranged in different shapes shapes depending graphic element recognition layer of elements to be treated as a separate element of the type of the element,
A first step of extracting a recognition pattern based on the figure shape of the element recognition layer;
A second step of distinguishing an element region using the extracted recognition pattern;
A third step of extracting element components included in the element region;
And a fourth step of recognizing the transistor composed of the extracted element components. A method for recognizing elements from input layout data in a layout verification tool for a semiconductor integrated circuit. In a method for recognizing elements from input layout data in a layout verification tool of a semiconductor integrated circuit,
The layout data has an element recognition layer,
A first step of extracting a recognition pattern according to the number or area of vertices of the figure in the element recognition layer;
A second step of distinguishing an element region using the extracted recognition pattern;
A third step of extracting element components included in the element region;
And a fourth step of recognizing the transistor composed of the extracted element components. A method for recognizing elements from input layout data in a layout verification tool for a semiconductor integrated circuit. In a method for recognizing elements from input layout data in a layout verification tool of a semiconductor integrated circuit,
The layout structure is the same, but different numbers of the same shape figures are arranged in the element recognition layer of the element to be treated as another element according to the type of the element,
A first step of extracting a recognition pattern based on the number of figures in the element recognition layer;
A second step of distinguishing an element region using the extracted recognition pattern;
A third step of extracting element components included in the element region;
And a fourth step of recognizing the transistor composed of the extracted element components. A method for recognizing elements from input layout data in a layout verification tool for a semiconductor integrated circuit.

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