JP2001292569A - Method for controlling on pulse width of synchronous rectifier in flyback convertor - Google Patents
Method for controlling on pulse width of synchronous rectifier in flyback convertorInfo
- Publication number
- JP2001292569A JP2001292569A JP2000104989A JP2000104989A JP2001292569A JP 2001292569 A JP2001292569 A JP 2001292569A JP 2000104989 A JP2000104989 A JP 2000104989A JP 2000104989 A JP2000104989 A JP 2000104989A JP 2001292569 A JP2001292569 A JP 2001292569A
- Authority
- JP
- Japan
- Prior art keywords
- synchronous rectifier
- pulse width
- coil
- auxiliary coil
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、同期整流方式の
スイッチング電源のうちで、特にフライバック・コンバ
ータにおける制御方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous rectification type switching power supply, and more particularly to a control method for a flyback converter.
【０００２】[0002]
【従来の技術】従来技術によるフライバック・コンバー
タの回路構成は図２に示す通りである。インバータ・ト
ランス１０４の１次側には、１次コイル１０６に直列接
続したスイッチ素子１０３が設けてある。また、２次側
には１次コイル１０６の極性と異なる２次コイル１０７
と補助コイル１０８が直列接続してあり、補助コイル１
０８の一端に接続した抵抗１０１は同期整流器１０２の
ゲート端子に接続してある。同期整流器１０２のドレイ
ン端子は２次コイル１０７と補助コイル１０８との接合
点に接続してあり、ソース端子は２次コイル１０７に並
列接続してある並列コンデンサ１０５の一端に接続して
ある。2. Description of the Related Art The circuit configuration of a flyback converter according to the prior art is as shown in FIG. On the primary side of the inverter / transformer 104, a switch element 103 connected in series to the primary coil 106 is provided. On the secondary side, a secondary coil 107 having a polarity different from that of the primary coil 106 is provided.
And the auxiliary coil 108 are connected in series.
08 is connected to the gate terminal of the synchronous rectifier 102. The drain terminal of the synchronous rectifier 102 is connected to the junction between the secondary coil 107 and the auxiliary coil 108, and the source terminal is connected to one end of a parallel capacitor 105 connected in parallel to the secondary coil 107.
【０００３】[0003]
【発明が解決しようとする課題】上述した同期整流器と
してＭＯＳ−ＦＥＴが用いられており、このＭＯＳ−Ｆ
ＥＴ１０２を補助コイル１０８に設けた抵抗１０１を介
して駆動させると、１次側が自由共振モードの時は２次
側エネルギーが１次側に戻り、ＭＯＳ−ＦＥＴの発振が
安定しなかったりして損失が大きくなる。また、ＭＯＳ
−ＦＥＴのゲート回路における抵抗による抵抗損Ｉ2Ｒ
が生ずるので、駆動電力損も大きくなる。A MOS-FET is used as the above-mentioned synchronous rectifier.
When the ET 102 is driven via the resistor 101 provided in the auxiliary coil 108, when the primary side is in the free resonance mode, the secondary side energy returns to the primary side, and the oscillation of the MOS-FET becomes unstable and the loss is lost. Becomes larger. Also, MOS
-Resistance loss I 2 R due to resistance in gate circuit of FET
, The driving power loss also increases.
【０００４】また、従来方式のフライバック・コンバー
タにおけるＭＯＳ−ＦＥＴのオン期間は負荷変動により
大きく変化するばかりでなく、入力電圧の変動でオン期
間が大幅に変化する欠点があった。In addition, the on-period of the MOS-FET in the conventional flyback converter not only greatly changes due to load fluctuations, but also has the disadvantage that the on-period greatly changes due to fluctuations in the input voltage.
【０００５】[0005]
【課題を解決するための手段】この発明は、上述した従
来技術による欠点を解消するためになされたものであっ
て、インバータ・トランスの２次側に設けた補助コイル
にＭＯＳ−ＦＥＴの駆動を制御する充電回路と放電回路
を設け、負荷の小さい時は充放電コンデンサの放電量は
小さく、負荷が大きい時は放電量を大きくすることによ
り、負荷の変動に対応してＭＯＳ−ＦＥＴのゲートパル
ス幅を追従させるようにした。SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned drawbacks of the prior art. In this invention, an auxiliary coil provided on the secondary side of an inverter transformer drives a MOS-FET. A charge circuit and a discharge circuit for controlling are provided.When the load is small, the discharge amount of the charge / discharge capacitor is small, and when the load is large, the discharge amount is increased. The width is made to follow.
【０００６】さらに、並列コンデンサの放電電圧を一定
にするように、補助コイルの両端に並列接続したダイオ
ードとツエナーダイオードより成る直列回路を設け、入
力電圧の変化に対してほぼ一定幅のゲートパルスを発生
させるようにした。Further, a series circuit composed of a diode and a Zener diode connected in parallel at both ends of the auxiliary coil is provided so as to make the discharge voltage of the parallel capacitor constant, and a gate pulse having a substantially constant width is provided for a change in input voltage. To be generated.
【０００７】[0007]
【発明の実施の形態】以下、この発明の実施例を図面を
参照しながら説明する。図１は、この発明に係る同期整
流方式のフライバック・コンバータの回路構成を示すブ
ロック図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a synchronous rectification type flyback converter according to the present invention.
【０００８】図１において、インバータ・トランス４の
１次側には１次コイル１１に直列接続したスイッチ素子
３が設けてある。また、インバータ・トランス４の２次
側には２次コイル１２に直列接続した補助コイル１３が
設けてあって、２次側コイルの極性は１次側のコイルの
極性と反対である。補助コイル１３の一端には第１のダ
イオード５と第１の抵抗６より成る直列回路が接続して
あり、補助コイル１３と２次コイル１２との接合点と第
１の抵抗６の他端との間には第２のダイオード１４とツ
エナーダイオード１５より成る直列回路が設けてあっ
て、補助コイル１３の両端に並列接続してある。In FIG. 1, a switching element 3 connected in series to a primary coil 11 is provided on the primary side of an inverter transformer 4. On the secondary side of the inverter transformer 4, an auxiliary coil 13 connected in series to the secondary coil 12 is provided, and the polarity of the secondary coil is opposite to the polarity of the primary coil. A series circuit composed of a first diode 5 and a first resistor 6 is connected to one end of the auxiliary coil 13, and a junction between the auxiliary coil 13 and the secondary coil 12, the other end of the first resistor 6, A series circuit including a second diode 14 and a Zener diode 15 is provided therebetween, and is connected in parallel to both ends of the auxiliary coil 13.
【０００９】また、第１の抵抗６の他端と第２のダイオ
ード１４との接合点に一端を接続した第２の抵抗１６の
他端は、補助コイル１３の両端に並列接続するように形
成してある並列コンデンサ７の一端とスイッチ素子１の
ベース端子に接続してあり、さらに、外部電源によって
抵抗を介して並列コンデンサ７を充電する充電回路９
が、並列コンデンサ７の一端とスイッチ素子１のゲート
端子との間に接続してある。スイッチ素子１のエミッタ
端子は２次コイル１２と補助コイル１３との接合点とＭ
ＯＳ−ＦＥＴ２のドレイン端子との間に接続してあり、
さらに、コレクタ端子はバッファ・アンプ１０を介して
ＭＯＳ−ＦＥＴ２のゲート端子に接続してある。なお、
ＭＯＳ−ＦＥＴ２のソース端子は、２次コイル１２の両
端に並列接続した並列コンデンサ８の一端に接続してあ
り、この並列コンデンサ８はＭＯＳ−ＦＥＴ２からの直
流出力を平滑化させる。The other end of the second resistor 16 having one end connected to the junction between the other end of the first resistor 6 and the second diode 14 is formed so as to be connected in parallel to both ends of the auxiliary coil 13. The charging circuit 9 is connected to one end of the parallel capacitor 7 and a base terminal of the switch element 1 and charges the parallel capacitor 7 via a resistor by an external power supply.
Are connected between one end of the parallel capacitor 7 and the gate terminal of the switch element 1. The emitter terminal of the switch element 1 is connected to the junction between the secondary coil 12 and the auxiliary coil 13 by M
Connected between the drain terminal of OS-FET2 and
Further, the collector terminal is connected to the gate terminal of the MOS-FET 2 via the buffer amplifier 10. In addition,
The source terminal of the MOS-FET 2 is connected to one end of a parallel capacitor 8 connected in parallel to both ends of the secondary coil 12, and this parallel capacitor 8 smoothes the DC output from the MOS-FET 2.
【００１０】次に、この発明に係るフライバック・コン
バータにおけるＭＯＳ−ＦＥＴの動作特性を図３と図４
に示す波形図を用いて説明する。図３（ａ）は重負荷時
における動作特性を示し、図３（ｂ）は軽負荷時におけ
る動作特性を示す。また、図４（ａ）は低入力電圧時に
おける動作特性を示し、図４（ｂ）は高入力電圧時にお
ける動作特性を示す。Next, the operation characteristics of the MOS-FET in the flyback converter according to the present invention will be described with reference to FIGS.
This will be described with reference to the waveform diagram shown in FIG. FIG. 3A shows the operation characteristics under a heavy load, and FIG. 3B shows the operation characteristics under a light load. FIG. 4A shows the operating characteristics at a low input voltage, and FIG. 4B shows the operating characteristics at a high input voltage.
【００１１】１次コイル１１に直列接続してあるスイッ
チ素子３のスイッチングに伴って２次側コイルには電圧
が誘起される。２次コイル１２と補助コイル１３の極性
は１次コイル１１と反対であるので、スイッチ素子３が
オフの時に２次コイル１２と補助コイル１３には誘起電
圧ＶNSとＶNS′が発生し、これに伴って２次コイル電流
ＩNSが流れる。重負荷時における誘起電圧ＶNSとＶNS′
は図３（ａ）のとに示す波形となり、２次コイル電
流ＩNSは図３（ａ）のに示す波形となる。１次側が自
由共振モードの時、２次エネルギーが１次側に戻り、発
振が安定しなかったり、損失が大となる。軽負荷時にお
ける誘起電圧波形ＶNSとＶNS′は図３（ｂ）のとに
示すように振動成分を含んだ波形となり、２次コイル電
流ＩNSは図３（ｂ）のに示す波形となる。A voltage is induced in the secondary coil with the switching of the switch element 3 connected in series to the primary coil 11. Since the polarities of the secondary coil 12 and the auxiliary coil 13 are opposite to those of the primary coil 11, the induced voltages V NS and V NS ′ are generated in the secondary coil 12 and the auxiliary coil 13 when the switch element 3 is off, Accordingly, the secondary coil current INS flows. Induced voltages V NS and V NS ′ under heavy load
Figure 3 becomes (a) waveform shown in Noto, the secondary coil current I NS has a waveform shown in FIG. 3 (a). When the primary side is in the free resonance mode, the secondary energy returns to the primary side, and the oscillation becomes unstable or the loss becomes large. The induced voltage waveforms V NS and V NS ′ at the time of light load have waveforms including a vibration component as shown in FIG. 3B, and the secondary coil current INS is different from the waveform shown in FIG. Become.
【００１２】補助コイル１３の誘起電圧波形ＶNS′と充
電回路９からの電荷を並列コンデンサ７を介して入力す
るスイッチ素子１のベース〜エミッタ間電圧ＶBEは、図
３（ａ）と（ｂ）におけるに示す波形となる。スイッ
チ素子１のＶBEがしきい値電圧よりも大きくなるとスイ
ッチ素子１はオンとなり、しきい値電圧より小さい時は
オフとなり、その動作は図３（ａ）と（ｂ）における
に示す波形となる。スイッチ素子１がオンとなるとバッ
ファ・アンプ１０の入力端子電圧が低下するので、ＭＯ
Ｓ−ＦＥＴ２はオフとなる。図３（ａ）と（ｂ）におけ
るはＭＯＳ−ＦＥＴ２からの出力電流ＩQ2を示し、
はボディ・ダイオード電流を示す。3 (a) and 3 (b) show the induced voltage waveform V NS 'of the auxiliary coil 13 and the base-emitter voltage V BE of the switch element 1 to which the charge from the charging circuit 9 is input via the parallel capacitor 7. ). When the V BE of the switch element 1 becomes larger than the threshold voltage, the switch element 1 is turned on, and when it is smaller than the threshold voltage, the switch element 1 is turned off. The operation is as shown in FIGS. Become. When the switch element 1 is turned on, the input terminal voltage of the buffer amplifier 10 decreases.
S-FET2 is turned off. 3A and 3B show an output current IQ2 from the MOS-FET 2 .
Indicates body diode current.
【００１３】フライバック・コンバータにおける２次側
の整流素子から負荷に電流を供給する期間はＭＯＳ−Ｆ
ＥＴ２のオンパルス幅に比例しており、１次側のスイッ
チ素子３に同期している。ＭＯＳ−ＦＥＴ２を駆動させ
るために補助コイル１３を設けてＶNS′波形を生成さ
せ、１次側のスイッチ素子３がオンしている期間に並列
コンデンサ７を放電させ、オフしている期間に充電させ
る。スイッチ素子１のＶBEがしきい値を越えた時にスイ
ッチ素子１をオンとさせ、これに伴ってＭＯＳ−ＦＥＴ
２をオフさせる。重負荷時におけるＭＯＳ−ＦＥＴ２か
らの出力電流ＩQ2は図３（ａ）のに示すように大き
く、軽負荷時におけるＭＯＳ−ＦＥＴ２からの出力電流
は図３（ｂ）のに示すように小さい。即ち、負荷変動
に追従してＭＯＳ−ＦＥＴのオンパルス幅を制御するこ
とができる。The period during which a current is supplied to the load from the rectifier on the secondary side in the flyback converter is MOS-F.
It is proportional to the ON pulse width of ET2 and is synchronized with the primary-side switch element 3. MOS-FET2 auxiliary coil 13 is provided to drive the to produce a V NS 'waveform, to discharge the parallel capacitor 7 during the period when the primary switch element 3 is turned on, charging the period during which the OFF Let it. When the V BE of the switch element 1 exceeds the threshold value, the switch element 1 is turned on, and accordingly, the MOS-FET
Turn 2 off. The output current IQ2 from the MOS-FET 2 under heavy load is large as shown in FIG. 3A, and the output current from the MOS-FET 2 under light load is small as shown in FIG. 3B. That is, the on-pulse width of the MOS-FET can be controlled according to the load fluctuation.
【００１４】次に、入力電圧の変動に伴ってＭＯＳ−Ｆ
ＥＴのオンパルス幅は大きく変化するが、補助コイル１
３の両端に並列に第２のダイオード１４とツエナーダイ
オード１５より成る直列回路を設けておくと、入力電圧
はツエナー電圧によってクランプされるので並列コンデ
ンサ７の放電電圧も一定になる。即ち、１次側のスイッ
チ素子３がオンの時に補助コイル１３に発生するマイナ
ス電圧を第２のダイオード１４とツエナーダイオード１
５によってクランプし、このクランプ電圧で第２の抵抗
１６を介して並列コンデンサ７を定電圧で放電させる。Next, the MOS-F
Although the on-pulse width of ET changes greatly, the auxiliary coil 1
If a series circuit composed of the second diode 14 and the Zener diode 15 is provided in parallel at both ends of 3, the input voltage is clamped by the Zener voltage, so that the discharge voltage of the parallel capacitor 7 becomes constant. That is, the negative voltage generated in the auxiliary coil 13 when the primary-side switch element 3 is turned on is applied to the second diode 14 and the Zener diode 1.
5, and the parallel capacitor 7 is discharged at a constant voltage through the second resistor 16 at the clamp voltage.
【００１５】１次コイル１１への入力電圧が変動した場
合におけるＭＯＳ−ＦＥＴ２の動作特性は、図４（ａ）
と（ｂ）に示す通りである。入力電圧が低い時の２次コ
イル１２と補助コイル１３への誘起電圧は、図４（ａ）
のとに示す波形となり、入力電圧が高い時の波形は
図４（ｂ）のとに示す波形となる。また、２次コイ
ル電流ＩNSは図４（ａ）と（ｂ）におけるに示すよう
になる。第２のダイオード１４とツエナーダイオード１
５より成る直列回路への印加電圧ＶD2-ZD1と、並列コン
デンサ７への印加電圧ＶC1は、図４（ａ）と（ｂ）にお
けるとに示す波形となる。において、（ＶD2＋Ｖ
ZD1）はクランプ電圧を示す。ＶC1はスイッチ素子１の
ベース〜エミッタ間電圧ＶBEに等しいので、スイッチ素
子１のしきい値電圧よりもＶC1が高くなるとスイッチ素
子１はオンとなり、ＭＯＳ−ＦＥＴ２はオフとなる。図
４（ａ）と（ｂ）における，は、スイッチ素子１の
スイッチング動作とＭＯＳ−ＦＥＴ２から送出される電
流波形を示しており、入力電圧の変動に対し、ほぼ一定
のパルス幅を発生していることが判る。はＭＯＳ−Ｆ
ＥＴ２のボディ・ダイオード電流波形を示す。FIG. 4A shows the operating characteristics of the MOS-FET 2 when the input voltage to the primary coil 11 fluctuates.
And (b). The induced voltage on the secondary coil 12 and the auxiliary coil 13 when the input voltage is low is shown in FIG.
4B. The waveform when the input voltage is high is the waveform shown in FIG. Further, the secondary coil current INS is as shown in FIGS. 4A and 4B. Second diode 14 and Zener diode 1
And applied to the serial circuit voltage V D2-ZD1 consisting 5, the applied voltage V C1 to parallel capacitor 7 has a waveform shown in capital in FIGS. 4 and (a) (b). At (V D2 + V
ZD1 ) indicates a clamp voltage. Since V C1 is equal to the base-emitter voltage V BE of the switch element 1, when V C1 becomes higher than the threshold voltage of the switch element 1, the switch element 1 is turned on and the MOS-FET 2 is turned off. 4A and 4B show the switching operation of the switching element 1 and the current waveform sent from the MOS-FET 2, and generate a substantially constant pulse width with respect to the fluctuation of the input voltage. It turns out that there is. Is MOS-F
5 shows a body diode current waveform of ET2.
【００１６】[0016]
【発明の効果】以上説明したように、この発明に係るフ
ライバック・コンバータにおける同期整流器のオンパル
ス幅の制御方法によると、入力電圧の変動が発生した時
もＭＯＳ−ＦＥＴのドライブ期間を一定に制御でき、ま
た負荷変動に対して効率よく同期整流の追従を行わせる
ことができるので、整流損失を低減させた少ない部品点
数で低消費電力化した制御方法を実現できる。As described above, according to the method for controlling the on-pulse width of the synchronous rectifier in the flyback converter according to the present invention, the drive period of the MOS-FET is controlled to be constant even when the input voltage fluctuates. Since synchronous rectification can be efficiently followed in response to load fluctuations, a control method that reduces rectification loss and reduces power consumption with a small number of components can be realized.
【図１】この発明に係るフライバック・コンバータにお
ける同期整流器の回路構成を示すブロック図。FIG. 1 is a block diagram showing a circuit configuration of a synchronous rectifier in a flyback converter according to the present invention.
【図２】従来技術によるフライバック・コンバータにお
ける同期整流器の回路構成を示すブロック図。FIG. 2 is a block diagram showing a circuit configuration of a synchronous rectifier in a conventional flyback converter.
【図３】この発明に係る同期整流器の動作特性を示す波
形図。FIG. 3 is a waveform chart showing operating characteristics of the synchronous rectifier according to the present invention.
【図４】この発明に係る同期整流器の動作特性を示す波
形図。FIG. 4 is a waveform chart showing operating characteristics of the synchronous rectifier according to the present invention.
１ スイッチ素子 ２ ＭＯＳ−ＦＥＴ ３ １次側スイッチ素子 ４ インバータ・トランス ５，１４ ダイオード ６，１６ 抵抗 ７，８ 並列コンデンサ ９ 充電回路 １０ バッファ・アンプ １５ ツエナーダイオード DESCRIPTION OF SYMBOLS 1 Switch element 2 MOS-FET 3 Primary switch element 4 Inverter transformer 5,14 Diode 6,16 Resistance 7,8 Parallel capacitor 9 Charging circuit 10 Buffer amplifier 15 Zener diode
Claims (1)
同期整流器を制御する駆動回路を、２次コイルと同一極
性の補助コイルを２次コイルに直列接続して構成したフ
ライバック・コンバータにおける同期整流器のオンパル
ス幅制御方法において、 補助コイルの一端にカソード端子を接続した第１のダイ
オードと第１および第２の抵抗より成る直列回路を介し
て、補助コイルと２次コイルとの接合点に接続した並列
コンデンサと、 第１と第２の抵抗との中間接続点にカソード端子を接続
した第２のダイオードと、補助コイルと２次コイルとの
接合点にカソード端子を接続したツエナー・ダイオード
との直列回路を補助コイルの両端に並列接続して形成し
たクランプ回路と、 補助コイルと２次コイルとの接合点に接続した同期整流
器のドレイン端子に接続したエミッタ端子と、同期整流
器のゲート端子に接続したバッファ・アンプの入力端に
接続したコレクタ端子と、第２の抵抗と並列コンデンサ
の一端との接続点に接続したベース端子とを備えたスイ
ッチ素子と、 スイッチ素子のベース端子と並列コンデンサの一端との
間に接続した外部電源を入力する充電回路と、 によって同期整流器のオンパルス幅を制御する制御回路
を構成し、 並列コンデンサの充放電電圧をクランプ回路によってク
ランプすることにより、入力電圧の変化に対してほぼ一
定のオンパルス幅を同期整流器から発生させると共に、 負荷が小さい時は並列コンデンサからの放電量を小さく
し、負荷が大きい時は放電量を大きくすることにより、
負荷変動に対し同期整流器を追従させるようにオンパル
ス幅を制御することを特徴とするフライバック・コンバ
ータにおける同期整流器のオンパルス幅の制御方法。1. A synchronous circuit in a flyback converter comprising a drive circuit for controlling a synchronous rectifier provided on the secondary side of an inverter transformer and an auxiliary coil having the same polarity as the secondary coil connected in series to the secondary coil. In an on-pulse width control method for a rectifier, a connection is made to a junction between an auxiliary coil and a secondary coil through a series circuit including a first diode having a cathode terminal connected to one end of the auxiliary coil and first and second resistors. A parallel capacitor, a second diode having a cathode terminal connected to an intermediate connection point between the first and second resistors, and a Zener diode having a cathode terminal connected to a junction between the auxiliary coil and the secondary coil. A clamp circuit formed by connecting a series circuit in parallel to both ends of an auxiliary coil, and a drain of a synchronous rectifier connected to a junction between the auxiliary coil and a secondary coil An emitter terminal connected to the terminal, a collector terminal connected to the input terminal of the buffer amplifier connected to the gate terminal of the synchronous rectifier, and a base terminal connected to a connection point between the second resistor and one end of the parallel capacitor. And a charging circuit connected to an external power supply connected between the base terminal of the switching element and one end of the parallel capacitor, and a control circuit for controlling the on-pulse width of the synchronous rectifier. By clamping the voltage with a clamp circuit, a substantially constant on-pulse width is generated from the synchronous rectifier with respect to changes in the input voltage, and the discharge amount from the parallel capacitor is reduced when the load is small, and when the load is large. By increasing the amount of discharge,
A method of controlling an on-pulse width of a synchronous rectifier in a flyback converter, wherein the on-pulse width is controlled so that the synchronous rectifier follows a load change.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000104989A JP3619115B2 (en) | 2000-04-06 | 2000-04-06 | Control method of on-pulse width of synchronous rectifier in flyback converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000104989A JP3619115B2 (en) | 2000-04-06 | 2000-04-06 | Control method of on-pulse width of synchronous rectifier in flyback converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001292569A true JP2001292569A (en) | 2001-10-19 |
| JP3619115B2 JP3619115B2 (en) | 2005-02-09 |
Family
ID=18618443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000104989A Expired - Fee Related JP3619115B2 (en) | 2000-04-06 | 2000-04-06 | Control method of on-pulse width of synchronous rectifier in flyback converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3619115B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004047278A1 (en) * | 2002-11-19 | 2004-06-03 | Cosel Co., Ltd. | Synchronous rectification switching power supply |
| CN100389535C (en) * | 2002-11-19 | 2008-05-21 | 科索株式会社 | Synchronous rectification switching power supply |
-
2000
- 2000-04-06 JP JP2000104989A patent/JP3619115B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004047278A1 (en) * | 2002-11-19 | 2004-06-03 | Cosel Co., Ltd. | Synchronous rectification switching power supply |
| US7116562B2 (en) | 2002-11-19 | 2006-10-03 | Cosel Co., Ltd. | Synchronous rectification switching power supply |
| CN100389535C (en) * | 2002-11-19 | 2008-05-21 | 科索株式会社 | Synchronous rectification switching power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3619115B2 (en) | 2005-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6788556B2 (en) | Switching power source device | |
| KR100297340B1 (en) | Asymmetry flyback converter | |
| JP3387456B2 (en) | Switching power supply | |
| JP2003088117A (en) | Switching power supply unit | |
| JP2005278263A (en) | Switching power unit | |
| JP3475892B2 (en) | Switching power supply | |
| JPH1189232A (en) | Switching electric power supply equipment | |
| JP2001346379A (en) | Switching power supply apparatus | |
| JP3221185B2 (en) | Switching power supply | |
| US7400519B2 (en) | Switching power supply | |
| JP4210803B2 (en) | Synchronous rectification type DC-DC converter | |
| JP4605532B2 (en) | Multi-output type switching power supply | |
| JP2001333576A (en) | Method of controlling dc-dc converter | |
| JP2001309646A (en) | Switching power unit | |
| JP2004173396A (en) | Synchronous rectification switching power supply | |
| JP3619115B2 (en) | Control method of on-pulse width of synchronous rectifier in flyback converter | |
| JP4201161B2 (en) | Switching power supply | |
| JPH1118426A (en) | Switching power supply circuit | |
| JP4304751B2 (en) | Ringing choke converter with improved turn-on loss | |
| JP3306542B2 (en) | Partially Resonant Self-Excited Switching Power Supply Low Loss Circuit | |
| JP3619116B2 (en) | Synchronous rectifier drive circuit in flyback converter | |
| JPH099615A (en) | Switching power supply apparatus | |
| JPH0767335A (en) | Switching power supply device | |
| JP3595737B2 (en) | Self-excited flyback converter | |
| JPH09271167A (en) | Synchronous rectifier circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040813 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040824 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20041012 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20041111 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071119 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081119 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081119 Year of fee payment: 4 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091119 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091119 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101119 Year of fee payment: 6 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101119 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111119 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131119 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |